Skip to main content

Full text of "Philips-80C51 Based8 Bit Microcontrollers1994OCR"

See other formats


TEGRATED CIRCUITS 



80CS1 -Based 

8-Bit Microcontrollers 




FUTURE ELECTRONICS INC. 

5935 Airport Road, Data Handbook IC20 

Suite 200 

Mississauga, Ontario 
L4V 1W5 

TEL.: (905) 612-9200 
FAX: (905) 612-9185 
TOLL FREE 1-800-268-7948 



Philips 

Semiconductors 



idk mah Ikvup betted 

PHILIPS 



QUALITY ASSURED 



Our quality system focuses on the continuing high quality of our 
components and the best possible service for our customers. We have 
a th ree-sided quality strategy: we apply a system of total quality control 
and assurance; we operate customer-oriented dynamic improvement 
programmes; and we promote a partnering relationship with our 
customers and suppliers. 



PRODUCT SAFETY 

In striving for state-of-the-art perfection, we continuously improve 
components and processes with respect to environmental demands. 
Our components offer no hazard to the environment in normal use 
when operated or stored within the limits specified in the data sheet. 

Somecomponents unavoidably contain substances that, if exposed by 
accident or misuse, are potentially hazardous to health. Users of these 
components are informed of the danger by warning notices in the data 
sheets supporting the components. Where necessary the warning 
notices also indicate safety precautions to be taken and disposal 
instructions to be followed. Obviously users of these components, in 
general the set-making industry, assume responsibility towards the 
consumer with respect to safety matters and environmental demands. 

All used or obsolete components should be disposed of according to 
the regulations applying at the disposal location. Depending on the 
location, electronic components are considered to be 'chemical', 
'special' orsometimes 'industrial' waste. Disposal as domestic waste is 
usually not permitted. 



80C51 -Based 8-Bit Microcontrollers 



CONTENTS 



page 

SECTION 1 GENERAL INFORMATION 1-1 

SECTION 2 80C51 TECHNICAL DESCRIPTION 2-1 

SECTION 3 80C51 FAMILY DERIVATIVES 3-1 

SECTION 4 HIGH PERFORMANCE 1 6-BIT 80C51 XA 

(extended Architecture) 4-1 

SECTION 5 PACKAGE OUTLINES 5-1 

SECTION 6 DATA HANDBOOK SYSTEM 6-1 

APPENDIX A PIN CONFIGURATIONS A-1 



Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make 
changes, without notice, in the products, including circuits, standard cells, and/or software, described 
or contained herein in order to improve design and/or performance. Philips Semiconductors assumes 
no responsibility or liability for the use of any of these products, conveys no license or title under any 
patent, copyright, or mask work right to these products, and makes no representations or warranties 
that these products are free from patent, copyright, or mask work right infringement, unless otherwise 
specified. Applications that are described herein for any of these products are for illustrative purposes 
only. Philips Semiconductors makes no representation or warranty that such applications will be suit- 
able for the specified use without further testing or n 



LIFE SUPPORT APPLICATIONS 

Philips Semiconductors and Philips Electronics North America Corporation Products are not designed 
for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors 
and Philips Electronics North America Corporation Product can reasonably be expected to result in a 
personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers 
using or selling Philips Semiconductors and Philips Electronics North America Corporation Products 
for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors 
and Philips Electronics North America Corporation for any damages resulting from such improper use 
or sale. 



Philips Semiconductors and Philips Electronics North America Corporation register 
eligible circuits under the Semiconductor Chip Protection Act. 



© Copyright Philips Electronics North America Corporation, 1996 



All rights reserved. 
Printed in U.S.A. 



PRODUCT STATUS 



DEFINITIONS 


DATA SHEET IDENTIFICATION 


PRODUCT STATUS 


DEFINITION 


Objective Specification 


Formative or in Design 


This data sheet contains the design target or goal specifications for 
product development. Specifications may change in any manner 
without notice. 


Preliminary Specification 


Preproduction Product 


This data sheet contains preliminary data, and supplementary data will 
be published at a later date. Philips Semiconductors reserves the right 
to make changes at any time without notice in order to improve design 
and supply the best possible product. 


Product Specification 


Full Production 


This data sheet contains Final Specifications. Philips Semiconductors 
reserves the right to make changes at any time without notice, in order 
to improve design and supply the best possible product. 



Purchase of Philips l 2 C components conveys a license under the Philips' l 2 C patent 
. to use the components in the l 2 C system provided the system conforms to the 

Un |2/- :<: , u.. i->u:i: : x : — _ , 



JUn 



l 2 C specifications defined by Philips. This specification can be ordered using the 
code 9398 393 40011. 



Philips Semiconductors 



Preface 



80C51 -Based 

8-Bit Microcontrollers 



Microcontrollers from Philips Semiconductors 

Philips Semiconductors 8 and 16-bit microcontrollers are based on the 
widely-accepted 8048, 8051 and XA architectures. We offer most of the 'industry 
standard' products in these architectures as well as a large selection of powerful 
derivative products. These derivatives offer a wide assortment of features, 
including: additional memory, A/D, PWM, additional timers, DTMF, OSD, OTP, EMC 
and EMI, plus many others. The variety of product derivatives allows Philips 
Semiconductors to support a broad range of functions in consumer, telecom, EDP, 
multi media, automotive and industrial applications. 

For details, see: 

• 8048 'industry standard' architecture types (PCF84CXXX family) in "Dafa 
Handbook IC14". 

The PCD33XX family covers telecom terminal family devices based on the 8048 
core and instruction set, in "Data Handbook IC03". 

• 8051 'industry standard' architecture types in "Data Handbook IC20". 

• XA types in "Data Handbook IC25". 

The Low Power 80CL51 family of derivatives can be found in "Data Handbook 
IC20". These devices operate over the wide voltage range of 1 .8 to 6.0V and are 
ideal for portable and battery operations. 

Many of Philips Semiconductors ICs offer on-board UART serial ports and l 2 C-bus. 
The l 2 C-bus allows easy connection to over 100 other devices, thereby increasing 
system capabilities even further. For automotive and industrial applications, we also 
offer the CAN and the VAN serial bus. The CAN standard, developed by Bosch, 
and VAN concepts offer high noise immunity and error correction. 

Philips Semiconductors 16-bit microcontroller family is based on the XA 
architecture. The XA is upwards compatible with the 80C51 and offers users an 
easy migration path to higher performance. While compatible with the 80C51, this 
compatibility has in no way limited the performance of the XA, which is one of the 
highest performance 16-bit microcontrollers available. 

Philips Semiconductors is developing a family of 32-bit microcontrollers that will be 
based on the MIPS core. This family of microcontrollers will offer advanced 
performance for those applications that are computation and memory intensive in 
an embedded control environment. 



August 1996 



Philips Semiconductors §GCtiOf1 1 

General Information 



80C51 -Based 

8-Bit Microcontrollers 

CONTENTS 

Contents 1-3 

Quality 1-9 

80C51 microcontroller family features guide 1-10 

8051 microcontroller cross-reference guide 1-14 

Low power / low voltage microcontroller family 1-15 

CMOS and NMOS 8-bit microcontroller family 1-16 

CMOS 16-bit microcontroller family 1-20 

Ordering Information 1-21 

FAX-on-DEMAND System 1-23 

Microcontroller internet and bulletin board access 1-24 

80C51 microcontroller development system support 1-26 

8-bit microcontroller demonstration and evaluation boards 1-28 



i-1 



1 



1-2 



Philips Semiconductors 80C51 -Based 8-Bit Microcontrollers 



CONTENTS 



IC20: 80C51-BASED 8-BIT MICROCONTROLLERS 

Preface Hi 

Section 1 - General Information 

Contents 1-3 

Quality 1-9 

80C51 microcontroller family features guide 1-10 

8051 microcontroller cross-reference guide 1-14 

Low power / low voltage microcontroller family 1-15 

CMOS and NMOS 8-bit microcontroller family 1-16 

CMOS 1 6-bit microcontroller family 1-20 

Ordering Information 1-21 

FAX-on-DEMAND System 1-23 

Microcontroller internet and bulletin board access 1-24 

80C51 microcontroller development system support 1-26 

8-bit microcontroller demonstration and evaluation boards 1-28 

Section 2 - 80CS1 Technical Description 

80C51 family architecture 2-3 

80C51 family hardware description 2-18 

80C51 family programmer's guide and instruction set 2-43 

80C51 family EPROM products 2-98 

Section 3 - 80CS1 Family Derivatives 

80C31/80C51/87C51 CMOS single-chip 8-bit microcontrollers 3-3 

83C51FA/83C51FB/ 

83C51 FC/80CS1 FA CMOS single-chip 8-bit microcontrollers 3-25 

87C51FA/87C51FB CMOS single-chip 8-bit microcontrollers 3-61 

87C51FC CMOS single-chip 8-bit microcontroller 3-89 

80CL31/80CL51 Low-voltage single-chip 8-bit microcontrollers 3-117 

87L51FA/87L51FB CMOS single-chip 3.0V 8-bit microcontrollers 3-150 

80C32/87C52 CMOS single-chip 8-bit microcontrollers 3-166 

80C52/80C54/80C58 CMOS single-chip 8-bit microcontrollers 3-188 

87C54/87C58 CMOS single-chip 8-bit microcontrollers 3-215 

83C145; 83C845 

83C055; 87C055 Microcontrollers for TV and video (MTV) 3-236 

80CL41 0/83CL41 Low voltage/low power single-chip 8-bit microcontroller with l 2 C 3-270 

80C451/83C451/87C451 CMOS single-chip 8-bit microcontrollers 3-292 

80C453/83C453/87C453 CMOS single-chip 8-bit microcontrollers 3-311 

83C508/87C508 CMOS single-chip 8-bit microcontrollers 3-334 

P83C524 8-bit microcontroller 3.351 

87C524 CMOS single-chip 8-bit microcontroller 3-372 

80C528/83C528 CMOS single-chip 8-bit microcontrollers 3-392 

87C528 CMOS single-chip 8-bit microcontroller 3-410 

P8xCE528 8-bit microcontroller with EMC 3.430 

80C550/83C550/87C550 CMOS single-chip 8-bit microcontroller with A7D and watchdog timer 3-450 

8XC552/562 overview 3.473 

8XC552 OVERVIEW !!!!!!'.!!!".!!!", 3-473 

83C562 OVERVIEW 3.473 

Differences From the 80C51 3.473 

Program Memory 3.473 

August 1996 1-3 



Philips Semiconductors 80C51 -Based 8-Bit Microcontrollers 




CONTENTS 











Data Memory 3-473 

Special Function Registers 3-473 

Timer T2 3-474 

Timer T3, The Watchdog Timer 3-480 

Serial I/O 3-481 

Reset Circuitry 3-512 

Interrupts 3-513 

I/O Port Structure 3-517 

Port 1 Operation 3-517 

Port 5 Operation 3-517 

Pulse Width Modulated Outputs 3-517 

Analog-to-Digital Converter 3-517 

Power Reduction Modes 3-523 

Memory Organization 3-525 

Single-chip 8-bit microcontroller with 1 0-bit A/D, capture/compare timer, high-speed outputs, PWM . 3-530 

Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM . 3-550 



80C552/83C552 
87C552 
P83CE558/P80CE558/ 



P83CE559/P80CE559 

80C562/83C562 

80C575/83C575/87C575 

83C576/87C576 

P80CL580; P83CL580 

P8XC592 

P8xCE598 

80C652/83C652 

87C652 

83C654 

87C654 

83CE654 

83C748/87C748 

83C749/87C749 

TPM749 

83C750/87C750 

83C751/87C751 



83C754/87C754 
TPM754 

P83CL781;P83CL782 

80C851/83C851 



Single-chip 8-bit microcontroller 3-571 

Single-chip 8-bit microcontroller 3-640 

Single-chip 8-bit microcontroller with 8-bit A/D. capture/compare timer, high-speed outputs, PWM . . 3-708 

CMOS single-chip 8-bit microcontrollers 3-721 

CMOS single-chip 8-bit microcontrollers 3-756 

Low voltage 8-bit microcontrollers 3-798 

8-bit microcontroller with on-chip CAN 3-869 

8-bit microcontroller with on-chip CAN 3-969 

CMOS single-chip 8-bit microcontrollers 3-992 

CMOS single-chip 8-bit microcontroller 3-1010 

CMOS single-chip 8-bit microcontroller 3-1030 

CMOS single-chip 8-bit microcontroller 3-1 048 

CMOS single-chip 8-bit microcontroller with Electromagnetic Compatibility improvements 3-1069 

CMOS single-chip 8-bit microcontrollers 3-1083 

CMOS single-chip 8-bit microcontrollers 3-1095 

Microcontroller with TrackPoint™ microcode from IBM 3-1110 

CMOS single-chip 8-bit microcontrollers 3-1119 

CMOS single-chip 8-bit microcontrollers 3-1129 

CMOS single-chip 8-bit microcontroller with A/D, PWM 3-1147 

CMOS single-chip 8-bit microcontrollers 3-1165 

Microcontroller with TrackPoint™ microcode from IBM 3-1187 

Low voltage 8-bit microcontrollers 3-1195 

CMOS single-chip 8-bit microcontroller with on-chip EEPROM 3-1 251 



Section 4 - High Performance 1 6-bit 80C51 XA (extended Architecture) 

80C51XA Architectural overview 4-3 

XA-G1 CMOS single-chip 16-bit microcontroller 4-13 

XA-G2 CMOS single-chip 1 6-bit microcontroller 4-14 

XA-G3 CMOS single-chip 1 6-bit microcontroller 4-15 

XA-C3 CMOS single-chip 1 6-bit microcontroller with CAN/DeviceNet controller 4-16 

XA-S3 Single-chip 16-bit microcontroller 4-17 



August 1996 



Philips Semiconductors 80C51 -Based 8-Bit Microcontrollers 



CONTENTS 



Section 5 -Package Outlines 

Soldering Package information 5-2 

Plastic Dual In-Line Package 

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 .... 5-4 

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1 ... 5-5 

DIP28: plastic dual in-line package; 28 leads (600 mil); long body SOT117-2... 5-6 

DIP40; plastic dual in-line package; 40 leads (600 mil) SOT129-1 ... 5-7 

Plastic Shrink Dual In-Line Package 

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 ... 5-8 

SDIP64; plastic shrink dual in-line package; 64 leads (750 mil) SOT274-1 ... 5-9 

Ceramic Dual In-Line Package 

24-Pin (300 mils wide) Ceramic Dual In-line (F) Package (with Window (FA) Package) 0586B 5-10 

28-Pin (600 mils wide) Ceramic Dual In-line (F) Package (with Window (FA) Package) 0589B 5-11 

40-Pin (600 mils wide) Ceramic Dual In-line (F) Package (with Window (FA) Package) 0590B 5-12 

Plastic Leaded Chip Carrier 

PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3 ... 5-13 

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 ... 5-14 

PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 ... 5-15 

PLCC68: plastic leaded chip carrier; 68 leads; pedestal SOT188-3 ... 5-16 

Ceramic Leaded Chip Carrier 

68-Pin Chip Carrier, J-Bend (L) Package 1240C 5-17 

Ceramic leaded chip carrier (window); 68 leads NO330 5-18 

Plastic Quad Flat Package 

QFP44: plastic quad flat package; 44 leads (lead length 1.3mm); body 10x 10 x 1.75mm SOT307-2 ... 5-19 

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14x14x2.2 mm SOT205-1 ... 5-20 

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm SOT389-1 ... 5-21 

QFP64: plastic quad flat package; 64 leads (lead length 2.35 mm); body 1 4 x 20 x 2.75 mm SOT208-1 5-22 

QFP64; plastic quad flat package; 64 leads (lead length 1.95mm); body 14 x 20 x 2.8 mm SOT319-2 ... 5-23 

QFP80; plastic quad flat package; 80 leads (lead length 1.6 mm); body 14x20x3.0 mm SOT310-1 ... 5-24 

QFP80: plastic quad flat package; 80 leads (lead length 1 .95 mm); body 1 4 x 20 x 2.7 mm; 

high stand-off height SOT318-1 ... 5-25 

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14x20x2.8 mm SOT318-2... 5-26 

Ceramic Quad Flat Package 

44-pin CerQuad J-Bend (K) Package 1472A 5-27 

68-pin CerQuad J-Bend (K) Package 1473A 5-28 

Plastic Small Outline Package 

S08; plastic small outline package; 8 leads; body width 3.9mm SOT96-1 .... 5-29 

S028: plastic small outline package; 28 leads; body width 7.5mm SOT1 36-1 ... 5-30 

VSO40: plastic very small outline package; 40 leads SOT158-1 5-31 

VS056: plastic very small outline package; 56 leads SOT190-1 ... 5-32 

Plastic Shrink Small Outline Package 

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 . . . 5-33 

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT341 -1 5-34 

Section 6 - Data Handbook System R ., 

Data handbook system 6-2 

Appendix A - Pin Configurations 



A-1 



August 1996 1-5 



Philips Semiconductors 80C51-Based 8-Bit Microcontrollers 



CONTENTS 



APPLICATION NOTES AND DEVELOPMENT TOOLS FOR 80C51 MICROCONTROLLERS 



Preface , iii 

Section 1 - General Information 

Contents,.... 1-3 

Quality , 1-9 

80C51 microcontroller family features guide 1-10 

8051 microcontroller cross-reference guide 1-14 

Low power / low voltage microcontroller family 1-15 

CMOS and NMOS 8-bit microcontroller family 1-16 

CMOS 1 6-bit microcontroller family 1-20 

Ordering Information 1-21 

FAX-on-DEMAND System 1-23 

Microcontroller internet and bulletin board access 1-24 

80C51 microcontroller development system support 1-26 

8-bit microcontroller demonstration and evaluation boards 1-28 

Section 2 - 80C51 Support Chips 

PCF1252-X family Threshold detector and reset generator 2-3 

Section 3 - Inter-Integrated Circuit (l 2 C) Bus 

The l 2 C-bus and how to use it 3-3 

l 2 C peripheral selection guide 3-27 

82B715 l 2 C bus extender 3-29 

Section 4 - l 2 C Serial Bus Application Notes & Articles 

AN422 Using the 8XC751 microcontroller as an l 2 C bus master 4-3 

AN425 Interfacing the PCF8584 l 2 C-bus controller to 80C51 family microcontrollers 4-21 

AN430 Using the 8XC751/752 in multimaster l 2 C applications 4-40 

AN433 l 2 C slave routines for the 83C751 4-76 

AN434 Connecting a PC keyboard to the l 2 C-bus 4-82 

AN438 l 2 C routines for 8XC528 4-100 

AN444 Using the P82B71 5 l 2 C extender on long cables 4-1 22 

AN452 One mile long l 2 C communication using the P82B71 5 4-1 42 

ETV/AN89004 PLM51 l 2 C software interface IIC51 (version 0.5) 4-149 

EIE/AN91007 l 2 C driver routines for 8XC751/2 microcontrollers 4-158 

Exploring l 2 C 4-212 

Programming the l 2 C interface 4.215 

Section 5 - 87C750, 8XC751 , 8XC752 Application Notes 

AN422 Using the 8XC751 microcontroller as an l 2 C bus master See Section 4 

AN423 Software driven serial communication routines for the 83C751 and 83C752 microcontrollers 5-3 

AN426 Controlling air core meters with the 87C751 and SA5775 5-8 

AN427 Timer I for the 83/87C748/749 and the 83/87C751/752 (non-l 2 C applications) microcontrollers 5-22 

AN428 Using the ADC and PWM of the 83C752/87C752 5-28 

AN429 Airflow measurement using the 83/87C752 and "C" 5.35 

AN430 Using the 8XC751/752 in multimaster l 2 C applications See Section 4 

AN433 l 2 C slave routines for the 83C751 See Section 4 

AN436 "Opti-Mizer" power management for notebook computers using the 8XC752 microcontroller 5-54 

AN439 87C751 fast NiCad charger 5^4 

August 1996 1-6 



Philips Semiconductors 80C51 -Based 8-Bit Microcontrollers 



CONTENTS 



AN442 
AN446 
AN453 
AN454 



(BCM) 87C751 Specification for a bus-controlled monitor 5-76 

A software duplex UART for the 751/752 5-93 

Using the 87C751 microcontroller to gang program PCF8582/PCF8581 EEPROMs 5-101 

Interfacing the 83C576/87C576 to the ISA bus 5-120 



EIE/AN91007 l 2 C driver routines for 8XC751/2 microcontrollers 



See Section 4 



Section 6 - 80C51 Application Notes & Articles 



AN408 
AN417 
AN418 
AN420 
AN424 
AN440 
AN443 
AN447 
AN448 
AN449 
AN455 
AN456 
AN457 
ESG89001 
EIE/AN91001 
EIE/AN91006 
EIE/AN91009 
EIE/AN92001 
EIE/AN93017 



Counter/timer 2 of the 83C552 microcontroller 
Using up to 5 external interrupts on 80C51 *~ 



80C451 operation of port 6 6-3 

256k Centronics printer buffer using the 87C451 microcontroller 6-14 

6-27 

6-34 

8051 family warm boot determinations 6-36 

RAM loader program for 80C51 family applications 6-38 

IEEE Micro Mouse using the 87C751 microcontroller 6-47 

Automatic baud rate detection for the 80C51 6-68 

Determining baud rates for 8051 UARTs and other UART issues 6-71 

Measure resistance and capacitance without an A/D 6-74 

Incircuit programming of the Philips 87C576 microcontroller 6-87 

Using LC oscillator circuits with Philips microcontrollers 6-92 

80C51 External Memory Interfacing 6-94 

Electro magnetic compatibility and printed circuit board (PCB) constraints 6-112 

Workbench EMC evaluation method 6-131 

A/D conversion with P83CL41 PCF1 252-x 6-1 48 

Driver for 8xC851 E2PROM 6-164 

Low RF-emission applications with a P83CE654 microcontroller 6-179 



Using the analog-to-digital converter of the 8XC552 microcontroller 

Chips push CAN bus into embedded world 

Add Text Overlay to Any Video Display 

Section 7 - Control Area Network (CAN) Bus 

Control Area Network (CAN) overview 

P82C150 CAN Serial Linked I/O device (SLIO) with digital and analog port functions 



6-191 
6-209 
6-211 



7-3 
7-4 



82C200 



Stand-alone CAN-controller 7-33 



CAN controller interface . 



7-69 



Section 8 - Development Support Tools 

Development support tools 8-3 

Advin Systems, Inc.: PILOT-MVP Universal Programmer 8-16 

Aisys Ltd.: DriveWay™-51 Device Drivers Code Generation Tool 8-17 

Archimedes Software, Inc.: IDE-8051 Integrated Development Environment 8-18 

Ashling: CTS51 Microprocessor Development Systems for Philips Microcontrollers 8-19 

Avocet Systems, Inc.: AvCase51 Complete Embedded Software Development 8-24 

BSO/Tasking: The total development solution for the 8051 family 8-25 

Cactus Logic: Integrated Debugging System/LC (IDS/LC™) 8-34 

CEIBO: DS-51 Microprocessor Development System 8-35 

EB-51 Emulation Board 8-43 

DB-51 Development Board 8-47 

DS-750 Microcontroller Development Tool 8-49 

DS-752 In Circuit Emulator 8-51 

MP-51 Programmer 8-53 

ChipTools, Inc.: ChipView^-SI High-Level/Low-Level Debugger 8-55 

CMX Company: CMX-RTX™, CMX-TINY™, CMX-TINY+™ 

Real-Time Multi-Tasking Operating System for Microprocessors and Microcomputers 8-56 

August 1996 1-7 



Philips Semiconductors 80C51 -Based 8-Bit Microcontrollers 



CONTENTS 



Emulation Technology, Inc.: ET-iC2000 8051 Real-Timer In-Circuit OpenEmulator 8-57 

8051 Emulator Adapters, Test Clips and Accessories 8-58 

Franklin Software, Inc.: 8051 Software Development Tool Suites 8-59 

ProView— 8051 Turbo Tools 8-61 



C51 C Language Compiler Kit for the Professional User 8-65 

DK51— Complete 8051 Developers Kit 8-66 

PK51— The Professional 8051 Developers Kit 8-67 

HiTech Equipment Corp: DrylCE 8051 Family In-Circuit Emulators 8-68 

Hitex: teletest51 In-Circuit Emulators 8-69 

IAR Systems: 8051 Embedded Workbench for Windows 8-70 

C-SPY 8051 for Windows 8-71 

Lauterbach: TRACE32 ICE-51 ' 8-72 

Logical Systems: 8051 Family Programming Adapters and Socket Adapters 8-73 

MetaLink Corporation: iceMASTER-PE™ 8051 Family In-Circuit Emulator 8-74 

iceMASTER™ 8051 In-Circuit Emulators 8-79 

Microtek International, Inc.: EasyPack8051 Family In-Circuit Emulator 8-92 

EasyPack 8052F In-Circuit Emulator 8-95 

Nohau Corporation: EMUL51-PC 8-97 

EMUL51 -PC- PC-based in-circuit emulator 8-99 

Raisonance: PCE-51 Real-Time In-Circuit Emulator 8-110 

RamtexA/S: STIMGATE® Target Controller for ANSI-C 8-111 

Signum Systems: USP-51 In-Circuit Emulator 8-112 

Systronix®, Inc.: BCI51 Pro/Dallas Development Board 8-113 

PDS51 Development System for 8XC51 Microcontroller Derivatives 8-114 

LCP Family of Programmers for 87C51 and Derivatives f 8-118 

S87C0OKSD 8XC51 and l 2 C Bus Evaluation Board I 8-121 

OM4130 CAN evaluation board with the 8XC552 and 82C200 CAN controller 8-122 

OM4239 CAN evaluation board with the 8XC592 microcontroller 8-123 

OM4240 Evaluation board for the 8XCE598 microcontroller 8-124 

OM4272 SLIO evaluation board with the 82C150 and 82C250 CAN ICs 8-125 

OM4280 P83C852 Smart Card crypto-controller demonstration kit 8-126 

PEB552 Evaluation board 8-127 

Section 9 - Data Handbook System 9_2 



■ 



August 1996 



1-8 



mm 



General 



Quality 



— 



TOTAL QUALITY MANAGEMENT 

Philips Semiconductors is a Quality Company, renowned 
for the high quality of our products and service. We keep 
alive this tradition by constantly aiming towards one 
ultimate standard, that of zero defects. This aim is guided 
by our Total Quality Management (TQM) system, the 
basis of which is described in the following paragraphs. 

Quality assurance 

Based on ISO 9000 standards, customer standards such 
as Ford TQE and IBM MDQ. Our factories are certified to 
ISO 9000 by external inspectorates. 

Partnerships with customers 

PPM co-operations, design-in agreements, ship-to-stock, 
just-in-time and self-qualification programmes, and 
application support. 

Partnerships with suppliers 

Ship-to-stock, statistical process control and ISO 9000 
audits. 



Quality improvement programme 

Continuous process and system improvement, design 
improvement, complete use of statistical process control, 
realization of our final objective of zero defects, and 



logistics improvement by ship-to-stock and just-in-time 
agreements. 



ADVANCED QUALITY PLANNING 

During the design and development of new products and 
processes, quality is built-in by advanced quality 
planning. Through failure-mode-and-effect analysis the 
critical parameters are detected and measures taken to 
ensure good performance on these parameters. The 
capability of process steps is also planned in t 



PRODUCT CONFORMANCE 

The assurance of product conformance is an integral part 
of our quality assurance (QA) practice. This is achieved 
by: 

• Incoming material management through partnerships 
with suppliers. 

• In-line quality assurance to monitor process 
reproducibility during manufacture and initiate any 
necessary corrective action. Critical process steps are 
100% under statistical process control. 

• Acceptance tests on finished products to verify 
conformance with the device specification. The test 
results are used for quality feedback and corrective 
actions. The inspection and test requirements are 
detailed in the general quality specifications. 

• Periodic inspections to monitor and measure the 
conformance of products. 



PRODUCT RELIABILITY 

With the increasing complexity of Original Equipment 
Manufacturer (OEM) equipment, components reliability 
must be extremely high. Our research laboratories and 
development departments study the failure mechanisms 
of semiconductors. Their studies result in design rules 
and process optimization for the highest built-in product 
reliability. Highly accelerated tests are applied to the 
product reliability evaluation. Rejects from reliability tests 
and from customer complaints are submitted to failure 
analysis, to result in corrective action. 



CUSTOMER RESPONSES 

Our quality improvement depends on joint action with our 
customer. We need our customer's inputs and we invite 
constructive comments on all aspects of our performance. 
Please contact our local sales representative. 



RECOGNITION 

The high quality of our products and services is 
demonstrated by many Quality Awards granted by major 
customers and international organizations. 



1995Mar21 



1-9 



Philips Semiconductors 

^ — 

80C51 microcontroller family features guide 



Part Number 
(ROMIess) 




Counter 
Timers 


I/O 
Port 


Serial 
Interfaces 


External 
Interrupt 


Comments/ 
Special Features 


ROM 


EPRM 


RAM 


p 


B3C750 


1K 




64 


1 (16-bit) 


2-3/8 




2 


40 MHz, Lowest cost, SSOP 


P 


870750 




1K 


64 


1 (16-bit) 


2-3/8 




2 


40 MHz, Lowest cost, SSOP 


P 


83C748 


■ 2K 




64 


1 (16-bit) 


2-3/8 


- 


2 


8XC751 w/o K=C, SSOP 


P 


87C748 




2K 


64 


1 (16-bit) 


2-3/8 


- 


2 


8XC751 w/o l 2 C, SSOP 


S 


83C751 


2K 




64 


1 (16-bit) 


2-3/8 


I 2 C (bit) 


2 


24-pin Skinny DIP, SSOP 


s 


87C751 




2K 


64 


1 (16-bit) 


2-3/8 


l 2 C (bit) 


2 


24-pin Skinny DIP, SSOP 


P 


83C749 


2K 




64 


1 (16-bit) 


2-5/8 




2 


8XC752 w/o l 2 C, SSOP 


p 


87C749 




2K 


64 


1 (16-bit) 


2-5/8 




2 


8XC752 w/o l 2 C, SSOP 


s 


83C752 


2K 




64 


1 (16-bit) 


2-5/8 


l 2 C (bit) 


2 


5 Channel 8-bit A/D, PWM Output, SSOP 


s 


87C752 




2K 


64 


1 (16-bit) 


2-5/8 


l 2 C (bit) 


2 


5 Channel 8-bit A/D, PWM Output, SSOP 


sc 


80CM (80C31) 


4K 




128 


2 


4 


UART 


2 


CMOS (Sunnyvale) 




oUOO 1 (oUL-dl ) 


4K 




128 


2 


4 


UART 


2 


CMOS (Hamburg) 












2 


4 


UART 


2 


CMOS 




oUL/Lol (OUULol J 


4K 






2 




UART 


10 


I nw Vnltartfi M RV tn fiVl I nw Pnwpr 
luw vuiifiyc ^ i - O v iv ovj, luw ruwct 






4K 






2 




l 2 C 


10 


I nw Vnltanp M RV tn fiVl I nw Pnwpr 
i_uw v uiiciyc i i .o v tuov], i_uw rywci 




OO/^yl EH 1 Qn/"M G -t \ 

ooL<4oi [oU04ol) 


4K 




128 






UART 




Extended I/O, Processor Bus Interface 




87C451 




4K 


128 










Extended I/O, Processor Bus Interface 




oJOooU (oOOooU) 


4K 




128 


2 + Watchdog 




uThT 








87C550 




4K 


128 


2 + Watchdog 




UART 




rhann = i fl nil £iIP\ 
O \ji\a\H IfcJI O-Ull r\l \J 






4K 




128 










•.out) ctrnL^ivi, ouL^oi rin cornpatiuie 


p 




6K 




256 


2 (16-bit) 


2/8 




1 


smart Tod c erc" Ph icc^sr (Da,a ' 


p 


83CL580 (80CL580) 


6K 




256 


3 + Watchdog 


5 


UART, l 2 C 


9 


4 Channel 8-bit A/D, PWM Output, 
Low Voltage (2.5V to 6V), Low Power 


p 


80C52 (80C32) 


-8K- 




256 


3 


4 


UART 


2 


80C51 Pin Compatible 


p 


87C52 




8K 


256 


3 


4 


UART 


2 


(see above) 


p 


83C652 (80C652) 


8K 




256 


2 


4 


UART, |2C 


2 


80C51 Pin Compatible 


s 


87C652 




8K 


256 


2 


4 


UART, |2C 


2 


(see above) 


p 


B3C453 (80C453) 


8K 




256 


2 


7 


UART 


2 


Extended t/O, Processor Bus Interface 


p 


87C453 




8K 


256 


2 


7 


UART 


2 


Extended I/O, Processor Bus Interface 


s 


83C51FA(80C51FA) 


8K 




256 


3 + PCA 


4 


UART 


2 


Enhanced UART, 3 timers + PCA 


s 


87C51 FA 




8K 


256 


3 + PCA 


4 


UART 


2 


Enhanced UART, 3 timers + PCA 


s 


83L51FA 


8K 




256 


3 + PCA 


4 


UART 


2 


Low Voltage 83C51 FA (3V @ 20MHz) 


s 


87L51 FA 




8K 


256 


3 + PCA 


4 


UART 


2 


Low Voltage OTP 87C51 FA (3V @ 20MHz) 


p 


83C575 (80C575) 


8K 




256 


3 + PCA+ 
Watchdog 


4 


UART 


2 


High Reliability, with Low Voltage Detect, 
OSC Fail Detect, Analog Comparators, PCA 


p 


37C575 




BK 


256 


(see above) 


4 


UART 


2 


(see above) 


p 


83C576 (80C576) 


8K 




256 


3 + PCA+ 
Watchdog 


4 


UART 


2 


Same as 8XC575 plus UPI and 10-bit A/D 


p 


87C576 




8K 


256 


(see above) 


4 


UART 


2 


(see above) 


PC 


83C562 (80C562) 


8K 




256 


3 + Watchdog 


6 


UART 


2 


8 Channel 8-bit A/D, 2 PWM Outputs, 
Capture/Compare Timer 


PCX 


83C552 (80C552) 


8K 




256 


3 + Watchdog 


6 


UART, l 2 C 


2 


8 Channel 10-bit A/D, 2 PWM Outputs, 
Capture/Compare Timer 


s 


87C552 




8K 


256 


3 + Watchdog 


6 


UART, l 2 C 


2 


(see above) 



Notes: Part number prefixes are noted in the first column. 

All combinations of part type, speed, temperature and package may not be available. 



July 1996 



1-10 



Philips Semiconductors 



80C51 microcontroller family features guide 





Part Number 
(ROMIess) 


Program 
Security? 


Clock Frscj 
(MHz) 


Temperature Ranges ( C) 


| PacTS 


)6 


Oto 70 


-40 to +85 


-55 to +125 


PDIP 


CDIP 


PLCC 


CLCC 


PQFP/SSOP 


83C750 


5 


N 


3.5 to 40 


X 


X 




N24 


F24 


A28 




DB24 (0-70F) 


87C750 


s 


Y 


3.5 to 40 


X 


X 




N24 


F24 


A28 




DB24 (0-70F) 


83C748 


s 


N 


3.5to16 


X 


X 




N24 




A28 




DB24 (0-70F) 


87C748 


s 


Y 


3.5to16 


X 


X 




N24 


F24 


A28 




DB24 (0-70F) 


83C751 


s 


N 


3.5to16 


X 


X 




N24 




A28 




DB24 (0-70F) 




87C751 


3 


Y 


3.51016 


X 


X 




N24 


F24 


A28 




DB24 (0-70F) 




83C749 




N 


3.5 to 16 


X 


X 




N28 




A28 




DB28 (0-70F) 


87C749 


s 


Y 


3.510 16 


X 


X 




N28 


F28 


A28 




DB28 (0-70F) 


83C752 


s 


N 


3.5 to 16 


X 


X 


X 






A28 




DB28 (0-70F) 


87C752 


s 


Y 


3.510 16 


X 














DB28 (0-70F) 


SC80C51 (80C31) 


s 


Y 


3.5 to 33 


X 


X 


X 


N40 




A44 




B44 (5) 


| PCx80C51 (80C31) 


H 


N 


1 .2 to 30 


X 


X 


X 


P(40) 




WP(44) 




H(44) 




87C51 


s 


Y 


3.5 to 33 


X 


X 


X 


N40 


F40 


A44 


K44 


B44(5) 




80CL51 (80CL31) 


z 


N 


Oto 16(1) 




X 




N40 (2) 








B44 


83CL410{80CL410) 


z 


N 


to 12(1) 




X 




N40 (2) 








B44 


83C451 (80C451) 


s 


N 


3.5 to 16 


X 


X 


X 


N64(4) 




A68 






87C451 


s 


Y 


3.5to16 


X 


X 


X 


N64(4) 




A68 






83C550 (80C550) 


s 


Y 


3.5 to 16 


X 


X 




N40 




A44 






87C550 


s 


Y 


3.5 to 16 


X 


X 


-40 to +125 


N40 


F40 


A44 


K44 




83C851 (80C851) 


H 


Y 


1.2 to 16 


X 


X 




N40 




A44 




B44 




83C852 






1 10 12 


X 






S028 
or die 












83CL580 (80CL580) 


z 


N 


to 12 (1) 




X 




(3) 








B64 


80C52 (80C32) 


s 


Y 


3.5 to 24 


X 


X 




N40 




A44 




B44(5) 


87C52 


s 


Y 


3.5 to 24 


X 


X 


X 


N40 


F40 


A44 


K44 


B44 (5) 


B3C652 (80C652) 


H 


Y 


1 .2 to 24 


X 


X 


-4010+125 


N40 




A44 




B44 


87C662 


s 


Y 


1.2 to 20 


X 


X 


X 


N40 


F40 


A44 


K44 




83C453 (80C453) 


s 


N 


3.5 to 16 


X 


X 








A68 








87C453 


s 


Y 


3.5to16 


X 


X 








A68 






83C51 FA (80C51 FA) 


s 


Y 


3.5 to 24 


X 


X 




N40 








B44 


87C51FA 


s 


Y 


3.5 to 24 


X 


X 






F40 


A44 


K44 


B44 


83L51FA 


s 


y 




x 














B44 


87L51FA 


s 


y 


J.O IU £M 


X 


X 




N40 


F40 


A44 


K44 


B44 


83C575 (80C575) 


s 


Y 


4 to 16 


X 




X 


N40 




A44 




B44 


87C575 


s 


Y 


410 16 


X 




X 


N40 


F40 


A44 


K44 


B44 


83C576 (80C576) 


s 


Y 


410 16 


X 




X 


N40 




A44 




B44 


87C576 


s 


Y 


4 to 16 


X 




X 


N40 


F40 


A44 


K44 


B44 


83C562 (80C562) 


H 


N 


1.2 to 16 


X 


X 


-4010+125 






A68 




B80 


83C552 (80C552) 


H 


N 


1.210 30 


X 


X 


-40 to +125 






A68 




B80 


87C552 


S 


Y 


1.210 16 


X 










A68 


K66 





Notes: Production Centers are indicated in the second column: H - Hamburg, S - Sunnyvale, Z - Zurich. 
All combinations of part type, speed, temperature and package may not be available. 

1 ) Oscillator options start from 32kHz. 

2) Also available in VSO40 package. 

3) Also available in VS056 Package. 

4) Not recommended for new design. 

5) Package available up to 16 MHz only. 



July 1996 



Philips Semiconductors 



80C51 microcontroller family features guide 



Part Number 
(ROMIess) 


Memory 


Counter 
Timers 


I/O 
Port 


Serial 
Interfaces 


External 
Interrupt 


Comments/ 
Special Features 


ROM 


EPRM 


RAM 


p 


83C055 


16K 




256 


2 (1o-bit) 


3 1/2 




2 


On-Screen Display, 9 PWM Outputs, 
3 Software A/D Inputs 


p 


87C055 




16K 


256 


2 (16-bit) 


3 1/2 


_ 


2 


(see above) 


p 


80C54 


16K 




256 


3 


4 


UART 


2 


Standard; 80C51 compatible 



p 


87C54 




16K 


256 


3 


4 


UART 


2 


Standard; 87C51 compatible 


p 


83C654 


16K 




256 


2 


4 


UART, l 2 C 


2 


80C51 Pin Compatible 


s 


87C654 




16K 


256 


2 


4 


UART, l 2 C 


2 


(see above) 


p 


83CE654 


16K 




256 


2 


4 


UART, l 2 C 


2 


83C654 with Reduced EMI 


p 


83CL781 


16K 




256 


3 


4 


UART, l 2 C 


10 


Low Voltage (1 .8V to 6V), Low Power 


p 


83CL782 


16K 




256 


3 


4 


UART, l 2 C 


10 


83CL781 Optimized 12MHz 8 3.1V 


s 


83C51FB 


16K 




256 


3 + PCA 


4 


UART 


2 


Enhanced UART, 3 timers + PCA 


s 


87C51 FB 




16K 


256 


3 + PCA 


4 


UART 


2 


Enhanced UART, 3 timers + PCA 


s 


83L51FB 


16K 




256 


3 + PCA 


4 


UART 


2 


Low Voltage 83C51 FB (3V Q 20MHz) 


s 


87L51FB 




16K 


256 


3 + PCA 


4 


UART 


2 


Low Voltage OTP 87C51 FB (3V @ 20MHz) 


p 


83C524 


16K 




512 


3 + Watchdog 


4 


UART, l^-bit 


2 


512 RAM 




87C524 




16K 


512 


3 + Watchdog 


4 


UART, l^-bit 


2 


512 RAM 




83C592 (80C592) 


16K 






3 + Watchdog 


6 


UART, CAN 


6 


CAN Bus Controller with 8 x 10-bit A/D, 
2 PWM outputs, Capture/Compare Timer 








16K 


512 


3 + Watchdog 


6 


UART, CAN 


6 


(see above) 




80C58 


32 K 




256 


3 


4 


UART 


2 


Standard; 80C51 compatible 


p 


87C58 




32K 


256 


3 


4 


UART 


2 


Standard; 87C51 compatible 


s 


83C51FC 


32K 




256 










Enhanced UART, 3 timers + PCA 


s 


87C51 FC 




32K 


256 


3 + PCA 


4 


UART 


2 


Enhanced UART, 3 timers + PCA 


p 


83C528 (80C528) 


32K 




512 


3 + Watchdog 


4 


UART, l^-bit 


2 


Large Memory for High Level Languages 


p 


87C528 




32K 


512 


3 + Watchdog 


4 


UART, l^-bit 


2 


Large Memory for High Level Languages 


p 


83CE528 (80CE528) 


32K 




512 


3 + Watchdog 


4 


UART, l 2 C-bit 


2 


8XC526 with Reduced EMI 


p 


83CE59B(80CE598) 


32K 




512 


3 + Watchdog 


6 


UART, CAN 


6 


CAN Bus Controller, 8 x 10-bit A/D, 
2 PWM outputs, WD, T2, Reduced EMI 


p 


87CE598 




32K 


512 


3 + Watchdog 


6 


UART, CAN 


6 


(see above) 


p 


83CE558(80CE558) 


32K 




1024 


3 + Watchdog 


6 


UART, l 2 C 


2 


Low EMI, 8 Channel 10-bit A/D, 
2 PWM Outputs, Capture/Compare Timer 


p 


89CE558 




32K 


1024 


3 + Watchdog 


6 


UART, l 2 C 


2 


32K FLash EEPROM plus above 



All combinations of part type, speed, temperature and package may not be available. 



July 1996 



1-12 



80C51 microcontroller family features guide 



Part Number 
(ROMIess) 


Program 
Security? 


Clock Freq 
(MHz) 


Temperature Ranges ( c\ 


Package 


Oto 70 


-40 to +85 


-55 to +125 


PDIP 


CDIP 


PLCC 


CLCC 


PQFP/SSOP 


83C055 


S 


N 


3.5 to 20 


X 






NB42 










87C055 


S 


N 


3.5 to 20 


X 






NB42 










80C54 


S 


Y 


3.5 to 24 


X 


X 




N40 




A44 




B44 


87C54 


S 


Y 


3.5 to 24 


X 


X 




N40 


F40 


A44 


K44 


B44 


83C654 (80C654) 


H 


Y 


1 .2 to 24 


X 


X 


-40 to +125 


R42, 
N40 




A44 




B44 


87C654 


S 


Y 


1.2 to 20 


X 


X 


X 


N40 


F40 


A44 


K44 


B44 


83CE654 


H 


Y 


1.2 to 16 


X 


X 












B44 


83CL781 


Z 


N 


Oto 12 (1) 




X 




N40 








B44 


83CL782 


Z 


N 


Oto 12 (1) 




-25 to +55 




N40 








B44 


83C51FB 


s 


Y 


3.5 to 24 


X 


X 




N40 




A44 




B44 


87C51FB 


s 


Y 


3.5 to 24 


X 


X 




N40 


F40 


A44 


K44 


84 4 


83L51FB 


s 


Y 


3.5 to 20 


X 






N40 




A44 




B44 


87L51FB 


s 


Y 


3.5 to 20 


X 






N40 


F40 


A44 


K44 


B44 


83C524 


H 


Y 


1.2 to 16 


X 


X 




N40 




A44 




B44 


87C524 


s 


Y 


3.5 to 20 


X 


X 




N40 


F40 


A44 


K44 


B44 


83C592 (80C592) 


H 


Y 


1.2 to 16 




X 


-40 to +125 






A68 


K68 




87C592 




^ 


1 .2 to 1 6 


X 






R42 




A68 


K68 




80C58 






X 


X 




N40 




A44 




B44 


87C58 






3.5 to 16 








N40 


F40 






B44 


83C51FC 


S 


Y 


3.5 to 24 


X 


X 




N40 




A44 




B44 


87C51 FC 


s 


Y 


3.5 to 24 


X 


X 




N40 


F40 


A44 


K44 


B44 


83C528 (80C528) 


H 


Y 


1.2 to 16 


X 


X 


-40 to +125 


N40 




A44 




B44 


87C528 


S 


Y 


3.5 to 20 


X 


X 




N40 


F40 


A44 


K44 


B44 


83CE528 (80CE528) 


H 


Y 


1.2 to 16 


X 


X 


-40 to +125 






A44 




B44 


83CE598 (80CE598) 


H 


Y 


1.2 to 16 




X 


-40 to +125 










B80 


87CE598 


H 


Y 


3.5 to 16 


X 


X 












B80 


83CE558 80CE558 


H 




1.210 16 


X 


X 


-40 to +125 










B80 


89CE558 


H 


Y 


1.2 to 16 


X 


X 










Q80 


B80 



Notes: Production Centers are indicated in the second column: H - Hamburg, S - Sunnyvale, Z - Zurich. 
All combinations of part type, speed, temperature and package may not be available. 

1) Oscillator options start from 32kHz. 

2) Also available in VSO40 package. 

3) Also available in VS056 Package. 

4) Not recommended for new design. 

5) Package available up to 16 MHz only. 



July 1996 



Philips Semiconductors 



8051 microcontroller cross-reference guide 





INTEL 


SIEMENS 


OKI 


MATR A/HARRIS 


PHILIPS SEMICONDUCTORS 




ouvj I on 

80C31BH-1 
80C31BH-2 


car «nr^i 


MSM80C31 


80C31 
80C31-1 
80C3151 


PCRR0C31 RH-P/^CftOC^I ROC 
PCB80C31 BH-3/SC80C31 BCG 
/SC80C31 BCB 




80C51BH 
80O51BH-1 
80C51BH-2 


SAB 80C51 


MSM80C51 
MSM80C51 


80C51 
80C51-1 
80C51 


PCB80C51 BH-2/SC80C51 BCC 
rOBBOOol Bn-o/bO80u5l BOO 
/SC80C51 BCB 




87C51 
87C51-1 
87C51-2 








SC87C51CC 
SC87C51CG 
SC87C51CB 




80C32 
80C32-1 

80C52 
80C52-1 


SAB80C32 
SAB80C52 




80C32-25 
80C52-25 


P80C32EB 
P80C32GB 
P80C52EB 
P80C52GB 




80C54 
83C54 
87C54 
80C58 
83C58 
87C58 








80C54 
83C54 
87C54 
80C58 
83C58 
87C58 


CMOS 


83C51FA 
87C51FA 
83C51FB 
87C51FB 
83C51FC 
87C51FC 








S83C51FA 
S87C51FA 
S83C51FB 
S87C51FB 
S83C51 FC 
S87C51FC 



NOTES: 

1. 80XXAHL = 



80XX with low power standby pin; H = HMOS. 



March 1995 1-14 



Philips Semiconductors 



Low power / low voltage microcontroller family 



80C51 LOW POWER FAMILY 



Type 


Available 


ROM 


RAM 


I/O 


|2C 


UART 


Features 


Package 




Yes 


4k 


128 


32 


No 


Yes 


Low Voltage 80C51 


40-Pin Dual In-Line 
40-Pin Very Small Outline 
44-Pin Quad Flat Pack 


80CL31 


Yes 


- 


128 


32 


No 


Yes 


Low Voltage 80C31 


40-Pin Dual In-Line 
40-Pin Very Small Outline 
44-Pin Quad Flat Pack 


83CL410 


Yes 


4k 


128 


32 


Yes 


No 


80CL51 with l 2 C-bus 


40-Pin Dual In-Line 
40-Pin Very Small Outline 
44-Pin Quad Flat Pack 


80CL410 


Yes 




128 


32 


Yes 


No 


80CL51 with l 2 C-bus 


40-Pin Dual In-Line 
40-Pin Very Small Outline 
44-Pin Quad Flat Pack 


83CL580 


Yes 


6k 


256 


40 


Yes 


Yes 


ADC, PWM, Watchdog, T2 


50-Pin Very Small Outline 
64-Pin Quad Flat Pack 


80CL580 


Yes 




256 


40 


Yes 


Yes 


ADC, PWM, Watchdog, T2 


50-Pin Very Small Outline 
64-Pin Quad Flat Pack 


83CL781 


Yes 


16k 


256 


32 


Yes 


Yes 


Low voltage 83C654, T2 




40-Pin Dual In-Line 
44-Pin Quad Flat Pack 


83CL782 


Yes 


16k 


256 


32 


Yes 


Yes 


Fast83CL781: 12MHZ/3V 


40-Pin Dual In-Line 
44-Pin Quad Rat Pack 


85CL000 


Yes 




256 


32 


Yes 


Yes 


For SW development 


Piggyback 


85CL580 


Yes 




256 


40 


Yes 


Yes 


For SW development 


Piggyback 


85CL782 


Yes 




256 


32 


Yes 


Yes 


For SW development 


P 


ggyback 


LOW VOLTAGE DEVICES 




Type 


Available 


ROM 


RAM 


I/O 




UART 


Features 


Package 


83L51FA 


Yes 


8k 


256 


32 


No 


Yes 


PCA, Enhanced UART 
3.0V to 4.5V 


40-Pin Dual In-Line 

44-Pin PLCC 

44-Pin Quad Flat Pack 


87L51FA 


Yes 


8k 
EPROM/ 
OTP 


256 


32 


No 


Yes 


PCA, Enhanced UART 
3.0V to 4.5V 


40-Pin Dual In-Line 

44-Pin PLCC 

44-Pin Quad Flat Pack 


83L51FB 


Yes 


16k 


256 


32 


No 


Yes 


PCA, Enhanced UART 
3.0V to 4.5V 


40-Pin Dual In-Line 

44-Pin PLCC 

44-Pin Quad Flat Pack 


83L51FB 


Yes 


16k 
EPROM/ 
OTP 


256 


32 


No 


Yes 


PCA, Enhanced UART 
3.0V to 4.5V 


40-Pin Dual In-Line 

44-Pin PLCC 

44-Pin Quad Flat Pack 



March 1995 



Philips Semiconductors 



CMOS and NMOS 8-bit microcontroller family 



8400 FAMILY CMOS 



TYPE 


ROM 


RAM 


SPEED 
(MHz) 


PACKAGE 


FUNCTIONS 


REMARKS 


PROBE 
SDS 


REMARKS 


84C21A 
84C41A 


2k 
4k 
8k 


64 
128 
256 


10 
10 
10 


DIL28/S028 
DIL28/S028 
DIL28/S028 


20 I/O lines 
8-bit timer 
Byte l 2 C 




OM1083 


OM1025 
(LSDS) 


84C22A 
84C42A 


2k 
4k 
1k 


64 
64 
64 


10 
10 
16 


DIL20/SO20 
DIL20/SO20 
DIL20/SO20 
DIL20/SO20 


13 I/O lines 
8-bit timer 




OM1083 + 
AdapteM 


OM1025 
(LSDS) 


84C12A 




84C00B 






256 
256 


10 
10 


28 pins 


20 I/O lines 
8-bit timer 
Byte l 2 C 


Piggyback 
ROMIess 


OM1080 
OM1080 




84C00T 


VSO-56 


84C121 
84C121B 


1k 


64 
64 


10 
10 


DIL20/SO20 


13 I/O lines 
2 8-bit timers 
8 bytes 
EEPROM 




OM1073 


OM1025(LEDS) 
OM1027 







Piggyback 


84C122A 
84C122B 
84C422A 
84C422B 

f5*+\jO£.£.t\ 

84C822B 
84C822C 


1k 
4K 


32 
32 


10 


A: SO20 
B: S024 
C: S028 


Controller for 
remote control 
A: 12 I/O 
B: 16 I/O 
C: 20 I/O 




OM4830 




8K 


32 




























84C230 


a 


64 


10 


DIL40/VSO40 


12 I/O lines 




OM1072 










8-bit timer 
16*4 LCD drive 


















84C430 


4k 


128 


10 


QFP64 


24 I/O lines 

ft-hit timpr 

u Ull LI I ■ PCI 

Byte l 2 C 

24*4 LCD drivp 




OM1 072 






o 


128 






piggyback for C230 
and 04^0 

ul IU vtJU 






10 








256 
256 


16 
16 


VS056 




28 I/O lines 
8-bit timer 
16-bit up/down 
counter 
1 6-bit timer 
with compare 
and capture 
16*4 LCD drive 




OM1086 




84C633 
84C633B 


6k 







84C440 


4k 


128 


10 


DIP42 shrunk 


RC: 29 I/O lines 


l 2 C, RC 


OM1074 


For emulation of 


84C441 


4k 


128 


10 




LC: 28 I/O lines 


l 2 C, LC 




LC versions, 


84C443 


4k 


128 


10 




8-bit timer 


RC 




useOM1074 + 


84C444 


4k 


128 


10 




1 14-bit PWM 


LC 




adapter_3 + 


84C640 


6k 


128 


10 




5 6-bit PWM 


l 2 C, RC 




2 adapter_5 


84C641 


6k 


128 


10 




3-bit ADC 


l 2 C, LC 






84C643 


6k 


128 


10 




OSD 2L-16 


RC 






84C644 


6k 


128 


10 






LC 






84C840 


8k 


192 


10 






l 2 C, RC 






84C841 


8k 


192 


10 






l 2 C, LC 






84C843 


8k 


192 


10 






RC 




Baud for LCDS 


84C844 


8k 


192 


10 






LC 




OM4831 



July 1996 



Philips Semiconductors 



CMOS and NMOS 8-bit microcontroller family 



8400 FAMILY CMOS (Continued) 



TYPE 


ROM 


RAM 


SPEED 


PACKAGE 


FUNCTIONS 


REMARKS 


PROBE 


REMARKS 








(MHz) 








SDS 




84C646 


6k 


192 


10 


DIP42 shrunk 


30 I/O lines 


l 2 C, RC 


OM4829 + 


OM4833 for 


84C846 


8k 


192 


10 




DOS clock = 


l 2 C, RC 


OM4832 


LCD584 












PLL 


















8 bit timer 


















1-14 bit PWM 


















4-6 bit PWM 


















4-7 bit PWM 


















3-4 bit ADC 


















DOS: 64 disp. 


















RAM 


















62 char, fonts 


















Char, blinking 


















Shadow modes 


















8 foreground 


















colors/char. 


















8 background 


















colors/word 


















DOS: clock: 


















8 . . 20MHz 










84C85 


8k 


256 


10 


DIL40/VSO40 


32 I/O lines 




OM1070 














8-bit timer 


















Byte l 2 C 








84C85B 





256 


10 






Piggyback for C85 








Qr> 
OK 


256 


1 ft 
I 


nil /inA/QO/if\ 


oj \f\j lines 




OM1 nR1 

\JlVt I UO I 














8-bit timer 


















1 6-bit up/down 


















counter 


















16-bit timer with 


















compare and 


















LajJlUi b 








84C853B 





256 


16 






Piggyback for C853 






84C270 


2k 


128 


10 


DIL40/VSO40 


8 I/O lines 




OM1077 




84C470 


4k 


128 


10 


DIL40/VSO40 


1 6*8 capture 


















keyboard matrix 


















8-bit timer 








84C270B 





128 


10 






Piggyback for C270 






84C470B 





128 


10 




470 also 


Piggyback for C470 
















handles mech. 
















keys 










2k 






DIL40 










84C271 


128 


10 


8 I/O lines 
16'8 mech. 




OM1078 














keyboard matrix 


















8-bit timer 









8400 FAMILY NMOS 



■SoTT 



RAM 



SPEED 
(MHz) 



PACKAGE 



FUNCTIONS 



REMARKS 



EMULATOR 
TOOLS 



REMARKS 



8411 
8421 
8441 
8461 



1k 
2k 
4k 
6k 



64 
64 
128 
128 



DIL28/S028 
DIL28/S028 
DIL28/S028 
DIL28/S028 



20 I/O lines 
8-bit timer 
Byte l 2 C 



OM1025 
(LCDS) + 
OM1026 



8422 
8442 



2k 
4k 



64 
128 



DIL20 
DIL20 



13 I/O lines 
8-bit timer 
Bit l 2 C 



^OIB 



128 



6 28-pin 



Piggyback for 84X1 



July 1996 



1-17 



Philips Semiconductors 



CMOS and NMOS 8-bit microcontroller family 



3300 FAMILY CMOS 



TYPE 


ROM 


RAM 


SPEED 
(MHz) 


PACKAGE 


FUNCTIONS 


REMARKS 


PROBE 
SDS 


REMARKS 


331 5A 


1.5k 


160 


10 


DIL28/S028 


20 I/O lines 
8-bit timer 
V DD >1.8V 






OM1083 


OM1025(LCDS) 


3343 


3k 


224 


10 


DIL28/S028 


20 I/O lines 
8-bit timer 
V DD >1.8V 
Byte l 2 C 






OM1083 


OM1025(LCDS) 


3344A 


2k 


224 


3.58 


DIL28/S028 


20 I/O lines 
8-bit timer 
DTMF generator 






OM1071 


OM1025(LCDS) 
+ OM1028 


3346A 


4k 


128 


10 


DIL28/S028 


20 I/O lines 
8-bit timer 
Byte l 2 C 

256 bytes EEPROM 
V DD <1.8V 






OM1076 




3347 


1.5k 


64 


3.58 


DIL20/SO20 


12 I/O lines 
8-bit timer 
DTMF generator 




OM1071 + 
Adapter_2 


OM1025(LCDS) 
+ OM1028 


3348A 


8k 


256 


10 


DIL28/S028 


20 I/O lines 
8-bit timer 
Byte l 2 C 
V DD <1.8V 




OM1083 


OM1025(LCDS) 


3349A 


4k 


224 


3.58 


DIL28/S028 


20 I/O lines 
8-bit timer 
DTMF generator 




OM1071 


OM1025(LCDS) 
+ OM1028 


3350A 


8k 


128 


3.58 


VS064 


30 I/O lines 
8-bit timer 
DTMF generator 
256 bytes EEPROM 








3351 A 


2k 


64 


3.58 


DIL28/S028 


20 I/O lines 
8-bit timer 
DTMF generator 
128 bytes EEPROM 




OM5000 




3352A 




6k 


128 


3.58 


DIL28/S028 


20 I/O lines 
8-bit timer 
DTMF generator 
128 byte EEPROM 




OM5000 




3353A 


6k 


128 


16 


DIL28/S028 


20 I/O lines 
8-bit timer 
DTMF generator 
Ringer out 
128 bytes EEPROM 


March '92 


OM5000 




3354A 


8k 


256 


16 


QFP64 


36 I/O lines 
8-bit timer 
DTMF generator 
Ringer out 
256 bytes EEPROM 


June '92 


OM4829 + 


OM4829: Probe 
base 


8755A 





128 


16 


DIL28/S028 


8k OTP 
20 I/O lines 
8-bit timer 
DTMF generator 
Melody output 
128 bytes EEPROM 


In Development 






3301 B 












Piggyback for 331 5, 
3343, 3348 


OM1083 




3344B 












Piggyback for 3344, 
3347, 3349 


OM1071 




3346B 














OM1076 





July 1996 



1-18 



Philips Semiconductors 








3300 FAMILY CMOS (Continued) 



TYPE 


ROM 


RAM 


SPEED 
(MHz) 


PACKAGE 


FUNCTIONS 


REMARKS 


PROBE 


REMARKS 


3350B 












Piggyback for 3350A 


OM4829+ 
OM5003 





3351 B 












Piggyback for 
3351 A, 3352A, 
3353A 


OM5000 




3354B 












Piggyback for 3354A 


OM4829+ 
OM5010 


























































• 











































July 1996 



1-19 



Philips Semiconductors 



CMOS 16-bit microcontroller family 



16-BIT CONTROLLERS (XA ARCHITECTURE) 



TYPE 


(EP)ROM 


RAM 


SPEED 
(MHz) 


FUNCTIONS 


REMARKS 


DEVELOPMENT TOOLS 


XA-G1 


8k 


512 


30 


3 timers, watchdog, 
2 UARTs 


^tOto 
+125°C 


Nohau 
Ceibo 

MacCraigor Systems 


XA-G2 


16k 


512 


30 


3 timers, watchdog, 
2 UARTs 


-40 to 
+125°C 


Nohau 
Ceibo 

MacCraigor Systems 


XA-G3 


32k 


512 


30 


3 timers, watchdog, 
2 UARTs 


^tOto 
+125°C 


Nohau 
Ceibo 

MacCraigor Systems 



16-BIT CONTROLLERS (68000 ARCHITECTURE) 



TYPE 


(EP)ROM 


RAM 


SPEED 
(MHz) 


FUNCTIONS 


REMARKS 


PHILIPS TOOLS 


THIRD-PARTY 
TOOLS 


68070 






17.5 


2 DMA channels, 
MMU, UART, 
16-bit timer, l 2 C, 
68000 bus interface, 
16Mb address range 




OM4160 Microcore 1 
OM4160/2 Microcore 2 
OM4161 (SBE68070) 
OM4767/2 XRAY68070SBE 

high level symbolic debugger 
OM4222 68070DS development 

system 
OM4226 XRAY68070DS 

high level symbolic debugger 


TRACE32-ICE68070 
(Lauterbach) 


93C101 


34k 


512 


15 


Derivative with low 
power modes 


Not for new 
design 






90CE201 


16MB 
external 
ROM 


16MB 
external 
RAM 


24 


UART, fast l 2 C, 
3 timers (16 bit), 
Watchdog timer. 
68000 software 
compatible, EMC, 
QFP64 


-25 to 
+85°C 


OM4162 Microcore 4 


TRACE32 - 
(Lauterbach) 



July 1996 



1-20 



Philips Semiconductors 



Ordering Information 



MICROCONTROLLER PRODUCTS 







Example: 



P 8 X C X X X 



= ROMLESS 

5 = Bond-Out (emulation) 

3 = ROM 

7 = EPROM/OTP 

9 = FEEPROM (FLASH) 

Exceptions: 

P80C32 = ROMIess 
P80C52 = ROM 



This can be 2 or 3 digits- 



Speed 



C = 12MHz 
E = 3.5MHz to 16MHz 
F= 1.2MHz to 16MHz 
G = 20MHz 
H = 32kHz to 12MHz 
I = 24MHz 
P = 40MHz 



E B P N 



Philips North America Package Code 
A = Plastic Leaded Chip Carrier (PLCC) 
B = Quad Flat Pack (QFP) 
FA = Hermetic Cerdip (window) 
KA = CerQuad (window) 
N = Plastic Dual In-Line 

Philips Package Code 

A = Plastic Leaded Chip Carrier (PLCC) 

B = Quad Rat Pack (QFP) 

F = Hermetic Cerdip (window) 

L = Cerquad (window) 

P = Plastic Dual In-Line 

Q = Ceramic Quad Flat Pack (window) 

Temperature 

B = 0°C to +70°C 
F = -40°C to +85°C 
H = -40°Cto+125°C 



SC8XCXXXBCCN 40 



= ROMLESS 1 

3 = ROM 

7 = EPROM/OTP 

Exceptions: 

SC80C31 = ROMIess 
SC80C51 = ROM 



This can be 2 or 3 digits- 



I 



Pin Count 



Package Code 

A = Plastic Leaded Chip Carrier (PLCC) 

B = Quad Flat Pack (QFP) 

F = Ceramic Dual In-Line 

FA = Hermetic Cerdip (window) 

KA= CerQuad (window) 

L = Chip Carrier, Leaded 

N = Plastic Dual In-Line 

Speed 

B = 0.5to12MHz 
C = 12MHz 
G = 16MHz 
L = 20MHz 
P = 24MHz 
Y = 33MHz 

Temperature 

C = Commercial 0°C to +70°C 
A = Industrial -40°C to +85°C 

Revision (optional) 



July 1996 



1-21 



Philips Semiconductors 




Ordering Information 



— 







Example: S 8 X C XXX -1 N 24 



= ROMLESS — 

3= ROM 

7 = EPROM/OTP 



1 



Pin Count 



Package Code 

A = Plastic Leaded Chip Carrier (PLCC) 

B = Quad Flat Pack (QFP) 

F = Ceramic Dual In-Line 

K = CerQuad 

N = Plastic Dual In-Line 

Speed / Temperature Range 
-1 = 12MHz, 0°Cto+70°C 
-2 = 12MHz, -40°C to +BS°C 
-3 = 0.5 to 12MHz, 0°C to +7CTC 
-4 = 16MHz, 0°Cto+70°C 
-5 = 16MHz, -40°C to +85°C 
-6 = 1 2 or 1 6MHz, -55°C to +1 25°C 
-7 = 20MHz, 0°C to +70°C 
-8 = 20MHz, -40°C to +85°C 
-A = 24MHz, 0°C to +70°C 
-B = 24MHz, -40°C to +85°C 



XA PRODUCTS 



Example: 



P51XA G3 7 K B A 



Philips 80C51 extended Architecture 
Derivative Name 



J 



L 



Package Code 

A = Plastic Leaded Chip Carrier (PLCC) 

B = Quad Flat Pack (QFP) 

BD = Thin Quad Flat Pack (TQFP) 

FA = Hermetic Cerdip (window) 

KA = CerQuad (window) 

N = Plastic Dual In-Line 



Temperature 

B = 0°C to +70°C 
F = -40°C to +85°C 
H = -40°Cto+125°C 

Speed 

E = 16MHz 
G = 20MHz 
I = 24MHz 
K = 30MHz 

Memory Opation 
= ROMIess 
3 = ROM 

5 = Bond-Out (emulation) 

7 = EPROM/OTP 

9 = FEEPROM (FLASH) 



July 1996 



Philips Semiconductors 

FAX-on-DEMAND System 




FAXj 

DEMAND 



You can hang up now 



What is it? 

The FAX-on-DEMAND system is a computer facsimile 
system that allows customers to receive selected 
documents by fax automatically. 

How does it work? 

To order a document, you simply enter the document 
number. This number can be obtained by asking for an 
index of available documents to be faxed to you the 
first time you call the system. 

Our system has a selection of the latest product data 
sheets from Philips with varying page counts. As you 
know, it takes approximately one minute to FAX one 
page. This isn't bad if the number of pages is less than 
10. But if the document is 37 pages long, be ready for 
a long transmission! 

Philips Semiconductors also maintains product 
information on the World-Wide Web. Our home page 
can be located at: 

http://www.semiconductors.philips.com 

Who do I contact if I have a question 
about FAX-on-DEMAND? 

Contact your local Philips sales office. 



FAX-on-DEMAND phone numbers: 

England 44-181-730-5020 
(United Kingdom, Ireland) 

France 33-1 -40-99-60-60 

Germany 49-40-23536-357 
(Austria, Switzerland) 



Italy 

North America 



39-167-295502 
1-800-282-200 



Locations soon to be in operation: 

Hong Kong 
Japan 

The Netherlands 



1996 Jul 31 



Philips Semiconductors 



Microcontroller internet and 
bulletin board access 



INTERNET ACCESS 

Philips Semiconductors World Wide Web: 

http://www.semiconductors.philips.com 



Internet 80C51 Applications Support Address: 

80C51 _help @ scs.philips.com 

Send us your questions and we will respond quickly. 

Microcontroller FTP Site: 

ftp://ftp.PhilipsMCU.com 



Internet Microcontroller Newsletter: 

To subscribe, send email to: 

News-Request® PhilipsMCU.com 



Internet 80C51 Discussion Forum: 

9 P 



Internet XA 16-bit 80C51 Support Address: 

XA_help@scs.philips.com 



1996 Aug 16 1-24 



Philips Se 





Microcontroller internet 
bulletin board access 



BULLETIN BOARDS 

To better serve our customers, Philips maintains two microcontroller bulletin boards. These computer bulletin board 
systems feature microcontroller newsletters, application and demonstration programs for download, and the ability 
to send messages to microcontroller application engineers. 

The telephone numbers are: 

North American Bulletin Board 
MAX 14.400 baud 8-N-1 



(800) 451-6644 (in the U.S.) 
or 

(408) 991-2406 



European Bulletin Board 
MAX 14.400 baud 
Standards V32/V42/V42.bis/HST 
+31 40 2721102 



Sunnyvale ROMcode Bulletin Board 



We also have a ROM code bulletin board through which you can submit ROM codes. This is a closed bulletin 
board for security reasons. To get an ID, contact your local sales office. The system can be accessed with a 2400, 
1200, or 300 baud modem, and is available 24 hours a day. 

The telephone number is: 

(408) 991-3459 



All code for application notes in this databook are available on the Philips BBS, as well as on the world-wide web. 



1996 Aug 16 



Philips Semiconductors 

80C51 microcontroller development 



— 



DEVELOPMENT SYSTEM CONTACTS 



COMPANY 


ADDRESS 


TELEPHONE 


Ashling Microsystems Limited 


Plassey Technological Park 
Limerick, Ireland 

Eastern Systems Inc. 
1 60 East Main Street 
Westboro, MA 01581 


(353) 61 334 466 
(508) 366-3220 


BSO Tasking 


Norfolk Place 
333 Elm Stmfit 
Dedham, MA 02026-4530 


(800) 458-8276 


Ceibo 


7 Edgestone Ct. 
Florissant, MO 63033 

Merkazim Building, Industrial Zone 
P.O. Box 2106 
Herzelia 46120, ISRAEL 




(314)830-4084 
972-59-555387 


Lauterbach Datentechnik GmbH 


Fichtenstrasse 27 

SET" 

yno ooncoro oireei 
Framingham, MA 01701 




49 8104 894 328 
(508) 620-4521 


MetaLink Corp. 


325 E. Elliot Road, Suite 23 
Chandler, AZ 85225 


(602) 926-0797 


Nohau Corp. 


51 E. Campbell Ave. 
Campbell, CA 95008-2053 


(408) 866-1820 


Philips Semiconductors 


Corporate Centre 
Building BAE-2 
P.O. Box 21 8 
5600 MD Eindhoven 
The Netherlands 


31-40-724223 


SIGNUM Systems 


171 E. Thousand Oaks Blvd., 
#202 

Thousand Oaks, CA 91360 


(805)371-4608 


EPROM PROGRAMMING SUPPORT CONTACTS 


Advin Systems 
1 050-L East Duane Ave. 
Sunnyvale, CA 94086 
(408) 243-7000 
(800) 627-2456 


Logical Devices, Inc. 
1201 Northwest 65th Place 
Ft. Lauderdale, FL 33309 
(305) 974-0967 


North Valley Products 
P.O. Box 32899 
San Jose, CA 95152 
(408) 929-5345 


BP Microsystems 

10681 Haddington #190 

Houston, TX 77043 

(800) 225-2102, (713) 461-9430 


Logical Systems 
P.O. Box 6184 
Syracuse, NY 13217-6184 
(315)478-0722 


Strebor Data Communications 
1008 N. Nob Hill 
American Fork, UT 84003 
(801)756-3605 


Data I/O Corp. 
10525 Willows Road N.E. 
P.O. Box 97046 
Redmond, WA 98073-9746 
(206) 881-6444 


Needham's Electronics 
4535 Orange Grove Ave. 
Sacramento, CA 95841 
(916)924-8037 




1996 Aug 12 1-26 



Philips Semiconductors 



80C51 microcontroller development system support 







SOFTWARE SUPPORT CONTACTS 



COMPANY 


ADDRESS 


TELEPHONE 


Archimedes Software, Inc. 


2159 Union St. 

San Francisco, CA 941 23 


(415) 567-^010 


BSO/Tasking 


Tasking Software BV 
P.O. Box 899 
3800 AW Amersfoort 
The Netherlands 

BSO Tasking 

1 28 Technology Center 

P.O. Box 9164 

Waltham, MA 02254-9164 


31-33-55-85-84 (Telephone) 
31-33-55-00-33 (Fax) 

(617) 894-7800 (Telephone) 
(617) 894-0551 (Fax) 
(710) 324-0760 (Telex) 
(800) 458-8276 (Toll Free) 


Franklin Software, Inc. 


888 Saratoga Ave. #2 
San Jose, CA 95129 


(408) 296-8051 


Keil Software 


Bretonischer Ring 15 
85630 Grasbrunn 
Germany 


49-89-46-50-57 (Telephone) 
49-89-46-81-62 (Fax) 


NOTE: 

For more information on Development Support, see Section 9, Vol. 2, IC20. 



1996 Aug 12 



Philips Semiconductors 



8-bit microcontroller demonstration and 
evaluation boards 



PRODUCT 


DESCRIPTION 


OM4151, S87C00K 

OM4238, P8051DB 
OM4128 

OM4130, PCAN-EVAL 

OM4239 

OM4240 

OM4241 

OM4160, SM68070 

OM4160/2 

OM4162 

OM4280, P83C852DEM 

OM4281 1 

P8051DB 

OM4717 

OM5005, P80CLEVAL 
DS750 


l 2 C demonstration board based on 80C51 derivatives 

8051 family demonstration board 
8XC552 evaluation board PEB552 
CAN controller evaluation board 
8XC592 evaluation board PEB592 
8XCE598 evaluation board PEB598 
8XCE598 evaluation board PDB598 

68070 and 66470 demonstration and evaluation board Microcore 1 
68070 evaluation board Microcore 2 

83C852 demonstration kit 

83C852 software evaluation kit 

80C51 family development board 

83CL41 solar powered demonstration board 

80CL51 evaluation board 

8XC750 microcontroller in-circuit emulation development tool 



NOTE: 

1. The OM4281 is now available only from Ashling Microsystems Ltd. as type SCPC4281. 



March 1995 



1-28 



Philips Semiconductors 



Section 2 

80C51 Technical Description 



80C51 -Based 

8-Bit Microcontrollers 



CONTENTS 

80C51 family architecture 

80C51 family hardware description 

80C51 family programmer's guide and instruction set . . 
80C51 family EPROM products 



2-1 



2-2 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



80C51 ARCHITECTURE 



MEMORY ORGANIZATION 

All 80C51 devices have separate address spaces for program and 



data memory, as shown in Figures 1 and 2. The logical separation of 
program and data memory allows the data memory to be accessed 
by 8-bit addresses, which can be quickly stored and manipulated by 
an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also 
be generated through the DPTR register. 

Program memory (ROM, EPROM) can only be read, not written to. 
There can be up to 64k bytes of program memory. In the 80C51 , the 
lowest 4k bytes of program are on-chip. In the ROMIess versions, all 
program memory is external. The read strobe for external program 
memory is the PSEN (program store enable). 

Data Memory (RAM) occupies a separate address space from 
Program Memory. In the 80C51 , the lowest 1 28 bytes of data 
memory are on-chip. Up to 64k bytes of external RAM can be 
addressed in the external Data Memory space. In the ROMIess 
version, the lowest 128 bytes are on-chip. The CPU generates read 
and write signals, RD and WR, as needed during external Data 
Memory accesses. 

External Program Memory and external Data Memory may be 
combined if desired by applying the RD and PSEN signals to the 
inputs of an AND gate and using the output of the gate as the read 
strobe to the external Program/Data memory. 

Program Memory 

Figure 3 shows a map of the lower part of the Program Memory. 
After reset, the CPU begins execution from location 0000H. As 
shown in Figure 3, each interrupt is assigned a fixed location in 
Program Memory. The interrupt causes the CPU to jump to that 
location, where it commences execution of the service routine. 
External Interrupt 0, for example, is assigned to location 0003H. If 
External Interrupt is going to be used, its service routine must 
begin at location 0003H. If the interrupt is not going to be used, its 
service location is available as general purpose Program Memory. 



The interrupt service locations are spaced at 8-byte intervals: 0003H 
for External Interrupt 0, 000BH for Timer 0, 001 3H for External 
Interrupt 1 , 001 BH for Timer 1 , etc. If an interrupt service routine is 
short enough (as is often the case in control applications), it can 
reside entirely within that 8-byte interval. Longer service routines 
can use a jump instruction to skip over subsequent interrupt 
locations, if other interrupts are in use. 

The lowest 4k bytes of Program Memory can either be in the on-chip 
ROM or in an external ROM. This selection is made by strapping the 
EE (External Access) pin to either V C c, or V ss . In the 80C51 , if the 
EE pin is strapped to Vcc, then the program fetches to addresses 
0000H through 0FFFH are directed to the internal ROM. Program 
fetches to addresses 1000H through FFFFH are directed to external 
ROM. 

If the EE pin is strapped to Vss, then all program fetches are 
directed to external ROM. The ROMIess parts (8031 , 80C31 , etc.) 
must have this pin externally strapped to V s s to enable them to 
execute from external Program Memory. 

The read strobe to external ROM, PSEN, is used for all external 
program fetches. PSEN is not activated for internal program fetches 

The hardware configuration for external program execution is shown 
in Figure 4. Note that 16 I/O lines (Ports and 2) are dedicated to 
bus functions during external Program Memory fetches. Port (P0 
in Figure 4) serves as a multiplexed address/data bus. It emits the 
low byte of the Program Counter (PCL) as an address, and then 
goes into a float state awaiting the arrival of the code byte from the 
Program Memory. During the time that the low byte of the Program 
Counter is valid on Port 0, the signal ALE (Address Latch Enable) 
clocks this byte into an address latch. Meanwhile, Port 2 (P2 in 
Figure 4) emits the high byte of the Program Counter (PCH). Then 
PSEN strobes the EPROM and the code byte is read into the 
microcontroller. 



Program Memory addresses are always 1 6 bits wide, even though 
the actual amount of Program Memory used may be less than 64k 
bytes. External program execution sacrifices two of the 8-bit ports, 
P0 and P2, to the function of addressing the Program Memory. 



Interrupt 
Control 



128 
RAM 



A 



fE J! 



Timer 1 






Timer 





Counter 
Inputs 



Bus 
Control 



/\ s\ /\ s\ 



\y <y \7 \> 

P0 P2 P1 P3 



Serial 
Port 



TXD RXD 





Figure 1. 80C51 Block Diagram 







March 1995 



Philips Semiconductors 



80C51 Family 



Program Memory 
(Read Only) 

■ 



Data Memory 
(Read/Write) 



ES = 
External 



, , r- w - 

^....1. .......... 



EA=1 
Internal 



■ 

: 

■ 
■ 



........i 



W 7 - 



Figure 2. 80C51 Memory Structure 



Interrupt < 
Locations * 



001 BH 
0013H 
000BH 
0003H 



I 



8 Bytes 



Figure 3. 80C51 Program Memory 




Figure 4. Executing from External Program Memory 



Data Memory 

The right half of Figure 2 shows the internal and external Data 
Memory spaces available to the 80C51 user. Figure 5 shows a 
hardware configuration for accessing up to 2k bytes of external 
RAM. The CPU in this case is executing from internal ROM. Port 
serves as a multiplexed address/data bus to the RAM, and 3 lines of 
Port 2 are being used to page the RAM. The CPU generates RD 
and WR signals as needed during external RAM accesses. There 
can be up to 64k bytes of external Data Memory. External Data 



Memory addresses can be either 1 or 2 bytes wide. One-byte 
addresses are often used in conjunction with one or more other I/O 
lines to page the RAM, as shown in Figure 5. 

Two-byte addresses can also be used, in which case the high 
address byte is emitted at Port 2. 

Internal Data Memory is mapped in Figure 6. The memory space is 
shown divided into three blocks, which are generally referred to as 
the Lower 128, the Upper 128, and SFR space. 



March 1995 



2-4 



Philips Semiconductors 

80C51 Family 80C51 family architecture 



Internal Data Memory addresses are always one byte wide, which 
implies an address space of only 256 bytes. However, the 
addressing modes for internal RAM can in fact accommodate 384 
s, using a simple trick. Direct addresses higher than 7FH 
s one memory space, and indirect addresses higher than 7FH 
3 a different memory space. Thus Figure 6 shows the Upper 
128 and SFR space occupying the same block of addresses, 80H 
through FFH, although they are physically separate entities. 

The Lower 128 bytes of RAM are present in all 80C51 devices as 
pped in Figure 7. The lowest 32 bytes are grouped into 4 banks 
f 8 registers. Program instructions call out these registers as RO 
gh R7. Two bits in the Program Status Word (PSW) select 
i register bank is in use. This allows more efficient use of code 
e, since register instructions are shorter than instructions that 
use direct addressing. 



The next 1 6 bytes above the register banks form a block of 
bit-addressable memory space. The 80C51 instruction set includes 
a wide selection of single-bit instructions, and the 128 bits in this 
area can be directly addressed by these instructions. The bit 
addresses in this area are 00H through 7FH. 

All of the bytes in the Lower 128 can be accessed by either direct or 
indirect addressing. The Upper 1 28 (Figure 8) can only be accessed 
by indirect addressing. 

Figure 9 gives a brief look at the Special Function Register (SFR) 
space. SFRs include the Port latches, timers, peripheral controls, 
etc. These registers can only be accessed by direct addressing. 
Sixteen addresses in SFR space are both byte- and bit-addressable. 
The bit-addressable SFRs are those whose address ends in OH or 8H. 



c 





PO 




ES 




80C51 






with 






Internal 






ROM 








ALE 




\ P3 


PZ < 




RD 






wn J 







/LA 



Page 
Bits 



WE DE 

T 



Figure 5. Accessing External Data Memory 
If the Program Memory Is Internal, 
the Other Bits of P2 Are Available as I/O 



Bank 
Select 
Bits in 
PSW 



7FH 




2FH 


20H 




18H 


1FH 


10H 


17H 


08H 


OFH 





07H 



Bit-Addressable Space 
(Bit Addresses 0-7F) 



■ 



Reset Value of 
Stack Pointer 



Upper 
128 



Lower 
128 



Accessible 
by Indirect 
Addressing 
Only 



Accessible 
by Direct 
and Indirect 
Addressing 



by Direct 



Special 
Function 
Registers 



Ports. 
Status and 
Control Bits, 
Timer, 
Registers, 
Slack Pointer, 
Accumulator 
(Etc.) 



Figure 6. Internal Data Memory 



FFH 



Figure 7. Lower 128 Bytes of Internal RAM 



gure 8. 



of Internal RAM 



March 1995 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 







FFH 
EOH 



AOH 



90H 



80H Port 



Register-Mapped Ports 



is 



thai end in OH or 8H 



Port Pins 

Accumulator 

PSW 



Figure 



J 

- 

SFR Space 



PSW 

Carry flag receives carry out 
from bit 7 of ALU 



Auxiliary carry (lag receives carry out from bit 3 
of addition operands. 



FO RS1 RSO OV 



General pu 



PSW 4 - 
bank select bit 1 



r 



PSWO 

Parity of accumulator si 
by hardware to 1 if it contains 
an odd number of 1s;o' 
it is reset to 0. 



User-definable flag 

PSW 2 

Overflow flag set by 
arithmetic operations 

PSW 3 

Register bank select bit 



SU00467 



Figure 10. 

80C51 FAMILY INSTRUCTION SET 

The 80C51 instruction set is optimized for 8-bit control applications. 
It provides a variety of fast addressing modes for accessing the 
internal RAM to facilitate byte operations on small data structures. 
The instruction set provides extensive support for one-bit variables 
as a separate data type, allowing direct bit manipulation in control 
and logic systems that require Boolean processing. 

Program Status Word 

The Program Status Word (PSW) contains several status bits that 
reflect the current state of the CPU. The PSW, shown in Figure 10, 
resides in the SFR space. It contains the Carry bit, the Auxiliary 
Carry (for BCD operations), the two register bank select bits, the 
Overflow flag, a Parity bit, and two user-definable status flags. 

The Carry bit, other than serving the function of a Carry bit in 
arithmetic operations, also serves as the "Accumulator" for a 
number of Boolean operations. 

The bits RSO and RS1 are used to select one of the four register 
banks shown in Figure 7. A number of instructions refer to these 



Word) 



RAM locations as R0 through R7. The selection of which of the four 
is being referred to is made on the basis of the RSO and RS1 at 
execution time. 

The Parity bit reflects the number of 1s in the Accumulator: P = 1 if 
the Accumulator contains an odd number of 1 s, and P = if the 
Accumulator contains an even number of 1 s. Thus the number of 1 s 
in the Accumulator plus P is always even. Two bits in the PSW are 
uncommitted and may be used as general purpose status flags. 

Addressing Modes 

The addressing modes in the 80C51 instruction set are as follows: 
Direct Addressing 

In direct addressing the operand is specified by an 8-bit address 
field in the instruction. Only internal Data RAM and SFRs can be 
directly addressed. 



March 1995 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



Indirect Addressing 

In indirect addressing the instruction specifies a register which 
contains the address of the operand. Both internal and external 
RAM can be indirectly addressed. 

The address register for 8-bit addresses can be RO or R1 of the 
selected bank, or the Stack Pointer. The address register for 1 6-bit 
addresses can only be the 16-bit "data pointer" register, DPTR. 

Register Instructions 

The register banks, containing registers RO through R7, can be 
accessed by certain instructions which carry a 3-bit register 
specification within the opcode of the instruction. Instructions that 
access the registers this way are code efficient, since this mode 
eliminates an address byte. When the instruction is executed, one of 
the eight registers in the selected bank is accessed. One of four 
banks is selected at execution time by the two bank select bits in the 
PSW. 

Register-Specific Instructions 

Some instructions are specific to a certain register. For example, 
some instructions always operate on the Accumulator, or Data 
Pointer, etc., so no address byte is needed to point to it. The opcode 
itself does that. Instructions that refer to the Accumulator as A 
assemble as accumulator specific opcodes. 

Immediate Constants 

The value of a constant can follow the opcode in Program Memory. 
For example, 

MOV A, #100 

loads the Accumulator with the decimal number 100. The same 
number could be specified in hex digits as 64H. 

Indexed Addressing 

Only program Memory can be accessed with indexed addressing, 
and it can only be read. This addressing mode is intended for 
reading look-up tables in Program Memory A 1 6-bit base register 
(either DPTR or the Program Counter) points to the base of the 
table, and the Accumulator is set up with the table entry number. 

The address of the table entry in Program Memory is formed by 
adding the Accumulator data to the base pointer. 

Another type of indexed addressing is used in the "case jump" 
instruction. In this case the destination address of a jump instruction 
is computed as the sum of the base pointer and the Accumulator 

Table 1. 80C51 Arithmetic Instructions 



Arithmetic Instructions 

The menu of arithmetic instructions is listed in Table 1 . The table 
indicates the addressing modes that can be used with each 
instruction to access the <byte> operand. For example, the ADD 
A,<byte> instruction can be written as: 

ADD a, 7FH (direct addressing) 

A, @R0 (indirect addressing) 

.r addressing) 
A, #127 (immediate constant) 

The execution times listed in Table 1 assume a 1 2MHz clock 
frequency. All of the arithmetic instructions execute in 1 us except 
the INC DPTR instruction, which takes 2us, and the Multiply and 
Divide instructions, which take 4us. 

Note that any byte in the internal Data Memory space can be 
incremented without going through the Accumulator. 

One of the INC instructions operates on the 16-bit Data Pointer. The 
Data Pointer is used to generate 1 6-bit addresses for external 
memory, so being able to increment it in one 1 6-bit operation is a 
useful feature. 

The MUL AB instruction multiplies the Accumulator by the data in 
the B register and puts the 1 6-bit product into the concatenated B 
and Accumulator registers. 

The DIV AB instruction divides the Accumulator by the data in the B 
register and leaves the 8-bit quotient in the Accumulator, and the 
8-bit remainder in the B register. 

Oddly enough, DIV AB finds less use in arithmetic "divide" routines 
than in radix conversions and programmable shift operations. An 
example of the use of DIV AB in a radix conversion will be given 
later. In shift operations, dividing a number by 2n shifts its n bits to 
the right. Using DIV AB to perform the division completes the shift in 
4ns and leaves the B register holding the bits that were shifted out. 
The DA A instruction is for BCD arithmetic operations. In BCD 
arithmetic, ADD and ADDC instructions should always be followed 
by a DA A operation, to ensure that the result is also in BCD. Note 
that DA A will not convert a binary number to BCD. The DA A 
operation produces a meaningful result only as the second step in 
the addition of two BCD bytes. 





OPERATION 


ADDRESSING MODES 


EXECUTION 
TIME (ns) 


DIR 


IND 


REG 


IMM 


ADD A,<byte> 


A = A + <byte> 


X 


X 


X 


X 


1 


ADDC A,<byte> 


A = A + <byte> + C 


X 


X 


X 


X 


1 


SUBB A,<byte> 


A = A-<byte>-C 


X 


X 


X 


X 


1 


INC A 


A = A+ 1 


Accumulator only 


1 


INC <byte> 


<byte> = <byte> + 1 


X | X | X | 


1 


INC DPTR 


DPTR = DPTR + 1 


Data Pointer only 


2 


DEC A 


A = A-1 


Accumulator only 


1 


DEC <byte> 


<byte> = <byte> - 1 


X | X | X | 


1 


MULAB 


B:A = B x A 


ACC and B only 


4 


DIV AB 


A = lnt[A/B] 
B = Mod[A/B] 


ACC and B only 


4 




DA A 


Decimal Adjust 


Accumulator only 


1 



March 1995 



2-7 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



Logical Instructions 

Table 2 shows the list of 80C51 logical instructions. The instructions 
that perform Boolean operations (AND, OR, Exclusive OR, NOT) on 
bytes perform the operation on a bit-by-bit basis. That is, if the 
Accumulator contains 0011 01 01 B and byte contains 01 01 001 1 B, 
then: 

ANL A, <byte> 

will leave the Accumulator holding 0001 0001 B. 

The addressing modes that can be used to access the <byte> 
operand are listed in Table 2. 

The ANL A, <byte> instruction may take any of the forms: 
ANL A.7FH (direct addressing) 
ANL A,@R1 (indirect addressing) 
ANL A,R6 (register addressing) 
ANL A,#53H (immediate constant) 

All of the logical instructions that are Accumulator-specific execute 
in 1ns (using a 12MHz clock). The others take 2p.s. 

Note that Boolean operations can be performed on any byte in the 
internal Data Memory space without going through the Ac 
The XRL <byte>, #data instruction, for example, offers a c 
easy way to invert port bits, as in XRL P1 , #OFFH. 

If the operation is in response to an interrupt, not using the 
Accumulator saves the time and effort to push it onto the stack in the 
service routine. 

The Rotate instructions (RL, A, RLC A, etc.) shift the Accumulator 1 
bit to the left or right. For a left rotation, the MSB rolls into the LSB 
position. For a right rotation, the LSB rolls into the MSB position. 

The SWAP A instruction interchanges the high and low nibbles 
within the Accumulator. This is a useful operation in BCD 
manipulations. For example, if the Accumulator contains a binary 
number which is known to be less than 100, it can be quickly 
converted to BCD by the following code: 



Table 2. 80C51 Logical Instructions 



MOVE B,#10 
DIV AB 
SWAP A 
ADD A,B 



Data Transfers 



Dividing the number by 10 leaves the tens digit in the low nibble of 
the Accumulator, and the ones digit in the B register. The SWAP and 
ADD instructions move the tens digit to the high nibble of the 
Accumulator, and the ones digit to the low nibble. 

Internal RAM 

Table 3 shows the menu of instructions that are available for moving 
data around within the internal memory spaces, and the addressing 
modes that can be used with each one. With a 12MHz clock, all of 
these instructions execute in either 1 or 2ns. 

The MOV <dest>, <src> instruction allows data to be transferred 
between any two internal RAM or SFR locations without going 
through the Accumulator. Remember, the Upper 128 bytes of data 
RAM can be accessed only by indirect addressing, and SFR space 
only by direct addressing. 

Note that in 80C51 devices, the stack resides in on-chip RAM, and 
grows upwards. The PUSH instruction first increments the Stack 
Pointer (SP), then copies the byte into the stack. PUSH and POP 
use only direct addressing to identify the byte being saved or 
restored, but the stack itself is accessed by indirect addressing 
using the SP register. This means the stack can go into the Upper 
128 bytes of RAM, if they are implemented, but not into SFR space. 

The Upper 128 bytes of RAM are not implemented in the 80C51 nor 
in its ROMIess or EPROM counterparts. With these devices, if the 
SP points to the Upper 128, PUSHed bytes are lost, and POPed 
bytes are indeterminate. 

The Data Transfer instructions include a 1 6-bit MOV that can be 
used to initialize the Data Pointer (DPTR) for look-up tables in 
Program Memory, or for 1 6-bit external Data Memory accesses. 



MNEMONIC 




ADDRESSING MODES 


EXECUTION 
TIME (us) 


□IR 


IND 


REG 


IMM 


ANL A,<byte> 


A = A.AND. <byte> 


X 


X 


X 


X 


1 


ANL <byte>,A 


<byte> = <byte> .AND.A 


X 








1 


ANL <byte>,#data 


<byte> = <byte> .AND.#data 


X 








2 




ORL A,<byte> 


A = A.OR.<byte> 


X 


X 


X 


X 


1 


ORL <byte>,A 


<byte> = <byte> .OR.A 


X 








1 


ORL <byte>,#data 


<byte> = <byte> .OR.#data 


X 








2 


XRL A,<byte> 


A = A.XOR. <byte> 


X 


X 


X 


X 


1 


XRL <byte>,A 


<byte> = <byte> .XOR.A 


X 








1 


XRL <byte>,#data 


<byte> = <byte> .XOR.#data 


X 








2 


CRL A 


A = 00H 


Accumulator only 


1 


CPLA 


A = .NOT.A 


Accumulator only 


1 


RL A 


Rotate ACC Left 1 bit 


Accumulator only 


1 


RLC A 


Rotate Left through Carry 


Accumulator only 


1 


RR A 


Rotate ACC Right 1 bit 


Accumulator only 


1 


PRC A 


Rotate Right through Carry 


Accumulator only 


1 


SWAP A 


Swap Nibbles in A 


Accumulator only 


1 



March 1995 



2-8 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



Table 3. Data Transfer Instructions that Access Internal Data Memory Space 



MNEMONIC 


OPERATION 


ADDRESSING MODES 


EXECUTION 
TIME ((is) 


DIR 


IND 


REG 


IMM 


MOV A,<src> 


A = <src> 


X 


X 


X 


X 


1 


MOV <dest>,A 


<dest> 5 A 


X 


X 


X 




1 


MOV <dest>,<src> 


<dest> = <src> 


X 


X 


X 


X 


2 


MOV DPTR,#data16 


DPTR = 1 6-bit immediate constant 








X 


2 


PUSH <src> 


INC SP:MOV@SP",<src> 


X 








2 


POP <dest> 


MOV <dest>,"@SP":DECSP 


X 








2 




XCH A,<byte> 


ACC and <byte> exchange data 


X 


X 


X 




1 


XCHD A,@Ri 


ACC and @Ri exchange low nibbles 




X 






1 



The XCH A, <byte> instruction causes the Accumulator and 
addressed byte to exchange data. The XCHD A, @Ri instruction is 
similar, but only the low nibbles are involved in the exchange. 

To see how XCH and XCHD can be used to facilitate data 
manipulations, consider first the problem of shifting an 8-digit BCD 
number two digits to the right. Figure 11 shows how this can be 
done using direct MOVs, and for comparison how it can be done 
using XCH instructions. To aid in understanding how the code 
works, the contents of the registers that are holding the BCD 
number and the content of the Accumulator are shown alongside 
each instruction to indicate their status after the instruction has been 
executed. 

After the routine has been executed, the Accumulator contains the 
two digits that were shifted out on the right. Doing the routine with 
direct MOVs uses 1 4 code bytes and 9(is of execution time 
(assuming a 12MHz clock). The same operation with XCHs uses 
only 9 bytes and executes almost twice as fast. 

To right-shift by an odd number of digits, a one-digit shift must be 
executed. 

Figure 1 2 shows a sample of code that will right-shift a BCD number 
one digit, using the XCHD instruction. Again, the contents of the 
registers holding the number and of the Accumulator are shown 
alongside each instruction. 

First, pointers R1 and RO are set up to point to the two bytes 
containing the last four BCD digits. Then a loop is executed which 



leaves the last byte, location 2EH, holding the last two digits of the 
shifted number. The pointers are decremented, and the loop is 
repeated for location 2DH. The CJNE instruction (Compare and 
Jump if Not Equal) is a loop control that will be described later. The 
loop executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH, and 
2BH. At that point the digit that was originally shifted out on the right 
has propagated to location 2AH. Since that location should be left 
with Os, the lost digit is moved to the Accumulator. 

External RAM 

Table 4 shows a list of the Data Transfer instructions that access 
external Data Memory. Only indirect addressing can be used. The 
choice is whether to use a one-byte address, @ Ri, where Ri can be 
either RO or R1 of the selected register bank, or a two-byte address, 
@ DPTR. The disadvantage to using 1 6-bit addresses if only a few k 
bytes of external RAM are involved is that 16-bit addresses use all 8 
bits of Port 2 as address bus. On the other hand, 8-bit addresses 
allow one to address a few bytes of RAM, as shown in Figure 5, 
without having to sacrifice all of Port 2. All of these instructions 
execute in 2 (is, with a 1 2MHz clock. 

Note that in all external Data RAM accesses, the Accumulator is 
always either the destination or source of the data. 

The read and write strobes to external RAM are activated only 
during the execution of a MOVX instruction. Normally these signals 
are inactive, and in fact if they're not going to be used at all, their 
pins are available as extra I/O lines. 





2A 


2B 


2C 


2D 


2E 


ACC 


MOV A.2EH 


00 


12 


34 


56 


78 


78 


MOV 2EH.2DH 


00 


12 


34 


56 


56 


78 


MOV 20H.2CH 


00 


12 


34 


34 


56 


78 


MOV 2CH.2BH 


00 


12 


12 


34 


56 


78 


MOV 2BH,#0 


00 


00 


12 


34 


56 


78 


A. Using direct MOVs: 14 byt.., 9,,. 




































2A 


2B 


2C 


2D 


2E 


ACC 


CLR A 


00 


12 


34 


56 


78 


00 


XCH A.2BH 


00 


00 


34 


56 


78 


12 


si ^ 


00 


00 


12 


56 


78 


34 




00 


00 


12 


34 


78 


56 


XCH A2EH 


00 


00 


12 


34 


56 


78 


B. Using XCHs: 9 byte 


«.S|18 




































SU00468 



Figure 11 . Shifting a BCD Number Two Digits to the Right 



MOV 
MOV 



R1.#2EH 
R0.#2DH 



2A 


2B 


2C 


2D 


2E 


ACC 


00 


12 


34 


56 


78 


XX 


00 


12 


34 


56 


78 


XX 



loop (or R1 »2EH: 



MOV 


A.8R1 


00 


12 


34 


56 


78 


78 




XCHD 


A,@R0 


00 


12 


34 


58 


78 


76 




SWAP 


A 


00 


12 


34 


58 


78 


67 




MOV 


SR1.A 


00 


12 


34 


58 


67 


67 




DEC 


R1 


00 


12 


34 


58 


67 


67 




DEC 


RO 


00 


12 


34 


58 


67 


67 





CJNE Rl.»2AH.LOOP 



loop tor RI * 2DH: 




00 


12 


38 


45 


67 


45 


loop lor R1 = 2CH: 




00 


18 


23 


45 


67 


23 


loop for R1 = 2BH: 




08 | 


01 


23 


45 


67 1 


01 


CLR A 
XCH A.2AH 




S| 


01 
01 


23 
23 


s 


s| 


00 
08 



Figure 12. Shifting a BCD Number One Digit to the Right 



March 1995 



2-9 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



Table 4. 80C51 Data Transfer Instructions that Access External Data Memory Space 



ADDRESS 
WIDTH 


MNEMONIC 


OPERATION 


EXECUTION 
TIME ((is) 


8 bits 


MOVX A,@Ri 


Read external RAM @Ri 


2 


8 bits 


MOVX @Ri,A 


Write external RAM @ Ri 


2 


16 bits 


MOVX A, ©DPTR 


Read external RAM @ DPTR 


2 


16 bits 


MOVX ©DPTR.A 


Write external RAM @ DPTR 


2 



Table 5. 80C51 Lookup Table Read Instructions 



MNEMONIC 


OPERATION 


EXECUTION TIME (us) 


MOVC A,@A+DPTR 


Read program memory at (A + DPTR) 


2 

- 


MOVC A,@A+PC 


Read program memory at (A + PC) 


2 



Lookup Tables 

Table 5 shows the two instructions that are available for reading 
lookup tables in Program Memory. Since these instructions access 
only Program Memory, the lookup tables can only be read, not 
updated. 

If the tabl e acce ss is to external Program Memory, then the read 
strobe is PSEN. 

The mnemonic is MOVC for "move constant." The first MOVC 
instruction in Table 5 can accommodate a table of up to 256 entries 
numbered through 255. The number of the desired entry is loaded 
into the Accumulator, and the Data Pointer is set up to point to the 
beginning of the table. Then: 

MOVC A, @ A+DPTR 

copies the desired table entry into the Accumulator. 

The other MOVC instruction works the same way, except the 
Program Counter (PC) is used as the table base, and the table is 
accessed through a subroutine. First the number of the desired 
entry is loaded into the Accumulator, and the subroutine is called: 

MOV A, ENTRY NUMBER 

CALL TABLE 

The subroutine 'TABLE" would look like this: 
TABLE: MOVC A,@A+PC 
RET 

The table itself immediately follows the RET (return) instruction in 
Program Memory. This type of table can have up to 255 entries, 
numbered 1 through 255. Number cannot be used, because at the 
time the MOVC instruction is executed, the PC contains the address 
of the RET instruction. An entry numbered would be the RET 
opcode itself. 

Boolean Instructions 

80C51 devices contain a complete Boolean (single-bit) processor. 
The internal RAM contains 128 addressable bits, and the SFR 
space can support up to 128 addressable bits as well. All of the port 
lines are bit-addressable, and each one can be treated as a 
separate single-bit port. The instructions that access these bits are 
not just conditional branches, but a complete menu of move, set, 
clear, complement, OR, and AND instructions. These kinds of bit 
operations are not easily obtained in other architectures with any 
amount of byte-oriented software. 

The instruction set for the Boolean processor is shown in Table 6. All 
bit accesses are by direct addressing. 



Bit addresses OOH through 7FH are in the Lower 128, and bit 
addresses 80H through FFH are in SFR space. 



easily an internal flag can be moved to a port pin: 
MOV C.FLAG 
MOV P1.0.C 

In this example, FLAG is the name of any addressable bit in the 
Lower 1 28 or SFR space. An I/O line (the LSB of Port 1 , in this 
case) is set or cleared depending on whether the flag bit is 1 or 0. 

The Carry bit in the PSW is used as the single-bit Accumulator of 
the Boolean processor. Bit instructions that refer to the Carry bit as 
C assemble as Carry-specific instructions (CLR C, etc.). The Carry 
bit also has a direct address, since it resides in the PSW register, 
which is bit-addressable. 

Note that the Boolean instruction set includes ANL and ORL 
operations, but not the XRL (Exclusive OR) operation. An XRL 
operation is simple to implement in software. Suppose, for example, 
it is required to form the Exclusive OR of two bits: 
C = bit1 XRL. bit2 

The software to do that could be as follows: 

MOV C,bit1 

JNB bit2,OVER 

CPL C 
OVER: (continue) 

First, bit1 is moved to the Carry. If bit2 = 0, then C now contains the 
correct result. That is, bit1 .XRL. bit2 = bit1 if bit2 = 0. On the other 
hand, if bit2 = 1 , C now contains the complement of the correct 
result. It need only be inverted (CPL C) to complete the operation. 

This code uses the JNB instruction, one of a series of bit-test 
instructions which execute a jump if the addressed bit is set (JC, JB, 
JBC) or if the addressed bit is not set (JNC, JNB). In the above 
case, bit2 is being tested, and if bit2 = 0, the CPL C instruction is 
jumped over. 

JBC executes the jump if the addre 

the bit. Thus a flag can be tested and cleared in one operation. All 
the PSW bits are directly addressable, so the Parity bit, or the 
general purpose flags, for example, are also available to the bit-test 
instructions. 

Relative Offset 

The destination address for these jumps is specified to the 
assembler by a label or by an actual address in Program memory. 
However, the destination address assembles to a relative offset 
byte. This is a signed (two's complement) offset byte which is added 
to the PC in two's complement arithmetic if the jump is executed. 
The range of the jump is therefore -128 to +127 Program Memory 
bytes relative to the first byte following the instruction. 



March 1995 



2-10 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



Table 6. 80C51 Boolean Instructions 



MNEMONIC 


App RATION 


EXECUTION TIME (us) 




ANL 


Cbit 




— C AMD hii 




2 




ANL 


C,/bit 




C, - C AND NOThit 


2 


ORL 


Cbit 


C - C OR hit 




2 




ORL 


C/bit 


C-C OR NOThit 




2 




MOV 


Cbit 


C = bit 


1 


MOV 


bit,C 




bit = C 




2 




CLR 


C 


C = 




1 




CLR 


bit 


bit = 





1 





SETB 


C 


C = 1 


1 


SETB 


bit 


bit = 1 


1 


CPL 




C = NOT.C 


1 


CPL 


bit 


bit = .NOT.bit 




1 




JC 


rel 


Jump if C = 1 




2 




JNC 


rel 


Jump if C = 




2 





JB 


bit.rel 


Jump if bit = 1 




2 




JNB 


bit.rel 


Jump if bit = 




2 




JBC 


bit.rel 


Jump if bit = 1 ; CLR bit 





2 


' 














Table 7. 


Unconditional Jumps in 80C51 Devices 








MNEMONIC 


OPERATION 


EXECUTION TIME (us) 


_. 


JMP 


addr 


Jump to addr 




2 




JMP 


©A+DPTR 


Jump to A + DPTR 




2 




CALL 


addr 


Call subroutine at addr 


2 


RET 


Return from subroutine 




2 




RETI 




Return from interrupt 





2 




NOP 


No operation 


1 | 



Jump Instructions 

Table 7 shows the list of unconditional jumps with execution time for 
a 12MHz clock. 

The table lists a single "JMP addr" instruction, but in fact there are 
three SJMP, LJMP, and AJMP, which differ in the format of the 
destination address. JMP is a generic mnemonic which can be used 
if the programmer does not care which way the jump is encoded. 

The SJMP instruction encodes the destination address as a relative 
offset, as described above. The instruction is 2 bytes long, 
consisting of the opcode and the relative offset byte. The jump 
distance is limited to a range of -1 28 to +1 27 bytes relative to the 
instruction following the SJMP. 

The LJMP instruction encodes the destination address as a 16-bit 
constant. The instruction is 3 bytes long, consisting of the opcode 
and two address bytes. The destination address can be anywhere in 
the 64k Program Memory space. 

The AJMP instruction encodes the destination address as an 11 -bit 
constant. The instruction is 2 bytes long, consisting of the opcode, 
which itself contains 3 of the 11 address bits, followed by another 
byte containing the low 8 bits of the destination address. When the 
instruction is executed, these 1 1 bits are simply substituted for the 
low 11 bits in the PC. The high 5 bits stay the same. Hence the 
destination has to be within the same 2k block as the instruction 
following the AJMP. 



In all cases the programmer specifies the destination address to the 
assembler in the same way: as a label or as a 1 6-bit constant. The 
assembler will put the destination address into the correct format for 
the given instruction. If the format required by the instruction will not 
support the distance to the specified destination address, a 
"Destination out of range" message is written into the List file. 

The JMP ©A+DPTR instruction supports case jumps. The 
destination address is computed at execution time as the sum of the 
1 6-bit DPTR register and the Accumulator. Typically, DPTR is set up 
with the address of a jump table. In a 5-way branch, for example, an 
integer through 4 is loaded into the Accumulator. The code to be 
executed might be as follows: 

MOV DPTR,#JUMP TABLE 

MOV A,INDEX_NUMBER 

RL A 

JMP ©A+DPTR 

The RL A instruction converts the index number (0 through 4) to an 
even number on the range through 8, because each entry in the 
jump table is 2 bytes long: 
JUMP TABLE: 

AJMP CASE 

AJMP CASE 1 

AJMP CASE 2 

AJMP CASE 3 

AJMP CASE 4 



March 1995 



2-11 



Philips Semiconductors 



80C51 family architecture 



Table 7 shows a single "CALL addr" instruction, but there are two of 
them, LCALL and ACALL, which differ in the format in which the 
subroutine address is given to the CPU. CALL is a generic 
mnemonic which can be used if the programmer does not care 
which way the address is encoded. 

The LCALL instruction uses the 1 6-bit address format, and the 
subroutine can be anywhere in the 64k Program Memory space. 
The ACALL instruction uses the 1 1 -bit format, and the subroutine 
must be in the same 2k block as the instruction following the 
ACALL. 

In any case, the programmer specifies the subroutine address to the 
assembler in the same way: as a label or as a 16-bit constant. The 
assembler will put the address into the correct format for the given 
instructions. 

Subroutines should end with a RET instruction, which returns 
execution to the instruction following the CALL. 

RETI is used to return from an interrupt service routine. The only 
difference between RET and RETI is that RETI tells the interrupt 
control system that the interrupt in progress is done. If there is no 
interrupt in progress at the time RETI is executed, then the RETI is 
functionally identical to RET. 

Table 8 shows the list of conditional jumps available to the 80C51 
user. All of these jumps specify the destination address by the 
relative offset method, and so are limited to a jump distance of -1 28 
to +127 bytes from the instruction following the conditional jump 
instruction. Important to note, however, the user specifies to the 
assembler the actual destination address the same way as the other 
jumps: as a label or a 1 6-bit constant. 

There is no Zero bit in the PSW. The JZ and JNZ instructions test 
the Accumulator data for that condition. 

The DJNZ instruction (Decrement and Jump if Not Zero) is for loop 
control. To execute a loop N times, load a counter byte with N and 
terminate the loop with a DJNZ to the beginning of the loop, as 
shown below for N = 1 0. 



MOV 
LOOP: (begin loop) 



(end loop) 

DJNZ 

(continue) 



COUNTER,#10 



Table 8. Conditional Jumps in 80C51 Devices 



The CJNE instruction (Compare and Jump if Not Equal) can also be 
used for loop control as in Figure 12. Two bytes are specified in the 
operand field of the instruction. The jump is executed only if the two 
bytes are not equal. In the example of Figure 1 2, the two bytes were 
data in R1 and the constant 2AH. The initial data in R1 was 2EH. 
Every time the loop was executed, R1 was decremented, and the 
looping was to continue until the R1 data reached 2AH. 

Another application of this instruction is in "greater than, less than" 
comparisons. The two bytes in the operand field are taken as 
unsigned integers. If the first is less than the second, then the Carry 
bit is set (1 ). If the first is greater than or equal to the second, then 
the Carry bit is cleared. 

CPU Timing 

All 80C51 microcontrollers have an on-chip oscillator which can be 
used if desired as the clock source for the CPU. To use the on-chip 
oscillator, connect a crystal or ceramic resonator between the 
XTAL1 and XTAL2 pins of the microcontroller, and capacitors to 
ground as shown in Figure 13. 

Examples of how to drive the clock with an external oscillator are 
shown in Figure 14. Note that in the NMOS devices (8051 , etc.) the 
signal at the XTAL2 pin actually drives the internal clock generator. 
In the CMOS devices (80C51 , etc.), the signal at the XTAL1 pin 
drives the internal clock generator. The internal clock generator 
defines the sequence of states that make up the 80C51 machine 
cycle. 



Quartz crystal 
or ceramic 
resonator 



= r T- 



Figure 1 3. Using the On-Chip 



HMOS or 
CMOS 



v S s 



SU00470 



Oscillator 



MNEMONIC 


OPERATION 


ADDRESSING MODES 


EXECUTION 
TIME (us) 


DIR | IND | REG | IMM 


JZ rel 


Jump if A = 


Accumulator only 


2 


JNZ rel 


Jump if A# 


Accumulator only 


2 


DJNZ <byte>,rel 


Decrement and jump if not zero 


X 




X 




2 


CJNE A,<byte>,rel 


Jump if A * <byte> 


X 






X 


2 


CJNE <byte>,#data,rel 


Jump if <byte> # #data 




X 


X 




2 



March 1995 



2-12 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 





XTAL2 


External 
clock 
signal 




XTAL2 




(NC) 


XTAL2 




A 

External 

clock I 


XTAL1 






XTAL1 


External 


XTAL1 




signal 


















vss 




vss 






vss 










a. NMOS or CMOS 


b. NMOS Only 


c. CMOS Only 


SU00471 



Figure 14. Using an External Clock 



Machine Cycles 

A machine cycle consists of a sequence of 6 states, numbered S1 
through S6. Each state time lasts for two oscillator periods. Thus a 
machine cycle takes 12 oscillator periods or 1ns if the oscillator 
frequency is 1 2MHz. 

Each state is divided into a Phase 1 half and a Phase 2 half. 
Figure 1 5 shows that fetch/execute sequences in states and phases 
for various kinds of instructions. Normally two program fetches are 
erated during each machine cycle, even if the instruction being 

i doesn't require it. If the instruction being executed doesn't 
j more code bytes, the CPU simply ignores the extra fetch, and 
s Program Counter is not incremented. 

l of a one-cycle instruction (Figures 15a and 15b) begins 
ring State 1 of the machine cycle, when the opcode is latched into 
i Instruction Register. A second fetch occurs during S4 of the 
s machine cycle. Execution is complete at the end of State 6 of 
his machine cycle. 

The MOVX instructions take two machine cycles to execute. No 
program fetch is generated during the second cycle of a MOVX 
instruction. This is the only time program fetches are skipped. The 
fetch/execute sequence for MOVX instructions is shown in Figure 
15d 



The fetch/execute sequences are the same whether the Program 
Memory is internal or external to the chip. Execution times do not 
depend on whether the Program Memory is internal or external. 

Figure 16 shows the signals and timing involved in program fetches 
when the Program Memory is external. If Program Memory is 
external, then the Program Memory read strobe PSEN" is normally 
activated twice per machine cycle, as shown in Figure 1 6a. If an 
acc ess to external Data Memory occurs, as shown in Figure 16b, 
two PSENs are skipped, because the address and data bus are 
being used for the Data Memory access. 

Note that a Data Memory bus cycle takes twice as much time as a 
Program Memory bus cycle. Figure 16 shows the relative timing of 
the ad dresses being emitted at Ports and 2, and of ALE and 
PS1R. ALE is used to latch the low address byte from PO into the 
address latch. 

When the CPU is executing from internal Program Memory, PSEN is 
not activated, and program addresses are not emitted. However, 
ALE continues to be activated twice per machine cycle and so it is 
available as a clock output signal. Note, however, that one ALE is 
skipped during the execution of the MOVX instruction. 



March 1995 



2-13 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



Osc 
(XTAL2) 

























PI P2 

JUl 




jui 


pi n 

m 


if 


P1 P2 

JUl 


iful 




Read next | 

r Readopcode - r ask 



Read next opcode again. 



S5 



a. 1-byte, 1-cycle Instruction, e.g., INC A 



I 



L 



Read next opcode. 





S1 


S2 


S3 


S4 


SS 


S6 











_Jl 



b. 2-byte, 1-cycle Instruction, < 



[— Read opcode. 



opcode (discard) 1 



Read next opcode again. 



S2 


S3 


S4 


SS 


S6 


S1 


S2 


S3 


S4 


S5 



I 

I 

c. 1-byte, 2-cycle Instruction, e.g., INC DPTR 



Reado 
(MOVX 



I No 
| (etch. 



Read next 
- opcode (discard) 



Read next opcode again. 
No fetch. 



d. MOVX (1-byte, 2-cycle) 



Figure 15. State Sequence in 80C51 Family Devices 



March 1995 



Philips Semiconductors 

80C51 Family 80C51 family architecture 



One Machine Cycle 



One Machine Cycle 



ALE , 

PSEN 
RD 



_H H R- 



| S4 | S5 | ! 



j n r 



P2 PCH out 



X 



X 



X 



X 



PO 



INST \J PCL 




ST V/ p CL \ f INST VJ PCL \— < INST V/ PCL \__/ INST V7 P1 =L 

*\ out r \ in A ° ul / \ in A ou ' l \ " A oul 



LPCL out PCL out PCL out 

Valid 1 Valid 1 Valid 



PCL out 
Valid 



L 



PCL out 
Valid 



a. Without a 



MOVX 



Cycle 1 



Cycle 2 















82 


S3 


S4 


S5 S6 


SI 


S2 


S3 


S4 


S5 | S6 




DPH out or P2 out 



b. With a MOVX 




Figure 16. Bus Cycles in 80C51 Family Devices Executing from External Program Memory 



March 1995 



2-15 



Philips Semiconductors 



80C51 Family 



80C51 family architecture 



(MSB) 



(LSB) 



ES 


X 


X 


ES 


ET1 


EX1 


ETO 


EXO 



Symbol Position Function 

ES IE.7 Disables all interrupts. If ES = 0, no 

interrupt will be acknowledged. If ES = 1 , 
each interrupt source is individually 
enabled or disabled by setting or clearing 
its enable bit. 

IE.6 Reserved. 

IE.5 Reserved. 

ES IE.4 Enables or disables the Serial Port 
interrupt. If ES = 0, the Serial Port 
interrupt is disabled. 

ET1 IE.3 Enables or disables the Timer 1 Overflow 
interrupt. If ET1 = 0, the Timer 1 interrupt 
is disabled. 

IE.2 Enables or disables External Interrupt 1 . 

If EX1 = 0, External Interrupt 1 is disabled. 
IE.1 Enables or disables the Timer Overflow 
interrupt. If ETO = 0, the Timer interrupt 
is disabled. 

EXO IE.0 Enables or disables Exetemal Interrupt 0. 

If EXO = 0, External Interrupt is disabled. 



EX1 
ETO 



(MSB) 



(LSB) 



X 


X 


X 


PS 


PT1 


PX1 


PTO 


PXO 



PT1 
PX1 
PTO 
PXO 



Figure 17. Interrupt Enable (IE) Register 







Symbol Position Function 

IP.7 Re 



PS 



IP.4 



IP.3 



IP.1 



IPO 



Defines the Serial Port interrupt priority 
level. PS = 1 programs it to the higher 
priority level. 

Defines the Timer 1 interrupt priority 
level. PT1 = 1 programs it to the higher 
priority level. 

Defines the External Interrupt 1 priority 
level. PX1 = 1 programs it to the higher 
priority level. 

Enables or disables the Timer Interrupt 
priority level. PT) = 1 programs it to the 
higher priority level. 

Defines the External Interrupt priority 
level. PXO = 1 programs it to the higher 
priority level. 



Figure 18. Interrupt Priority (IP) Register 



IE Register 



ruTO" — cr ito 




i v - r 



' IT1 



cr^ o-off o- 



o-crjo- 



'o-offo 



-or^ o-crfo 



-o^ o-ori^o 



IP Register 



Global 
Disable 



Figure 19. Interrupt Control 



High Priority 
Interrupt 



March 1995 



Philips Semiconductors 



80C51 Family 80C51 family architecture 



— 



Interrupt Structure 

The 80C51 and its ROMIess and EPROM versions have 5 interrupt 
sources: 2 external interrupts, 2 timer interrupts, and the serial port 
interrupt. 

What follows is an overview of the interrupt structure for the device. 
More detailed information for specific members of the 80C51 
derivative family is provided in later chapters of this user's guide. 

Interrupt Enables 

Each interrupt source can be individually enabled or disabled by 
setting or clearing a bit in the SFR named IE (Interrupt Enable). This 
register also contains a global disable bit, which can be cleared to 
disable all interrupts at once. Figure 17 shows the IE register. 

Interrupt Priorities 

Each interrupt source can also be individually programmed to one of 
two priority levels by setting or clearing a bit in the SFR named IP 
(Interrupt Priority). Figure 18 shows the IP register. A low-priority 
interrupt can be interrupted by a high-priority interrupt, but not by 
another low-priority interrupt. A high-priority interrupt can't be 
interrupted by any other interrupt source. 

If two interrupt requests of different priority levels are received 
simultaneously, the request of higher priority is serviced. If interrupt 
requests of the same priority level are received simultaneously, an 
internal polling sequence determines which request is serviced. 
Thus within each priority level there is a second priority structure 
determined by the polling sequence. Figure 1 9 shows how the IE 
and IP registers and the polling sequence work to determine which if 
any interrupt will be serviced. 

In operation, all the interrupt flags are latched into the interrupt 
control system during State 5 of every machine cycle. The samples 
are polled during the following machine cycle. If the flag for an 
enabled interrupt is found to be set (1 ), the interrupt system 
generates an LCALL to the appropriate location in Program Memory, 
unless some other condition blocks the interrupt. Several conditions 
can block an interrupt, among them that an interrupt of equal or 
higher priority level is already in progress. 

The hardware-generated LCALL causes the contents of the 
Program Counter to be pushed into the stack, and reloads the PC 
with the beginning address of the service routine. As previously 



noted (Figure 3), the service routine for each interrupt begins at a 
fixed location. 

Only the Program Counter is automatically pushed onto the stack, 
not the PSW or any other register. Having only the PC automatically 
saved allows the programmer to decide how much time should be 
spent saving other registers. This enhances the interrupt response 
time, albeit at the expense of increasing the programmer's burden of 
responsibility. As a result, many interrupt functions that are typical in 
control applications toggling a port pin for example, or reloading a 
timer, or unloading a serial buffer can often be completed in less 
time than it takes other architectures to complete. 

Simulating a Third Priority Level in Software 

Some applications require more than two priority levels that are 
provided by on-chip hardware in 80C51 devices. In these cases, 
relatively simple software can be written to produce the same effect 
as a third priority level. First, interrupts that are to have higher 
priority than 1 are assigned to priority 1 in the Interrupt Priority (IP) 
register. The service routines for priority 1 interrupts that are 
supposed to be interruptable by priority 2 interrupts are written to 
include the following code: 

PUSH IE 

MOV IE,#MASK 

CALL LABEL 

(execute service routine) 

POP IE 
RET 

LABEL: RETI 

As soon as any priority interrupt is acknowledged, the Interrupt 
Enable (IE) register is redefined so as to disable all but priority 2 
interrupts. Then a CALL to LABEL executes the RETI instruction, 
which clears the priority 1 interrupt-in-progress flip-flop. At this point 
any priority 1 interrupt that is enabled can be serviced, but only 
priority 2 interrupts are enabled. 

POPing IE restores the original enable byte. Then a normal RET 
(rather than another RETI) is used to terminate the service routine. 
The additional software adds 10ns (at 12MHz) to priority 1 
interrupts. 



March 1995 



HARDWARE DESCRIPTION 

This chapter provides a detailed description of the 80C51 
microcontroller (see Figure 1). Included in this description are: 

• The port drivers and how they function both as ports and, for Ports 
and 2, in bus operations 

• The Timers/Counters 




• The Serial Interface 

• The Interrupt System 

• Reset 

• The Reduced Power Modes in CMOS devices 

• The EPROM version of the 80C51 



r 







PortO 
Drivers 



7\ 



Port 2 
Drivers 



PortO 
Latch 



_1 



Port 2 
Latch 



EPROM/ /!_ 
ROM 



Stack 
I p °™« I 



_SZ 




1Z 



ALE 
EA~- 
RST 



Timing 

and 
Control 



Instruction 
Register 



'HDI— " 
HhjHH 



PCON 


SCON 


TMOD 


TCON 


T2CON 


THO 


TLO 


TH1 


TL1 










SBUF 


IE 


IP 




Interrupt, Serial 






Port. 
E 


and Timer 
locks 





Program 
Address 
Register 



o 



PC 
Incrementef 



JO 



Program 
Counter 



2 



Porn 
Drivers 



I 



~- -Ifflf— ■ 



H 



-N] Port 3 
Drivers 



WW- 

P3.0-P3.7 



Figure 1. B0C51 Architecture 



1996 Aug 12 



2-18 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 



Special Function Registers 

A Map of the on-chip memory area called the Special Function 
- T (SFR) space is shown in Figure 2. 



Note that in the SFRs not all of the addresses are occupied. 
Unoccupied addresses are not implemented on the chip. Read 
accesses to these addresses will in general return random data, and 
write accesses will have no effect. 

User software should not write 1 s to these unimplemented locations, 
since they may be used in other 80C51 Family derivative products 
to invoke new features. The functions of the SFRs are described in 
the text that follows. 

Accumulator 

ACC is the Accumulator register. The mnemonics for 
Accumulator-Specific instructions, however, refer to the Accumulator 
simply as A. 

B Register 

The B register is used during multiply and divide operations. For 
other instructions it can be treated as another scratch pad register. 

Program Status Word 

The PSW register contains program status information as detailed in 
Figure 3. 

Stack Pointer 

The Stack Pointer register is 8 bits wide. It is incremented before 
data is stored during PUSH and CALL executions. While the stack 
may reside anywhere in on-chip RAM, the Stack Pointer is initialized 
to 07H after a reset. This causes the stack to begin at locations 08H. 

Data Pointer 

The Data Pointer (DPTR) consists of a high byte (DPH) and a low 
byte (DPL). Its intended function is to hold a 1 6-bit address. It may 
be manipulated as a 1 6-bit register or as two independent 8-bit 

registers. 



Ports to 3 

PO, P1 , P2, and P3 are the SFR latches of Ports 0,1,2, and 3, 
respectively. Writing a one to a bit of a port SFR (PO, P1 , P2, or P3) 
causes the corresponding port output pin to switch high. Writing a 
zero causes the port output pin to switch low. When used as an 
input, the external state of a port pin will be held in the port SFR 
(i.e., if the external state of a pin is low, the corresponding port SFR 
bit will contain a 0; if it is high, the bit will contain a 1 ). 

Serial Data Buffer 

The Serial Buffer is actually two separate registers, a transmit buffer 
and a receive buffer. When data is moved to SBUF, it goes to the 
transmit buffer and is held for serial transmission. (Moving a byte to 
SBUF is what initiates the transmission.) When data is moved from 
SBUF, it comes from the receive buffer. 

Timer Registers Basic to 80C51 

Register pairs (THO, TLO), and (TH1 , TL1 ) are the 1 6-bit Counting 
registers for Timer/Counters and 1 , respectively. 

Control Register for the 80C51 

Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON 
contain control and status bits for the interrupt system, the 
Timer/Counters, and the serial port. They are described in later 
sections. 

Port Structures and Operation 

All four ports in the 80C51 are bidirectional. Each consists of a latch 
(Special Function Registers PO through P3), an output driver, and an 
input buffer. 

The output drivers of Ports and 2, and the input buffers of Port 0, 
are used in accesses to external memory. In this application, Port 
outputs the low byte of the external memory address, 
time-multiplexed with the byte being written or read. 

Port 2 outputs the high byte of the external memory address when 
the address is 16 bits wide. Otherwise, the Port 2 pins continue to 
emit the P2 SFR content. 



F8 
F0 



E0 
D8 



BO 
AS 



















B 
































ACC 
































PSW 
















































IP 
















P3 
















IE 
















P2 
















SCON 


SBUF 














PI 
















TCON 


TMOD 


TLO 


TL1 


THO 


TH1 






PO 


SP 


DPL 


DPH 








PCON 



BIT ADDRESSABLE 



E7 
DF 
D7 
CF 

C7 



SF 
87 



Figure 2. 80C51 SFR Memory Map 



1996 Aug 12 



2-19 



Phlips Semiconductors 



80C51 Family 




80C51 family hardware description 


i 1 



MSB 



LSB 





















CY 


AC 


FO 


RS1 


RSO 


OV 




P 



BIT 

PSW.7 
PSW.6 
PSW.5 
PSW.4 

PSW.3 



PSW.2 OV 
PSW.1 — 
PSW.O P 



SYMBOL FUNCTION 

CY Carry flag. 

AC Auxilliary Carry flag. (For BCD operations.) 

FO Flag 0. (Available to the user for general purposes. ) 

RS1 Register bank select control bit 1 . 

Set/cleared by software to determine working register bank. (See Note.) 
RSO Register bank select control bit 0. 

Set/cleared by software todetermine working register bank. (See Note.) 
Overflow flag. 
User-definable flag. 
P Parity flag. 

Set/cleared by hardware each instruction cycle to indicate an odd/even 
number of "one" bits in the Accumulator, i.e., even parity. 



NOTE: The contents of (RS1 , RSO) enable the working register banks as follows: 
(0,0)— Bank (00H-07H) 
(0,1)— Bank 1 (08H-0fH) 
(10H-17H) 
(3 (18H-17H) 



Figure 3. 



Word (PSW) Re 



All the Port 3 pins are multifunctional. They are not only port pins, 
but also serve the functions of various special features as listed 
below: 



Port Pin 

P3.0 
P3.1 
P3.2 
P3.3 
P3.4 
P3.5 
P3.6 
P3.7 



Alternate Function 

RxD (serial input port) 

TxD (serial output port) 

INTO (external interrupt) 

INT1 (external interrupt) 

TO (Timer/Counter external input) 

T1 (Timer/Counter 1 external input) 

WR (external Data Memory write strobe) 

RTJ (external Data Memory read strobe) 



The alternate functions can only be activated if the corresponding bit 
latch in the port SFR contains a 1 . Otherwise the port pin remains at 0. 

I/O Configurations 

Figure 4 shows a functional diagram of a typical bit latch and I/O 
buffer in each of the four ports. The bit latch (one bit in the port's 
FR) is represented as a Type D flip-flop, which will clock in a value 
i the internal bus in response to a "write to latch" signal from the 
PU. The level of the port pin itself is placed on the internal bus in 
nse to a "read pin" signal from the CPU. Some instructions that 
f a port activate the "read latch" signal, and others activate the 
1 pin" signal. 

As shown in Figure 4, the output drivers of Port and 2 are 
switchable to an internal ADDR and ADDR/DATA bus by an internal 
CONTROL signal for use in external memory accesses. During 
external memory accesses, the P2 SFR remains unchanged, but the 
P0 SFR gets 1s written to it. 

Also shown in Figure 4 is that if a P3 bit latch contains a 1 , then the 
output level is controlled by the signal labeled "alternate output 
function." The actual P3.X pin level is always available to the pin's 
alternate input function, if any. 

Ports 1 , 2, and 3 have internal pullups, and Port has open drain 
outputs. Each I/O line can be independently used as an input or an 
output. (Port and 2 may not be used as general purpose I/O when 



being used as the ADDR/DATA BUS for external memory during 
normal operation.) To be used as an input, the port bit latch must 
contain a 1 , which turns off the output driver FET. Then, for Ports 1 , 
2, and 3, the pin is pulled high by a weak internal pullup, and can be 
pulled low by an external source. 

Port differs in that its internal pullups are not active during normal 
port operation. The pullup FET in the P0 output driver (see Figure 4) 
is used only when the port is emitting 1s during external memory 
accesses. Otherwise the pullup FET is off. Consequently P0 lines 
that are being used as output port lines are open drain. Writing a 1 
to the bit latch leaves both output FETs off, so the pin floats. In that 
condition it can be used as a high-impedance input. 

Because Ports 1 , 2, and 3 have fixed internal pullups, they are 
sometimes called "quasi- bidirectional" ports. When configured as 
inputs they pull high and will source current (l||_, in the data sheets) 
when externally pulled low. Port 0, on the other hand, is considered 
"true" bidirectional, because when configured as an input it floats. 

All the port latches in the 80C51 have 1s written to them by the reset 
function. If a is subsequently written to a port latch, it can be 
reconfigured as an input by writing a 1 to it. 

Writing to a Port 

In the execution of an instruction that changes the value in a port 
latch, the new value arrives at the latch during S6P2 of the final 
cycle of the instruction. However, port latches are in fact sampled by 
their output buffers only during Phase 1 of an clock period. (During 
Phase 2 the output buffer holds the value it saw during the previous 
Phase 1). Consequently, the new value in the port latch won't 
actually appear at the output pin until the next Phase 1 , which will be 
at S1 P1 of the next machine cycle. 

If the change requires a 0-to-1 transition in Port 1 , 2, or 3, an 
additional pullup is turned on during S1 P1 and S1 P2 of the cycle in 
which the transition occurs. This is done to increase the transition 
speed. The extra pullup can source about 1 00 times the current that 
the normal pullup can. It should be noted that the internal pullups 
are field-effect transistors, not linear resistors. The pullup 
arrangements are shown in Figure 5. 



1996 Aug 12 



2-20 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 



Read 
Latch 



ADDR/Dala 

Control 



D 


Q 


POX 




Latch 




CL 







vcc 



Read v cc 
Utch 1 










D 




Q 




P1.X 






Utch 




CL 







Internal 
Pullup* 



a. Port Bit 



b. Port 1 



Bit 



o 

:H 1 



ADDR/Data 

Control " Cc 



Write to 
Utch 



D 




Q 




P2.X 






Utch 




CL 




Q 




Alternate 
Output 
Function 



Latch 1 



Write to 
Utch 



D 


Q 


P3.X 




Utch 




CL 






v cc 



Internal 
Pullup' 



P3.X 
Pin 



c Port 2 Bit 




•See Figure 5 for details of the internal pullup. 

Figure 4. 80C51 Port Bit Latches and I/O Buffers 



In the NMOS 8051 part, the fixed part of the pullup is a depletion 
mode transistor with the gate wired to the source. This transistor will 
allow the pin to source about 0.25mA when shorted to ground. In 
parallel with the fixed pullup is an enhancement mode transistor, 
which is activated during S1 whenever the port bit does a 0-to-1 
transition. During this interval, if the port pin is shorted to ground, 
this extra transistor will allow the pin to source an additional 30mA. 

In the CMOS 80C51 , the pullup consists of three pFETs. It should be 
noted that an n-channel FET (nFET) is turned on when a logical 1 is 
applied to its gate, and is turned off when a logical is applied to its 
gate. A p-channel FET (pFET) is the opposite: it is on when its gate 
sees a 0, and off when its gate sees a 1 . 

pFET1 in Figure 5 is the transistor that is turned on for 2 oscillator 
periods after a 0-to-1 transition in the port latch. While it's on, it turns 
on pFET3 (a weak pullup), through the inverter. This inverter and 
pFET3 form a latch which holds the 1 . 

Note that if the pin is emitting a 1 , a negative glitch on the pin from 
some external source can turn off pFET3, causing the pin to go into 



a float state. pFET2 is a very weak pullup which is on whenever the 
nFET is off, in traditional CMOS style. It's only about 1/1 the 
strength of pFET1 . Its function is to restore a 1 to the pin in the 
event the pin had a 1 and lost it to a glitch. 

Port Loading and Interfacing 

The output buffers of Ports 1 , 2, and 3 can each drive 4 LS TTL 
inputs. These ports on NMOS versions can be driven in a normal 
manner by a TTL or NMOS circuit. Both NMOS and CMOS pins can 
be driven by open-collector and open-drain outputs, but note that 
0-to-1 transitions will not be fast. 

In the NMOS device, if the pin is driven by an open-collector output, 
a 0-to-1 transition will have to be driven by the relatively weak 
depletion mode FET in Figure 5a. In the CMOS device, an input 
turns off pullup pFET3, leaving only the very weak pullup pFET2 to 
drive the transition. 

Port output buffers can each drive 8 LS TTL inputs. They do, 
however, require external pullups to drive NMOS inputs, except 
when being used as the ADDRESS/DATA bus for external memory. 



1996 Aug 12 



2-21 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 



v C c 



o[>- 

From Port 




vss 



a. NMOS Configuration. 

The enhancement mode transistor is turned on for 2 oscillator periods after Q makes a 0-to-1 transition. 



2 Osc. Periods 



vcc v cc v cc 



L> rlL> r\L 



Input Data Q 



Port 
Pin 



Read Port Pin C> 

b. CMOS Configuration. 
pFET1 is turned on for 2 oscillator periods after Q makes a 0-to-1 transition. 
During this time, pFET1 also turns on pFET3 through the inverter to form a latch which holds the 1. pFET2 is also on. 



Figure 5. Ports 1 and 3 NMOS and CMOS Internal Pullup Configurations 

(Port 2 is similar except that it holds the strong pullup on while emitting 1s that are address bits. See Accessing External Memory.) 



Read-Modify-Write Feature 

Some instructions that read a port read the latch and others read the 
pin. Which ones do which? The instructions that read the latch 
rather than the pin are the ones that read a value, possibly change 
it, and then rewrite it to the latch. These are called 
"read-modify-write" instructions. The instructions listed below are 
read-modify-write instructions. When the destination operand is a 
port, or a port bit, these instructions read the latch rather than the 
pin: 

ANL (logical AND, e.g., ANL P1 ,A) 

ORL (logical OR, e.g., ORL P2.A) 

XRL (logical EX-OR, e.g., XRL P3.A) 

JBC (jump if bit = 1 and clear bit, e.g., JBC P1 . 1 .LABEL) 

CPL (complement bit, e.g., CPL P3.0) 

INC (increment, e.g., INC P2) 

DEC (decrement, e.g., DEC P2) 

DJNZ (decrement and jump if not zero, 

e.g., DJNZ P3.LABEL) 
MOV PX. Y,C (move carry bit to bit Y of Port X) 
CLR PX.Y (clear bit Y of Port X) 
SET PX.Y (set bit Y of Port X) 



It is not obvious that the last three instructions in this list are 
read-modify-write instructions, but they are. They read the port byte, 
all 8 bits, modify the addressed bit, then write the new byte back to 
the latch. 

The reason that read-modify-write instructions are directed to the 
latch rather than the pin is to avoid a possible misinterpretation of 
the voltage level at the pin. For example, a port bit might be used to 
drive the base of a transistor. When a 1 is written to the bit, the 
transistor is turned on. If the CPU then reads the same port bit at the 
pin rather than the latch, it will read the base voltage of the transistor 
and interpret it as a 0. Reading the latch rather than the pin will 
return the correct value of 1 . 



1996 Aug 12 



2-22 



80C51 family hardware description 



Phlips Semiconductors 



80C51 Family 



Accessing External Memory 

Accesses to external memory are of two types: accesses to external 
Program Memory and accesses to external Data Memory. Accesses 
to external Program Memory use signal PSEN (program store 
enable) as the read strobe. Accesses to external Data Memory use 
RTJ or WR (alternate functions of P3.7 and P3.6) to strobe the 
memory. Fetches from external Program Memory always use a 
1 6-bit address. Accesses to external Data Memory can use either a 
16-bit address (MOVX @ DPTR) or an 8-bit address (MOVX @Ri). 

Whenever a 16-bit address is used, the high byte of the address 
comes out on Port 2, where it is held for the duration of the read or 
write cycle. Note that the Port 2 drivers use the strong pullups during 
the entire time that they are emitting address bits that are 1s. This is 
during the execution of a MOVX ODPTR instruction. During this 
time the Port 2 latch (the Special Function Register) does not have 
to contain 1 s, and the contents of the Port 2 SFR are not modified. If 
the external memory cycle is not immediately followed by another 
external memory cycle, the undisturbed contents of the Port 2 SFR 
will reappear in the next cycle. 

If an 8-bit address is being used (MOVX @Ri), the contents of the 
Port 2 SFR remain at the Port 2 pins throughout the external 
memory cycle. This will facilitate paging. 

In any case, the low byte of the address is time-multiplexed with the 
data byte on Port 0. The ADDR/DATA signals drive both FETs in the 
Port output buffers. Thus, in this application the Port pins are not 
open-drain outputs, and do not require external pullups. ALE 
(Address Latch Enable) should be used to capture the address byte 
into an external latch. The address byte is valid at the negative 
transition of ALE. Then, in a write cycle, the data byte to be written 
appears on Port just before WR is activated, and remains there 
until after WR is deactivated. In a read cycle, the incoming byte is 
accepted at Port just before the read strobe is deactivated. 

During any access to external memory, the CPU writes OFFH to the 
Port latch (the Special Function Register), thus obliterating 
whatever information the Port SFR may have been holding. 

External Program Memory is accessed under two conditions: 
Whenever signal EA" is active; or whenever the program counter 
(PC) contains a number that is larger than OFFFH (in the 80C51 ). 

This require that the ROMIess versions have ES wired low to enable 
the lower 4k program bytes to be fetched from external memory. 

When the CPU is executing out of external Program Memory, all 8 
b ts of Port 2 are dedicated to an output function and may not be 
used for general purpose I/O. During external program fetches they 
output the high byte of the PC. During this time the Port 2 drivers 
use the strong pullups to emit PC bits that are 1s. 

Timer/Counters 

The 80C51 has two 16-bit Timer/Counter registers: Timer and 
Tmer 1 . Both can be configured to operate either as timers or event 
counters (see Figure 6). 

In the "Timer function, the register is incremented every machine 
cycle. Thus, one can think of it as counting machine cycles. Since a 
machine cycle consists of 12 oscillator periods, the count rate is 
1/12 of the oscillator frequency. 

In the "Counter" function, the register is incremented in response to 
a 1 -to-0 transition at its corresponding external input pin, TO or T1 . 
In this function, the external input is sampled during S5P2 of every 
machine cycle. 

When the samples show a high in one cycle and a low in the next 
cycle, the count is incremented. The new count value appears in the 



register during S3P1 of the cycle following the one in which the 
transition was detected. Since it takes 2 machine cycles (24 
oscillator periods) to recognize a 1-to-0 transition, the maximum 
count rate is 1/24 of the oscillator frequency. There are no 
restrictions on the duty cycle of the external input signal, but to 
ensure that a given level is sampled at least once before it changes, 
it should be held for at least one full cycle. In addition to the Timer" 
or "Counter" selection, Timer and Timer 1 have four operating 
modes from which to select. 

Timer and Timer 1 

The Timer" or "Counter" function is selected by control bits C/T in 
the Special Function Register TMOD. These two Timer/Counters 
have four operating modes, which are selected by bit-pairs (M1 , MO) 
in TMOD. Modes 0, 1 , and 2 are the same for both Timers/Counters. 
Mode 3 is different. The four operating modes are described in the 
following text. 

Mode 

Putting either Timer into Mode makes it look like an 8048 Timer, 
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 7 
shows the Mode operation as it applies to Timer 1 . 

In this mode, the Timer register is configured as a 13-bit register. As 
the count rolls over from all 1 s to all 0s, it sets the Timer interrupt 
flag TF1 . The counted input is enabled to the Timer when TR1 = 1 
and either GATE = or TTCTT = 1 . (Setti ng GA TE = 1 allows the 
Timer to be controlled by external input TNTT, to facilitate pulse width 
measurements). TR1 is a control bit in the Special Function Register 
TCON (Figure 8). GATE is in TMOD. 

The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits 
of TL1 . The upper 3 bits of TL1 are indeterminate and should be 
ignored. Setting the run flag (TR1 ) does not clear the registers. 

Mode operation is the same for the Timer as for Timer 1 . 
Substitute TRO, TFO, and INTO for the corresponding Timer 1 
signals in Figure 7. There are two different GATE bits, one for Timer 
1 (TMOD.7) and one for Timer (TMOD.3). 

Model 

Mode 1 is the same as Mode 0, except that the Timer register is 
being run with all 1 6 bits. 

Mode 2 

Mode 2 configures the Timer register as an 8-bit Counter (TL1 ) with 
automatic reload, as shown in Figure 9. Overflow from TL1 not only 
sets TF1 , but also reloads TL1 with the contents of TH1 , which is 
preset by software. The reload leaves TH1 unchanged. 

Mode 2 operation is the same for Timer/Counter 0. 

Mode 3 

Timer 1 in Mode 3 simply holds its count. The effect is the same as 
setting TR1 = 0. 

Timer in Mode 3 establishes TL0 and TH0 as two separate 
counters. The logic for Mode 3 on Timer is shown in Figure 10. 
TL0 uses the Timer control bits: C/T, GATE, TRO, INTO, and TFO. 
TH0 is locked into a timer function (counting machine cycles) and 
takes over the use of TR1 and TF1 from Timer 1 . Thus, TH0 now 
controls the Timer 1" interrupt. 

Mode 3 is provided for applications requiring an extra 8-bit timer on 
the counter. With Timer in Mode 3, an 80C51 can look like it has 
three Timer/Counters. When Timer is in Mode 3, Timer 1 can be 
turned on and off by switching it out of and into its own Mode 3, or 
can still be used by the serial port as a baud rate generator, or in 
fact, in any application not requiring an interrupt. 



1996 Aug 12 



2-23 



Philips Semiconductors 



80C51 Family 



80C51 family hardware description 



M1 




1 



1 



MSB 



LSB 



GATE 


C/T 


M1 


MO 


GATE 


C/T 


M1 


MO 








j 












Y 






Y 





TIMER 



GATE 
C/T 



TIMER 1 

Gating control when set. Timer/Counter V is enabled only while 
"TRx" control pin is set. when cleared Timer "x" is enabled whenevi 
Timer or Counter Selector cleared for Timer operatio 
Set for Counter operation (input from Tx" input pin). 




is high and 
control bit is set. 
system clock.) 



MO OPERATING 

8048 Timer "TLx" serves as 5-bit prescaler. 

1 1 6-bit Timer/Counter THx" and 'TLx" are cascaded; there is no prescaler. 

8-bit auto-reload Timer/Counter THx" holds a value which is to be reloaded 

into "TLx" each time it overflows. 

(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer control bits. 
THO is an 8-bit timer only controlled by Timer 1 control bits. 

(T.merDT.mer/Counten stopped. 



1 



Figure 6. Timer/Counter Mode Control (TMOD) Register 



Osc. 




+12 





| C/T=1 



Gate £>> 



IWITPin 




o- 



TL1 
(5 Bits) 



TF1 



Figure 7. 



0: 13-Bit Counter 



MSB 














LSB 




TF1 


TR1 


TFO 


TRO 


IE1 


IT1 


IE0 


ITO 



1 



BIT 


SYMBOL 


TCON.7 


TF1 


TCON.6 


TR1 


TCON.5 


TFO 


TCON.4 


TRO 


TCON.3 


IE1 


TCON.2 


IT1 


TCON.1 


IE0 


TCON.O 


ITO 







■ I 



FUNCTION 

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. 

Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. 
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. 
Timer overflow flag. Set by hardware on Timer/Counter overflow. 

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. 
Timer Run control bit. Set/cleared by software to turn Timer/Counter on/off. 
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. 
Cleared when interrupt processed. 

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered 
external interrupts. 

Interrupt Edge flag. Set by hardware when external interrupt edge detected. 
Cleared when interrupt processed. 

Interrupt Type control bit. Set/cleared by software to specify falling edge/low level 
triggered external interrupts. 



SU00536 

' 



Figure 8. 



Control (TCON) Register 



1996 Aug 12 



Phlips Semiconductors 

80C51 Family 80C51 family hardware description 



J C/T.O 




tpfr-1 

Q 



TL1 
(8 Bits) 



Control 




Interrupt 



TH1 

(S Bits) 



Figure 9. Timer/Counter Mode 2: 8-Bit Auto-Load 





- 



1'12lQSC 



C/T = 



C/T»1 




TLX) 
(8 Bits) 



Interrupt 



1'12tOSC 



TRl 



THO 

(8 Bits) 



10. Timer/Counter Mode 3: Two 8-Bit Counters 



1996 Aug 12 



Phlips Semiconductors 



80C51 Family 80C51 family hardware description 



Stand 

The serial port is full duplex, meaning it can transmit and receive 
simultaneously. It is also receive-buffered, meaning it can 
commence reception of a second byte before a previously received 
byte has been read from the register. (However, if the first byte still 
hasn't been read by the time reception of the second byte is 
complete, one of the bytes will be lost.) The serial port receive and 
transmit registers are both accessed at Special Function Register 
SBUF. Writing to SBUF loads the transmit register, and reading 
SBUF accesses a physically separate receive r 



! serial port can operate in 4 modes: 



Mode 
Moc 



0: Serial data enters and exits through RxD. TxD outputs 
the shift clock. 8 bits are transmitted/received (LSB first). 
The baud rate is fixed at 1/12 the oscillator frequency. 

! 1 : 10 bits are transmitted (through TxD) or received 

(through RxD): a start bit (0), 8 data bits (LSB first), and 
a stop bit (1 ). On receive, the stop bit goes into RB8 in 
Special Function Register SCON. The baud rate is 
variable. 

Mode 2: 11 bits are transmitted (through TxD) or received 

(through RxD): start bit (0), 8 data bits (LSB first), a 
programmable 9th data bit, and a stop bit (1). On 
Transmit, the 9th data bit (TB8 in SCON) can be 
assigned the value of or 1 . Or, for example, the parity 
bit (P, in the PSW) could be moved into TB8. On receive, 
the 9th data bit goes into RB8 in Special Function 
Register SCON, while the stop bit is ignored. The baud 
rate is programmable to either 1/32 or 1/64 the oscillator 
frequency. 

Mode 3: 1 1 bits are transmitted (through TxD) or received 

(through RxD): a start bit (0), 8 data bits (LSB first), a 
programmable 9th data bit, and a stop bit (1). In fact, 
Mode 3 is the same as Mode 2 in all respects except 
baud rate. The baud rate in Mode 3 is variable. 

In all four modes, transmission is initiated by any instruction t 
uses SBUF as a destination register. Reception is in 
by the condition Rl = and REN = 1 . Reception is initiated in the 
other modes by the incoming start bit if REN = 1 . 



Multiprocessor Communications 

Modes 2 and 3 have a special provision for multiprocessor 
communications. In these modes, 9 data bits are received. The 9th 
one goes into RB8. Then comes a stop bit. The port can be 
programmed such that when the stop bit is received, the serial port 
interrupt will be activated only if RB8 = 1 . This feature is enabled by 
setting bit SM2 in SCON. A way to use this feature in multiprocessor 
systems is as follows: 

When the master processor wants to transmit a block of data to one 
of several slaves, it first sends out an address byte which identifies 
the target slave. An address byte differs from a data byte in that the 
9th bit is 1 in an address byte and in a data byte. With SM2 = 1 , no 



slave will be interrupted by a data byte. An address byte, however, 
will interrupt all slaves, so that each slave can examine the received 
byte and see if it is being addressed. The addressed slave will clear 
its SM2 bit and prepare to receive the data bytes that will be coming. 
The slaves that weren't being addressed leave their SM2s set and 
go on about their business, ignoring the coming data bytes. 

SM2 has no effect in Mode 0, and in Mode 1 can be used to check 
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1 , the 
receive interrupt will not be activated unless a valid stop bit is 
received. 

Serial Port Control Register 

The serial port control and status register is the Special Function 
Register SCON, shown in Figure 11 . This register contains not only 
the mode selection bits, but also the 9th data bit for transmit and 
receive (TB8 and RB8), and the serial port interrupt bits (Tl and Rl). 

Baud Rates 

The baud rate in Mode is fixed: Mode Baud Rate = Oscillator 
Frequency / 12. The baud rate in Mode 2 depends on the value of 
bit SMOD in Special Function Register PCON. If SMOD = (which 
is the value on reset), the baud rate is 1/64 the oscillator frequency. 
If SMOD = 1 , the baud rate is 1/32 the oscillator frequency. 

Mode 2 Baud Rate = 

2 SMOD 



64 



x (Oscillator Frequency) 



2SMOD 

32 



x (Timer 1 Overflow Rate) 



The Timer 1 interrupt should be disabled in this application. The 
Timer itself can be configured for either "timer" or "counter" 
operation, and in any of its 3 running modes. In the most typical 
applications, it is configured for "timer" operation, in the auto-reload 
mode (high nibble of TMOD = 001 0B). In that case the baud rate is 
given by the formula: 

Mode 1,3 Baud Rate = 

2SMQD Oscillator Frequency 
32 X 12 x [256 - (TH1)] 

One can achieve very low baud rates with Timer 1 by leaving the 
Timer 1 interrupt enabled, and configuring the Timer to run as a 
16-bit timer (high nibble of TMOD = 0001 B), and using the Timer 1 
interrupt to do a 1 6-bit software reload. Figure 1 2 lists various 
commonly used baud rates and how they can be obtained from 
Timer 1 . 



In the 80C51 , the baud rates in Modes 1 and 3 are determined by 
the Timer 1 overflow rate. 

Using Timer 1 to Generate Baud Rates 

When Timer 1 is used as the baud rate generator, the baud rates in 
Modes 1 and 3 are determined by the Timer 1 overflow rate and the 
value of SMOD as follows: 

Mode 1 , 3 Baud Rate = 



1996 Aug 12 



2-26 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 







SM2 

REN 
TB8 
RB8 

Rl 



SMO 


SM1 


SM2 


REN 


TBS 


RB8 


Tl 


Rl 



























Where SMO, SM1 specify the serial port mode, as follows: 
SMO SM1 Mode Description Baud Rate 



shift register 

8- bit UART 

9- bit UART 
9-bit UART 



fosc/12 
variable 

fosc/64 or fosc/32 
variable 



Enables the multiprocessor communication feature in Modes 2 and 3, In Mode 2 or 3, if J 
activated if the received 9th data bit (RB8) is 0. In Mode 1 , if SM2=1 then Rl v "' 
received. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1 , it SM2=0, RB8 is the stop bit that was received. In Mode 0, 
RB8 is not used. 

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or a 
modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other 
modes, in any serial reception (except see SM2). Must be cleared by software. 








! is set to 1 , then Rl will not be 
J if a valid stop bit was not 



ing of the stop bit in the other 



SU00120 



Figure 11. Serial Port Control (SCON) Register 



Baud Rate 


'osc 


SMOD 


Timer 1 


C/T 


Mode 


Reload Value 




Mode Max: 1.67MHz 


20MHz 


X 


X 


X 


X 




Mode 2 Max: 625k 


20MHz 


1 


X 


X 


X 




Mode 1,3 Max: 104.2k 


20MHz 


1 





2 


FFH 




19.2k 


11.059MHz 


1 





2 


FDH 




9.6k 


11.059MHz 








2 


FDH 




4.8k 


11.059MHz 








2 


FAH 




2.4k 


11.059MHz 








2 


F4H 




1.2k 


11.059MHz 








2 


E8H 




137.5 


11.986MHz 








2 


1 DH 




110 


6MHz 








2 


72H 




110 


12MHz 








1 


FEEBH 
I 



Figure 12. Timer 1 Generated Commonly Used Baud Rates 



More About Mode 

Serial data enters and exits through RxD. TxD outputs the shift 
clock. 8 bits are transmitted/received: 8 data bits (LSB first). The 
baud rate is fixed a 1 /1 2 the oscillator frequency. 

Figure 1 3 shows a simplified functional diagram of the serial port in 
Mode 0, and associated timing. 

Transmission is initiated by any instruction that uses SBUF as a 
destination register. The "write to SBUP signal at S6P2 also loads a 
1 into the 9th position of the transmit shift register and tells the TX 
Control block to commence a transmission. The internal timing is 
such that one full machine cycle will elapse between "write to SBUP 
and activation of SEND. 

SEND enables the output of the shift register to the alternate output 
function line of P3.0 and also enable SHIFT CLOCK to the alternate 
output function line of P3.1 . SHIFT CLOCK is low during S3, S4, and 
S5 of every machine cycle, and high during S6, S1 , and S2. At 
S6P2 of every machine cycle in which SEND is active, the c 
of the transmit shift are shifted to the right one position. 



As data bits shift out to the right, zeros come in from the left. When 
the MSB of the data byte is at the output position of the shift register, 
then the 1 that was initially loaded into the 9th position, is just to the 
left of the MSB, and all positions to the left of that contain zeros. 
This condition flags the TX Control block to do one last shift and 
then deactivate SEND and set T1 . Both of these actions occur at 
S1P1 of the 10th machine cycle after "write to SBUF." 

Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 
of the next machine cycle, the RX Control unit writes the bits 
11111110 to the receive shift register, and in the next clock phase 
activates RECEIVE. 

RECEIVE enable SHIFT CLOCK to the alternate output function line 
of P3.1 . SHIFT CLOCK makes transitions at S3P1 and S6P1 of 
every machine cycle. At S6P2 of every machine cycle in which 
RECEIVE is active, the contents of the receive shift register are 
shifted to the left one position. The value that comes in from the right 
is the value that was sampled at the P3.0 pin at S5P2 of the same 
machine cycle. 



1996 Aug 12 



2-27 



Phlips Semiconductors 

80C51 Family 80C51 family hardware description 



As data bits come in from the right, 1 s shift out to the left. When the 
that was initially loaded into the rightmost position arrives at the 
leftmost position in the shift register, it flags the RX Control block to 
do one last shift and load SBUF. At S1 P1 of the 1 0th machine cycle 
after the write to SCON that cleared Rl, RECEIVE is cleared as Rl is 
set. 

More About Mode 1 

Ten bits are transmitted (through TxD), or received (through RxD): a 
start bit (0), 8 data bits (LSB first), and a s 
stop bit goes into RB8 in SCON. In the 8C 
determined by the Timer 1 overflow rate. 

Figure 14 shows a simplified functional d 
Mode 1 , and e 



) bit (1). On receive, the 
I the baud rate is 



More About Modes 2 and 3 

Eleven bits are transmitted (through TxD), or received (through 
RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data 
bit, and a stop bit (1 ). On transmit, the 9th data bit (TB8) can be 
assigned the value of or 1 . On receive, the 9the data bit goes into 
RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 
the oscillator frequency in Mode 2. Mode 3 may have a variable 
baud rate generated from Timer 1 . 

Figures 15 and 16 show a functional diagram of the serial port in 
Modes 2 and 3. The receive portion is exactly the same as in Mode 
1 . The transmit portion differs from Mode 1 only in the 9th bit of the 
transmit shift register. 



Transmission is initiated by any instruction that uses SBUF as a 
destination register. The "write to SBUF signal also loads a 1 into 
the 9th bit position of the transmit shift register and flags the TX 
Control unit that a transmission is requested. Transmission actually 
commences at S1P1 of the machine cycle following the next rollover 
in the divide-by-1 6 counter. (Thus, the bit times are synchronized to 
the divide-by-1 6 counter, not to the "write to SBUF" signal.) 

The transmission begins with activation of SEND which puts the 
start bit at TxD. One bit time later, DATA is activated, which enables 
the output bit of the transmit shift register to TxD. The first shift pulse 
occurs one bit time after that. 

As data bits shift out to the right, zeros are clocked in from the left. 
When the MSB of the data byte is at the output position of the shift 
register, then the 1 that was initially loaded into the 9th position is 
just to the left of the MSB, and all positions to the left of that contain 
zeros. This condition flags the TX Control unit to do one last shift 
and then deactivate SEND and set Tl. This occurs at the 10th 
divide-by-1 6 rollover after "write to SBUF." 

Reception is initiated by a detected 1-to-0 transition at RxD. For this 
purpose RxD is sampled at a rate of 1 6 times whatever baud rate 
has been established. When a transition is detected, the 
divide-by-1 6 counter is immediately reset, and 1FFH is written into 
the input shift register. Resetting the divide-by-1 6 counter aligns its 
rollovers with the boundaries of the incoming bit times. 

The 1 6 states of the counter divide each bit time into 1 6ths. At the 
7th, 8th, and 9th counter states of each bit time, the bit detector 
samples the value of RxD. The value accepted is the value that was 
seen in at least 2 of the 3 samples. This is done for noise rejection. 
If the value accepted during the first bit time is not 0, the receive 
circuits are reset and the unit goes back to looking for another 1 -to-0 
transition. This is to provide rejection of false start bits. If the start bit 
proves valid, it is shifted into the input shift register, and reception of 
the rest of the frame will proceed. 

As data bits come in from the right, 1 s shift out to the left. When the 
start bit arrives at the leftmost position in the shift register (which in 
mode 1 is a 9-bit register), it flags the RX Control block to do one 
last shift, load SBUF and RB8, and set Rl. The signal to load SBUF 
and RB8, and to set Rl, will be generated if, and only if, the following 
conditions are met at the time the final shift pulse is generated.: 

1. R1 =0, and 

2. Either SM2 = 0, or the received stop bit = 1 . 

If either of these two conditions is not met, the received frame is 
irretrievably lost. If both conditions are met, the stop bit goes into 
RB8, the 8 data bits go into SBUF, and Rl is activated. At this time, 
whether the above conditions are met or not, the unit goes back to 
looking for a 1-to-0 transition in RxD. 

■ 



>rt in 

Transmission is initiated by any instruction that uses SBUF as a 
destination register. The "write to SBUP signal also loads TB8 into 
the 9th bit position of the transmit shift register and flags the TX 
Control unit that a transmission is requested. Transmission 
commences at S1 P1 of the machine cycle following the next rollover 
in the divide-by-1 6 counter. (Thus, the bit times are synchronized to 
the divide-by-16 counter, not to the "write to SBUP signal.) 



The transmission begins with activation of SEND, which puts the 
start bit at TxD. One bit time later, DATA is activated, which enables 
the output bit of the transmit shift register to TxD. The first shift pulse 
occurs one bit time after that. The first shift clocks a 1 (the stop bit) 
into the 9th bit position of the shift register. Thereafter, only zeros 
are clocked in. Thus, as data bits shift out to the right, zeros are 
clocked in from the left. When TB8 is at the output position of the 
shift register, then the stop bit is just to the left of TB8, and all 
positions to the left of that contain zeros. This condition flags the TX 
Control unit to do one last shift and then deactivate SEND and set 
Tl. This occurs at the 11th divide-by-16 rollover after "write to SUBF." 

Reception is initiated by a detected 1-to-0 transition at RxD. For this 
purpose RxD is sampled at a rate of 16 times whatever baud rate 
has been established. When a transition is detected, the 
divide-by-1 6 counter is immediately reset, and 1 FFH is written to the 
input shift register. 

At the 7th, 8th, and 9th counter states of each bit time, the bit 
detector samples the value of R-D. The value accepted is the value 
that was seen in at least 2 of the 3 samples. If the value accepted 
during the first bit time is not 0, the receive circuits are reset and the 
unit goes back to looking for another 1 -to-0 transition. If the start bit 
proves valid, it is shifted into the input shift register, and reception of 
the rest of the frame will proceed. 

As data bits come in from the right, 1 s shift out to the left. When the 
start bit arrives at the leftmost position in the shift register (which in 
Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do 
one last shift, load SBUF and RB8, and set Rl. 

The signal to load SBUF and RB8, and to set Rl, will be generated 
if, and only if, the following conditions are met at the time the final 
shift pulse is generated. 

1. Rl = 0,and 

2. Either SM2 = 0, or the received 9th data bit = 1 . 

If either of these conditions is not met, the received frame is 
irretrievably lost, and Rl is not set. If both conditions are met, the 
received 9th data bit goes into RB8, and the first 8 data bits go into 
SBUF. One bit time later, whether the above conditions were met or 
not, the unit goes back to looking for a 1 -to-0 transition at the RxD 
input. 



1996 Aug 12 



2-28 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 



Writs 
SBUF 



REN 



80C51 Internal Bus 



CL 




] 



Serial 
Port 
Interrupt 



Start 


Shift 


TX Clock 


TX Control 


T1 Send 




RX Clock 


RI RBceive 
RX Control Shitl 


Start 


11111110 




1 li-.-W 1 11 




Input Shift Register U 



P3.0 Ail 
Output 
Function 




Shift 




Clock 





TxD 
P3.1 Alt 
Output 
Function 



RxD 
P3.0 Alt 



80C51 Internal Bus 



S4 . 
ALE 



S1 .... S6 S1 .... S6 St .... S6 St .... S6 S1 .... S6 S1 .... S6l SI ... . S6 S1....S6S1....S6S1. 



ji_n 



r | Write to 
S6P2 



SBUP 



jt n n_n_n n_n n_n n_n n_n n_r 







_n_ 



RxD (Data Out) \ 00 )( D1 X " 



JT. 



_TL 



JT_ 



^ 05 )T D6 )T 



TxD (Shift Clock) 



p i Wrile lo SCON (Clear RI) 



RI 1 
Receive 



_n_ 



JT- 



JT_ 



JT_ 



JT. 



JT. 



JT. 



> Receive 



RxD (Data tn) 



-fj^ D- 22 0-^— 0^- 



TxD (Shift Clock) 



Figure 13. Serial Port Mode 



1996 Aug 12 



2-29 




Sample 



1-to-0 
Transition 
Detector 



RX Clock Rl 


Load 


SBUF 


RX Control 


Shift 


Start 






1FFH 



eh 



P, v^ -i 

Input Shift Register 

(9 Bits) r * - ^ 

T~Shilt 



Input Shift P 
1 (9 Bits 



Read 
SBUF 



SBUF 



80C51 Internal Bus 



J D_ 



Jl II L 



f | Write to SBUF 



tSen 



J L 



J clock fl ILL 



X 



J L 



RxD 

Bit Detector 



i B r / do x pi x 02 y 03 ^ x ^ x ^ y 



_j o n n o n n o n l 







— 



J" 



rigure ih. oenai run rv?oae l 



> Transmit 



> Receive 



1996 Aug 12 



2-30 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 




80C51 Internal E 



Phase 2 Clock 
(1/2 lose) 









D b Q 






CL 








Stop Bit 
Start Gen. 



X 



5en3 




f SMOD = 
— > rcunn ic 



(SMOD is 
PCON.7) 



Serial 
Port 
Interrupt 



ml 





Sample 


RX Clock R1 


Load 
SBUF 


1-to-0 
Transition 




RX Control 

Start 


Shift 


Dete 


ctor 






1FFH 



» j Bit Detector [ . 



Input Shirt Register I 
(9 Bits) 



Load 
SBUF 



[ 



SBUF 



I 



80C51 Internal Bus 



jlAji n II D D_ 



J [ 1 1 L 



k s 



Shitt 



J L 



j n it ii il 



\ Transmit 



TxD 


^\StartBrl / D0 


X 


D1 


X 


02 X 


D3 


X 


D4 


X 


D5 


X 


D6 


X 


D7 


X 


TB8 


y 


Stop Bit 


Tl 


































j 




Stop Bit Gen. 


' 
































j 




RX 

n n 


- 16 Reset 




































ni n 


n 




11 


n 




n 




A 




n 




i 




n 




n 


n 




RxD 


I at' / do 


X 


D1 


X 


D2 X 


D3 


X 


D4 




D5 




D6 




D7 




RB8 




Stop Bit 


Bit Detector 
Sample Times 






1 




INI 


Ml 




Ml 




1 




m 




ItT 




Ml 




Ml 


Shift 






1) 




1 


11 




D 




11 








1) 




n 




n 


Rl 
































i 







\ Receive 



1996 Aug 12 



Figure 15. Serial Port Mode 2 

2-31 



Phlips Semiconductors 

80C51 Family 80C51 family hardware description 



Timer 1 
Overflow 



80C5 1 Inter nal Bus 

EE 



Write 

to 
SBUF 



JT D S Q 

CL 




T 



Start Shift Data 

TX Control 

TX Clock T1 Sena 




Si 



1-to-O 
Transition 



RX Clock HI 


Load 


SBUF 


RX Control 


Shift 


Start 






1FFH 




80C51 Internal Bus 



TX 

fl Clock f| 









n 




ii 







n 


J IL 




n w '« e 


to SBUF 
























• wn 






















Data 


T_S1P1| 


















1 




Shift 


n 




n n 


n 









fi 


n 


n n 






TxD 


\StartBil / DO X 


D1 


y « x 


D3 X 


D4 


X 


D5 


X 




x ™y 


Stop Bit 


Tl 




















_r 




























Stop Bit Gen 


1 


















i 




RX 

n ci °<* n 


+ 1 6 Reset 

ni n n 




n n 


1 




o 




i 


1 


n n 


n 




RxD 


| Bif / DO X 


D1 


X at X os TL 


D4 


X 


D5 


X 


06 X D7 


x ™ y 


Stop Bit 


Bit Detector 
Sample Times 


Ml Ml 


Ml 


m 


in 


m 




Ml 






m 


■ 


Shift 


n n 


II 




n 


n 




n 




n n 


n 





Figure 1 6. Serial Port Mode 3 



1996 Aug 12 



2-32 



Philips Semiconductors 



80C51 Family 



80C51 family hardware description 




- | IEO | " 



^ IE1 | — »- 



\ Interrupt 
' Sources 



Figure 17. S0C51 Interrupt Sources 

Interrupts 

The 80C51 provides 5 interrupt sources. These are shown in Figure 
17. The External Interrupts INTO and INT1 can each be either 
level-activated or transition-activated, depending on bits ITO and IT1 
in Register TCON. The flags that actually generate these interrupts 
are bits IEO and IE1 in TCON. When an external interrupt is 
generated, the flag that generated it is cleared by the hardware 
hen the service routine is vectored to only if the interrupt was 
nsition-activated. If the interrupt was level-activated, then the 
ernal requesting source is what controls the request flag, rather 
i the on-chip hardware. 

The Timer and Timer 1 Interrupts are generated by TFO and TF1 , 
which are set by a rollover in their respective Timer/Counter 
registers (except see Timer in Mode 3). When a timer interrupt is 
generated, the flag that generated it is cleared by the on-chip 
hardware when the service routine is vectored to. 

The Serial Port Interrupt is generated by the logical OR of Rl and Tl. 
Neither of these flags is cleared by hardware when the service 
routine is vectored to. In fact, the service routine will normally have 
to determine whether it was Rl or Tl that generated the interrupt, 
and the bit will have to be cleared in software. 

All of the bits that generate interrupts can be set or cleared by 
software, with the same result as though it had been set or cleared 
by hardware. That is, interrupts can be generated or pending 
interrupts can be canceled in software. 

Each of these interrupt sources can be individually enabled or 
disabled by setting or clearing a bit in Special Function Register IE 
(Figure 18). IE also contains a global disable bit, EA, which disables 
all interrupts at once. 

Priority Level Structure 

Each interrupt source can also be individually programmed to one of 
two priority levels by setting or clearing a bit in Special Function 



Register IP (Figure 19). A low-priority interrupt can itself be 
interrupted by a high-priority interrupt, but not by another low-priority 
interrupt. A high-priority interrupt can't be interrupted by any other 
interrupt source. 

If two request of different priority levels are received simultaneously, 
the request of higher priority level is serviced. If requests of the 
same priority level are received simultaneously, an internal polling 
sequence determines which request is serviced. Thus within each 
priority level there is a second priority structure determined by the 
polling sequence as follows: 

Priority Within Level 

(highest) 



Source 

1. IEO 

2. TFO 

3. IE1 

4. TF1 

5. RI+TI 



(lowest) 



Note that the "priority within level" structure is only used to resolve 
simultaneous requests of the same priority level. 

The IP register contains a number of unimplemented bits. IP.7, IP.6, 
and IP.5 are reserved in the 80C51 . User software should not write 
1s to these positions, since they may be used in other 8051 Family 
products. 

How Interrupts Are Handled 

The interrupt flags are sampled at S5P2 of every machine cycle. 
The samples are polled during the following machine cycle. If one of 
the flags was in a set condition at S5P2 of the preceding cycle, the 
polling cycle will find it and the interrupt system will generate an 
LCALL to the appropriate service routine, provided this 
hardware-generated LCALL is not blocked by any of the following 
conditions: 

1 . An interrupt of equal or higher priority level is already in 
progress. 

2. The current (polling) cycle is not the final cycle in the execution 
of the instruction in progress. 

3. The instruction in progress is RETI or any write to the IE or IP 
registers. 

Any of these three conditions will block the generation of the LCALL 
to the interrupt service routine. Condition 2 ensures that the 
instruction in progress will be completed before vectoring to any 
service routine. Condition 3 ensures that if the instruction in 
progress is RETI or any access to IE or IP, then at least one more 
instruction will be executed before any interrupt is vectored to. 

The polling cycle is repeated with each machine cycle, and the 
values polled are the values that were present at S5P2 of the 
previous machine cycle. Note that if an interrupt flag is active but not 
being responded to for one of the above conditions, if the flag is not 
still active when the blocking condition is removed, the denied 
interrupt will not be serviced. In other words, the fact that the 
interrupt flag was once active but not serviced is not remembered. 
Every polling cycle is new. 



1996 Aug 12 



2-33 



MSB 



LSB 



EA 


X 


X 


ES 


ET1 


EX1 


ETO | EXO 



BIT 



SYMBOL 



IE.7 


EA 






IE.6 




IE.5 




IE.4 


ES 


IE.3 


ET1 


IE.2 


EX1 


IE.1 


ETO 


IE.0 


EXO 



FUNCTION 

Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1 , each interrupt 
source is individually enabled or disabled by setting or clearing its enable bit. 



Reserved. 

Enables or disables the Serial Port interrupt. If ES=0, the Serial Port interrupt is disabled. 
Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled. 
Enables or disables External Interrupt 1 . If EX1 =0, External interrupt 1 is disabled. 
Enables or disables the Timer Overflow interrupt. If ET0=0, the Timer interrupt is disabled. 
Enables or disables External interrupt 0. If EX0=0, External interrupt is disabled. 



Figure 18. Interrupt Enable Register (IE) 




MSB 



LSB 



X 


X 


X 


PS 


PT1 


PX1 


PTO 


PXO 



BIT 


SYMBOL 


IP.7 


— 


IP.6 




IP.5 




IP.4 


PS 


IP.3 


PT1 


IP.2 


PX1 


IP.1 


PTO 


IPO 


PXO 







FUNCTION 

Reserved. 
Reserved. 
Reserved. 

Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level. 
Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level. 
Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level. 
Enables or disables the Timer interrupt priority level. PT0=1 programs it to the higher priority level 
Defines the External Interrupt priority level. PX0=1 programs it to the higher priority level. 





Figure 1 9. Interrupt Priority Register (IP) 



C2 - 



| S5P2 | S6 | 

i n n n. 



-IV 



4V 



-IV 



Interrupts 
Are Polled 



Interrupt 
Goes 
Active 



Interrupt 
Latched 



Long Call to 
Interrupt 
Veclor Address 



Interrupt Routine 



This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP. 




Figure 20. Interrupt Response Timing Diagram 

The polling cycle/LCALL sequence is illustrated in Figure 20. 



Note that if an interrupt of higher priority level goes active prior to 
S5P2 of the machine cycle labeled C3 in Figure 20, then in 
accordance with the above rules it will be vectored to during C5 and 
C6, without any instruction of the lower priority routine having been 
executed. 

Thus the processor acknowledges an interrupt request by executing 
a hardware-generated LCALL to the appropriate servicing 
some cases it also clears the flag that generated the interrupt, and in 
other cases it doesn't. It never clears the Serial Port flag. This has to 
be done in the user's software. It clears an external interrupt flag 
(IE0 or IE1 ) only if it was transition-activated. The 



hardware-generated LCALL pushes the contents of the Program 
Counter on to the stack (but it does not save the PSW) and reloads 
the PC with an address that depends on the source of the interrupt 
being vectored to, as shown below: 



Source 

IE0 

TF0 

IE1 

TF1 

RI+TI 



Vector Address 

0003H 
000BH 
001 3H 
001 BH 
0023H 



Execution proceeds from that location until the RETI instruction is 
encountered. The RETI instruction informs the processor that this 



1996 Aug 12 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware description 



interrupt routine is no longer in progress, then pops the top two 
bytes from the stack and reloads the Program Counter. Execution of 
the interrupted program continues from where it left off. 

Note that a simple RET instruction would also have returned 
execution to the interrupted program, but it would have left the 
interrupt control system thinking an interrupt was still in progress, 
making future interrupts impossible. 

External Interrupts 

The external sources can be programmed to be level-activated or 
transition-activated by setting or clearing bit IT1 or ITO in Register 
TCON. If ITx - 0, external interrupt x is triggered by a detected low 
at the INTx pin. If ITx = 1 , external interrupt x is edge triggered. In 
this mode if successive samples of the INTx pin show a high in one 
cycle and a low in the next cycle, interrupt request flag lEx in TCON 
is set. Flag bit lEx then requests the interrupt. 

Since the external interrupt pins are sampled once each machine 
cycle, an input high or low should hold for at least 1 2 oscillator 
periods to ensure sampling. If the external interrupt is 
transition-activated, the external source has to hold the request pin 
high for at least one cycle, and then hold it low for at least one cycle. 
This is done to ensure that the transition is seen so that interrupt 
request flag lEx will be set. lEx will be automatically cleared by the 
CPU when the service routine is called. 

If the external interrupt is level-activated, the external source has to 
hold the request active until the requested interrupt is actually 
generated. Then it has to deactivate the request before the interrupt 
service routine is completed, or else another interrupt will be 
generated. 

Response Time 

The INTO and INT1 levels are inverted and latched into IE0 and IE1 
at S5P2 of every machine cycle. The values are not actually polled 
by the circuitry until the next machine cycle. If a request is active 
and conditions are right for it to be acknowledged, a hardware 
subroutine call to the requested service routine will be the next 
instruction to be executed. The call itself takes two cycles. Thus, a 
minimum of three complete machine cycles elapse between 
activation of an external interrupt request and the beginning of 
execution of the first instruction of the service routine. Figure 20 
shows interrupt response timings. 

A longer response time would result if the request is blocked by one 
of the 3 previously listed conditions. If an interrupt of equal or higher 
priority level is already in progress, the additional wait time obviously 
depends on the nature of the other interrupt's service routine. If the 
instruction in progress is not in its final cycle, the additional wait time 
cannot be more the 3 cycles, since the longest instructions (MUL 
and DIV) are only 4 cycles long, and if the instruction in progress is 
RETI or an access to IE or IP, the additional wait time cannot be 
more than 5 cycles (a maximum of one more cycle to complete the 
instruction in progress, plus 4 cycles to complete the next instruction 
if the instruction is MUL or DIV). 

Thus, in a single-interrupt system, the response time is always more 
than 3 cycles and less than 9 cycles. 

Single-Step Operation 

The 80C51 interrupt structure allows single-step execution with very 
little software overhead. As previously noted, an interrupt request 
will not be responded to while an interrupt of equal priority level is 
still in progress, nor will it be responded to after RETI until at least 



one other instruction has been executed. Thus, once an interrupt 
routine has been entered, it cannot be re-entered until at least one 
instruction of the interrupted program is executed. One way to use 
this feature for single-step operation is to program one of the 
external interrupts (e.g., INTO) to be level-activated. The service 
routine for the interrupt will terminate with the following code: 

JNB P3.2,$ ;Wait Till WTO Goes High 
JB P3.2,$ ;Wait Till INTO Goes Low 
RETI ;Go Back and Execute One Instruction 

Now if the INTO pin, which is also the P3.2 pin, is held normally low, 
the CPU will go right into the External Interrupt routine and stay 
there until INTO is pulsed (from low to high to low). Then it will 
execute RETI, go back to the task program, execute one instruction, 
and immediately re-enter the External Interrupt routine to await the 
next pulsing of P3.2. One step of the task program is executed each 
time P3.2 is pulsed. 

Reset 

The reset input is the RST pin, which is the input to a Schmitt 
Trigger. A reset is accomplished by holding the RST pin high for at 
least two machine cycles (24 oscillator periods), while the oscillator 
is running. The CPU responds by generating an internal reset, with 
the timing shown in Figure 21 . 

The external reset signal is asynchronous to the internal clock. The 
RST pin is sampled during State 5 Phase 2 of every machine cycle. 
The port pins will maintain their current activities for 1 9 oscillator 
periods after a logic 1 has been sampled at the RST pin; that is, for 
19 to 31 oscillator periods after the external reset signal has been 
applied to the RST pin. 

The internal reset algorithm writes 0s to all the SFRs except the port 
latches, the Stack Pointer, and SBUF. The port latches are initialized 
to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. Table 
1 lists the SFR reset values. The internal RAM is not affected by 
reset. On power up the RAM content is indeterminate. 



Table 1. 



80C51 SFR Reset Values 



REGISTER 



PC 
ACC 
B 

PSW 
SP 

DPTR 
P0-P3 
IP 
IE 

TMOD 
TCON 
THO 
TLO 
TH1 
TL1 
SCON 
SBUF 

PCON (NMOS) 
PCON (CMOS) 



RESET VALUE 



000H 

00H 

00H 

00H 

07H 
0000H 

FFH 
XXX000OOB 
0XXOOOOOB 

00H 

00H 

00H 

00H 

00H 

00H 

00H 
Indeterminate 
OXXXXXXXB 
OXXXO000B 



1996 Aug 12 



2-35 



Phlips Semiconductors 



80C51 Family 



family hardware description 



| S5 | S6 ( SI | S2 | S3 | S4 | S5 | S6 | S1 | S2 | S3 | S4 | S5 | S6 | S1 | S2 | S3 j S4 | 

minimi 



Sample HST 



Sample RST 



j— Internal Reset Signal 



nr 



ArJdr.Y Inst. Y Addr. 



11 Osc. Periods 



Addr. 
19 Osc. Periods 




Power-on Reset 

An automatic reset can be obtained when V C c is turned on by 
connecting the RST pin to V cc through a 1 0ut capacitor and to V ss 
through an 8.2k resistor, providing the V cc rise time does not 
exceed 1 millisecond and the oscillator start-up time does not 
exceed 10 milliseconds. This power-on reset circuit is shown in 
Figure 22. The CMOS devices do not require the 8.2k pulldown 
resistor, although its presence does no harm. 

When power is turned on, the circuit holds the RST pin high for an 
amount of time that depends on the value of the capacitor and the 
rate at which it charges. To ensure a good reset, the RST pin must 
be high long enough to allow the oscillator time to start-up (normally 
a few ms) plus two machine cycles. 

Note that the port pins will be in a random state until the oscillator 
has started and the internal reset algorithm has written 1s to them. 

With this circuit, reducing Vcc quickly to causes the F 
voltage to momentarily fall below 0V. However, this 
internally limited, and will not harm the device. 

Power-Saving Modes of Operation 

For applications where power consumption is critical the CMOS 
version provides power reduced modes of operation as a standard 
feature. The power down mode in NMOS devices is no longer a 
standard feature. 

CMOS Power Reduction Mode 

CMOS versions have two power reducing modes, Idle and Power 
Down. The input through which backup power is supplied during 
these operations is V cc . Figure 23 shows the internal circuitry which 
implements these features. In the Idle modes (IDL = 1), the oscillator 
continues to run and the Interrupt, Serial Port, and Timer blocks 
continue to be clocked, but the clock signal is gated off to the CPU. 
In Power Down (PD = 1), the oscillator is frozen. The Idle and Power 
Down Modes are activated by setting bits in Special Function 
Register PCON. The address of this register is 87H. Figure 24 
details its contents. 

In the NMOS devices the PCON register only contains SMOD. The 
other four bits are implemented only in the CMOS devices. User 



Figure 21. Reset Timing 

software should never write 1s to unimplemented bits, since they 
may be used in other 80C51 Family products. 



Idle Mode 

An instruction that sets PCON.O causes that to be the last 
instruction executed before going into the Idle mode, the internal 
clock signal is gated off to the CPU but not to the Interrupt, Timer, 
and Serial Port functions. The CPU status is preserved in its 
entirety; the Stack Pointer, Program Counter, Program Status Word, 
Accumulator, and all other registers maintain their data during Idle. 
The port pins hold the logical states they had at the time Idle was 
activated. ALE and PSEN hold at logic high levels. 

There are two ways to terminate the Idle. Activation of any enabled 
interrupt will cause PCON.O to be cleared by hardware, terminating 
the Idle mode. The interrupt will be serviced, and following RETI, the 
next instruction to be executed will be the one following the 
instruction that put the device into Idle. 

The flag bits GFO and GF1 can be used to give an indication if an 
interrupt occurred during normal operation or during an Idle. For 
example, an instruction that activates Idle can also set one or both 
flag bits. When Idle is terminated by an interrupt, the interrupt 
service routine can examine the flag bits. The other way of 
terminating the Idle mode is with a hardware reset. Since the clock 
oscillator is still running, the hardware reset needs to be held active 
for only two machine cycles (24 oscillator periods) to complete the 
reset. 

The signal at the RST pin clears the IDL bit directly and 
asynchronously. At this time the CPU resumes program execution 
from where it left off; that is, at the instruction following the one that 
invoked the Idle Mode. As shown in Figure 21 , two or three machine 
cycles of program execution may take place before the internal reset 
algorithm takes control. On-chip hardware inhibits access to the 
internal RAM during this time, but access to the port pins is not 
inhibited, so, the insertion of 3 NOP instructions is recommended 
following the instruction that invokes idle mode. To eliminate the 
possibility of unexpected outputs at the port pins, the instruction 
following the one that invokes Idle should not be one that writes to a 
port pin or to external Data RAM. 



1996 Aug 12 



Phlips Semiconductors 



80C51 Family 



hardware description 



Vcc- 



S.2k£l i 



| 



Vcc 

80C51 



Vss 







Figure 22. Power-On Reset Circuit 




XTAL2 



Clock 
Gen. 








' [ 





Interrupt. 
Serial Port, 
Timer Blocks 



IDT 



Figure 23. Idle and Power Down Hardware 



MSB 



LSB 



SMOD 








GF1 


GFO 


PD 


IDL 



BIT 

PCON.7 

PCON.6 
PCON.5 
PCON.4 
PCON.3 
PCON.2 
PCON.1 
PCON.O 



SYMBOL FUNCTION 

SMOD Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Seri- 
al Port is used in modes 1 , 2, or 3. 
Reserved. 

— Reserved. 

— Reserved. 

GF1 General-purpose flag bit. 

GFO General-purpose flag bit. 

PD Power-Down bit. Setting this bit activates power-down operation. 

IDL Idle mode bit. Setting this bit activate idle mode operation. 



If 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XXX0000). 
In the NMOS devices, the PCON register only contains SMOD. The other four bits are implemented only in the CMOS 
devices. User software should never write 1s to unimplemented bits, since they may be used in future products. 



Figure 24. Power Control (PCON) Register 



1996 Aug 12 



2-37 



Phlips Semiconductors 



80C51 Family 



80C51 family hardware 



Power-Down Mode 

An instruction that sets PCON.1 causes that to be the last 
instruction executed before going into the Power Down mode. In the 
Power Down mode, the on-chip oscillator is stopped. With the clock 
frozen, all functions are stopped, the contents of the on-chip RAM 
and Special Function Registers are maintained. The port pins output 
the values held by their respective SFRs. The ALE and PSEN 
output are held low. 

The only exit from Power Down is a hardware reset. Reset redefines 
all the SFRs, but does not change the on-chip RAM. 

In the Power Down mode of operation, Vcc can be reduced to as 
low as 2 V. Care must be taken, however, to ensure that Vcc is not 
reduced before the Power Down mode is invoked, and that V C c is 
restored to its normal operating level, before the Power Down mode 
is terminated. The reset that terminates Power Down also frees the 
oscillator. The reset should not be activated before Vcc is restored 
to its normal operating level, and must be held active long enough to 
allow the oscillator to restart and stabilize (normally less than 10ms). 

ONCE Mode 

The ONCE ("on-circuit emulation") mode facilitates testing and 
debugging of systems using the device without the device having to 
be removed from the circuit. The ONCE mode is invoked by: 

1 . Pull ALE low while the device in in reset and PSEN is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in the ONCE mode, the Port pins go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the device is in this 
mode, an emulator or test CPU can be used to drive the circuit. 
Normal operation is restored after a normal reset is applied. 



The On-Chip Oscillators 

NMOS Version 

The on-chip oscillator circuitry for the NMOS members of the 80C51 
family is a single stage linear inverter (Figure 25), intended for use 
as a crystal-controlled, positive reactance oscillator (Figure 26). In 
this application the crystal is operated in its fundamental response 
mode as an inductive reactance in parallel resonance with 
Ditance external to the crystal. 



any frequency with good quality crystals. A ceramic resonator can 
be used in place of the crystal in cost-sensitive applications. When a 
ceramic resonator is used, C1 and C2 are normally selected to be of 
somewhat higher values, typically, 47pF. The manufacturer of the 
ceramic resonator should be consulted for recommendation on the 
values of these capacitors. 

To drive the NMOS parts with an external clock source, apply the 
external clock signal to XTAL2, and ground XTAL1 , as shown in 
Figure 27. A pullup resistor may be used (to increase noise margin), 
but is optional if V h of the driving gate exceeds the V| H minimum 
specification of XTAL. 

CMOS Versions 

The on-chip oscillator circuitry for the 80C51 , shown in Figure 28, 
consists of a single stage linear inverter intended for use as a 
crystal-controlled, positive reactance oscillator in the same manner 
as the NMOS parts. However, there are some important differences. 

One difference is that the 80C51 is able to turn off its oscillator 
under software control (by writing a 1 to the PD bit in PCON). 
Another difference is that, in the 80C51 , the internal clocking 
circuitry is driven by the signal at XTAL1 , whereas in the NMOS 
versions it is by the signal at XTAL2. 

The feedback resistor Rf in Figure 28 consists of paralleled n- and 
p-channel FETs controlled by the PD bit, such that Rf is opened 
when PD = 1. The diodes D1 and D2, which act as clamps to V cc 
and V S s, are parasitic to the R f FETs. The oscillator can be used 
with the same external components as the NMOS versions, as 
shown in Figure 29. Typically, C1 = C2 = 30pF when the feedback 
element is a quartz crystal, and C1 = C2 = 47pF when a ceramic 
resonator is used. 

When a crystal is used at frequencies above 25MHz, C1 and C2 
should be in the range of 20pF to 25pF. 

To drive the CMOS parts with an external clock source, apply the 
external clock signal to XTAL1, and leave XTAL2 float, as shown in 
Figure 30. 

The reason for this change from the way the NMOS part is driven 
can be seen by comparing Figures 26 and 28. In the NMOS devices 
the internal timing circuits are driven by the signal at XTAL2. In the 
CMOS devices the internal timing circuits are driven by the signal at 
XTAL1. 



The crystal specifications and capacitance values (C1 and C2 in 
Figure 26) are not critical. 30pF can be used in these positions at 



□- 



Vcc 



or 



Q4 



TO INTERNAL 
TIMING CIR- 
- CUITS 



Vss 



Figure 25. On-Chip Oscillator in the NMOS Version of the 8051 Family 



1996 Aug 12 



2-38 



Phlips Semiconductors 




80C51 Family 




80C51 family 


hardware descriDtion 



r 



Q1 



Q2 



TO INTERNAL 
TIMING CIRCUIT! 



03, CM 



8051 - 



| XTAL1 rj XTAL2 

id^= 



- 



-K — nr 



QUARTZ CRYSTAL OR 
CERAMIC RESONATOR 



SU00S52 



Figure 26. Using the NMOS On-Chip Oscillator 



Vcc 



EXTERNAL 

OSCILLATOR 

SIGNAL 



TTL GATE WITH 
TOTEM-POLE OUTPUT 



8051 

XTAL2 
XTAL1 

VSS 







Figure 27. Driving the NMOS 8051 Family Parts with an External Clock 







TO INTERNAL 
TIMING CIRCUITS 



IZh 



40on 

-vw- 



D1 A 



_, 01 



A 
V 



HIE 



Rf i — i 

VW 1 II XTAL2 




SU00554 



Figure 28. On-Chip Oscillator Circuitry in the CMOS Version of the 80C51 Family 



1996 Aug 12 



2-39 



Phlips Semiconductors 








80C51 Family 




80C51 


family hardware description 


i 1 



TO INTERNAL 
TIMING CIRCUITS 




Rf 



□ 



-k — it — )h 



QUARTZ CRYSTAL OR 
CERAMIC RESONATOR 







Figure 29. Using the CMOS On-Chip Oscillator 



i 



EXTERNAL 
OSCILLATOR ■ 
SIGNAL 







80C51 




NC 


XTAL2 






XTAL1 




vss 



Figure 30. Driving the CMOS Family Parts with an External Clock Source 

Internal Timing 

Figures 31 through 34 show when the various strobe and port 
signals are clocked internally. The figures do not show rise and fall 
times of the signals, nor do they show propagation delays between 
5 XTAL2 signal and events at other pins. 

; and fall times are dependent on the external loading that each 
l must drive. They are often taken to be something in the 
ghborhood of 10ns, measured between 0.8V and 2.0V. 

i delays are different for different pins. For a given pin 
ey vary with pin loading, temperature, Vpc, and 

s XTAL2 waveform is ' 
ay vary up to ±200%. 

The AC Timings section of the data sheets do not reference any 
timing to the XTAL2 waveform. Rather, they relate the critical edges 
of control and input signals to each other. The timings published in 
the data sheets include the effects of propagation delays under the 
specified test conditions. 



Me mory, P SEN is activated twice each machine cycle (except that 
two PSEN activa tions are skipped during accesses to external Data 
Memory). PSEN is not activated when the device is executing out of 
internal Program Memory. 

EAWpp: When EA is held high the CPU executes out of internal 
Program Memory (unless the Program Counter exceeds OFFFH in 
the 80C51 ). Holding EA low forces the CPU to execute out of 
external memory regardless of the Program Counter value. In the 
80C31 , EA must be externally wired low. In the EPROM devices, 
this pin also receives the programming supply voltage (Vpp) during 
EPROM programming. 

XTAL1 : Input to the inverting oscillator amplifier. 
XTAL2: Output from the inverting oscillator amplifier. 



80C51 Pin Descriptions 

ALE/PROG: Address Latch Enable output pulse for latching the low 
byte of the address during accesses to external memory. ALE is 
emitted at a constant rate of 1/6 of the oscillator frequency, for 
external timing or clocking purposes, even when there are no 
accesses to external memory. (However, one ALE pulse is skipped 
during each access to external Data Memory.) This pin is also the 
program pulse input (PROG) during EPROM programming. 

PSEN: Program Store Enable is the read strobe to external Program 
Memory. When the device is executing out of external Program 



Port 0: Port is an 8-bit open drain bidirectional port. As an open 
drain output port, it can sink eight LS TTL loads. Port pins that 
have 1s written to them float, and in that state will function as high 
impedance inputs. Port is also the multiplexed low-order address 
and data bus during accesses to external memory. In this application 
it uses strong internal pullups when emitting 1s. Port emits code 
bytes during program verification. In this application, external pullups 
are required. 

Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pullups. 
Port 1 pins that have 1s written to them are pulled high by the 
internal pullups, and in that state can be used as inputs. As inputs, 
port 1 pins that are externally being pulled low will source current 
because of the internal pullups. 



1996 Aug 12 



2-40 



Phlips Semiconductors 




80C51 Family 


80C51 family 


f hardware description 



Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. 
Port 2 emits the high-order address byte during accesses to external 
memory that use 1 6-bit addresses. In this application, it uses the 
ng internal pullups when emitting 1s. 

1 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. It 
ves the functions of various special features of the 80C51 
Family as follows: 



Port Pin Alternate Function 

P3.0 RxD (serial input port) 

P3.1 TxD (serial output port) 

P3.2 TNTO (external interrupt 0) 

P3.3 INT1 (external interrupt 1 ) 

P3.4 TO (timer external input) 

P3.5 T1 (timer 1 external input) 

P3.6 WR (external data memory write strobe) 

P3.7 RT5 (external data memory read strobe) 

V C c: Supply voltage 



V ss : Circuit ground potential 



| Stale 1 | State 2 I State 3 I State 4 I State 5 I State 6 j State 1 I State 2 I 
| PI | P2 I P1 I P2 | P1 I P2 | PI | P2 | PI | P2 | P1 I P2 | P1 I P2 | PI I P2 | 

JURRMMMMMfinJl 
n TL 


































j nata Ramplwl % 




1^ Data Sampled J 




Data Sampled 








PCL 








PCL 








PCL 










Out 
' ' 








Out 

1 1 








Out 
































PCH Out 


PCH Out 


PCH Out 



Figure 31. External Program Memory Fetches 



I State 4 I 
•2 | P1 I P2 | I 



e4 I 
P2 | 



a 5 I State 6 I State 1 I State 2 I State 3 
P1 | P2 | PI | P2 | PI | P2 | P1 I P2 | P1 | P2 | P1 | P2 



State 5 I 
P1 I P2 | 



juuuinjinjMuuuiJuuirL 
r~L 







Data Sampled ■»■ 










DPL or Rl 


Float 




Float 




PO: 


Out 


I 









PCL Out it Program 
Memory Is External 



PCH or P2 
SFR 



DPH or P2 SFR Out 



PCH or P2 
SFR 



Figure 32. 



Data Memory Read Cycle 



1996 Aug 12 



2-41 



Phlips Semiconductors 



)51 Family 



51 family hardware description 



State 4 I State 5 I State 6 I State 1 I State 2 I Stale 3 I State 4 I States I 
P1 I P2 | PI I P2 | P1 I P2 | P1 I P2 | PI I P2 I P1 I P2 | P1 I P2 | P1 I P2 | 




PCLOut if Program 
Memory Is External 



— 



DPL or Rl 
Out 




Data Out 


PCL 
Ou, 









P2: PCH or P2 



DPH ot P2 SFR Out 



Figure 33. External Data Memory Write Cycle 



Inputs Sampled: 



I State 4 I State 5 I State 6 I State 1 I State 2 I State 3 I State 4 I State 5 I 
| P1 I P2 | P1 I P2 | P1 I P2 | P1 I P2 | P1 I P2 | P1 | P2 | P1 | P2 | P1 | P2 | 

MiMMiurnjuiMm 



P2, P3, RST 



P0.P1 
P2, P3, RST 



Serial Port 
Shift Clock 
(Mode 0): 



Old Data 




New Data 






















u 


* RXD Pin Sampled 


RXD Sampled — »| 



St/00560 



Figure 34. Port Operation 



1996 Aug 12 



2-42 



Philips Semiconductors 



80C51 family programmer's guide 
and instruction set 



PROGRAMMER'S GUIDE AND INSTRUCTION SET 
Memory Organization 
Program I 



he 80C51 has separate address spaces for program and data 
memory. The Program memory can be up to 64k bytes long. The 
lower 4k can reside on-chip. Figure 1 shows a map of the 80C51 
program memory. 

The 80C51 can address up to 64k bytes of data memory to trie chip. 
The MOVX instruction is used to access the external data memory. 

The 80C51 has 128 bytes of on-chip RAM, plus a number of Special 
l Registers (SFRs). The lower 128 bytes of RAM can be 

r by direct addressing (MOV data addr) or by indirect 
dressing (MOV @Ri). Figure 2 shows the Data Memory 

lization. 

Direct and Indirect Address Area 

The 1 28 bytes of RAM which can be accessed by both direct and 
indirect addressing can be divided into three segments as listed 
below and shown in Figure 3. 

1 . Register Banks 0-3: Locations through 1 FH (32 bytes). The 
device after reset defaults to register bank 0. To use the other 
register banks, the user must select them in software. Each 



register bank contains eight 1-byte registers through 7. Reset 
initializes the stack pointer to location 07H, and it is incremented 
once to start from location 08H, which is the first register (R0) of 
the second register bank. Thus, in order to use more than one 
register bank, the SP should be initialized to a different location 
of the RAM where it is not used for data storage (i.e., the higher 
part of the RAM). 

Bit Addressable Area: 1 6 bytes have been assigned for this 
segment, 20H-2FH. Each one of the 128 bits of this segment can 
be directly addressed (0-7FH). The bits can be referred to in two 
ways, both of which are acceptable by most assemblers. One 
way is to refer to their address (i.e., 0-7FH). The other way is 
with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be 
referred to as bits 20.0-20.7, and bits 8-FH are the same as 
21.0-21.7, and so on. Each of the 1 6 bytes in this segment can 
also be addressed as a byte. 



Scratch Pad Area: 30H through 7FH are available to the user as 
data RAM. However, if the stack pointer has been initialized to 
this area, enough bytes should be left aside to prevent SP data 
destruction. 



Figure 2 shows 



segments of the on-chip RAM. 



60k 
BYTES 
EXTERNAL 



_ 



y — or 



AND 



4k BYTES 
INTERNAL 



— 



64k 



BYTES 
EXTERNAL 



Figure 1. 80C51 Program Memory 



March 1995 



2-43 



Philips Semiconductors 



80C51 Family 







80C51 family programmer's guide 

and instruction set 






INTERNAL 








OFFF 






FF 


SFRs 

DIRECT ADDRESSING 
ONLY 






64k 
BYTES 
EXTERNAL 




BO 












7F 


DRIECT AND INDIRECT 
ADDRESSING 




> AND ► 






00 






0000 














SU00568 



Figure 2. 80C51 Data Memory 







7F 
77 



57 
4F 



SCRATCH 
PAD 
AREA 



2F BIT 

ADDRESSABLE 
27 SEGMENT 



IF 
17 
OF 
07 



Figure 3. 128 Bytes of RAM Direct and Indirect Addressable 



March 1995 



2-44 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



Table 1 . 80C51 Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRESS, 




., OR ALTERNATIVE PORT FUNCT 


ION 
LSB 


RESET VALUE 




Mod 
















ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


00H 


B* 


B register 


FOH 


F7 


F6 


F5 


F4 


F3 


F2 


F1 


FO 


00H 


DPTR 


Data pointer (2 by- 
tes) 






















DPH 


Data pointer high 


83H 


















00H 


DPL 


Data pointer low 


82H 


















00H 








AF 


AE 


AD 


AC 


AB 
— 


AA 


A9 


A8 




IE- 


Interrupt enable 


A8H 


EA 




- 


ES 




EX1 


I 


EXO 


OxOOOOOOB 








BF 


BE 


BD 


BC 


BB 


BA 


B9 


B8 




IP* 


Interrupt pnonty 


B8H 








PS 


PT1 


PX1 


PTO 


PXO 


xxOOOOOOB 








87 


86 


85 


84 


83 


82 


81 


80 




PO* 


Port 


80H 


AD7 


AD6 


AD5 


AD4 


AD3 


AD2 


I — 

| AD1 


ADO 


FFH 








97 


96 


95 


94 
- 


93 


92 


91 


90 




P1* 


Port 1 


90H 






- 






I 

- 


| T2EX 


T2 


FFH 








A7 


A6 


AC 

AO 


A4 


A3 


A2 


A1 


An 
AU 




P2* 


Port 2 


AOH 


A15 


A14 


A13 


r~777 — 

A12 


... 
A11 


A10 


T — — I 

| A9 


A8 


FFH 








B7 


B6 


OK 
DO 


B4 


B3 


B2 


B1 


on 




P3* 


Port 3 


BOH 


RD 


WR 


T1 


TO 


INTT 


INTO" 


TxD 


Rxd 


FFH 


PCON^ 


Power control 


87H 


SMOD 


~ 






GF1 


GFO 


PD 


I DL 


OxxxxxxxB 








D7 


D6 


D5 


: 


D3 


D2 


D1 


DO 




PSW* 


Program status word 


DOH 


CY 


AC 


FO 


RS1 


RSO 


OV 


" 


P 


00H 


SBUF 


Serial data buffer 


99H 


















xxxxxxxxB 








9F 


9E 


on 


9C 


9B 


9A 


99 


98 




SCON* 


Serial controller 




SMO 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


00H 


SP 


Stack pointer 


81 H 


















07H 








8F 


8E 


8D 


8C 


8B 


8A 


89 


88 




TCON* 


Timer control 


88H 


TF1 


TR1 


TFO 


TRO 


« 


m 


| IE0 


ITO 




THO 


Timer high 


8CH 


















00H 


TH1 


Timer high 1 


8DH 


















00H 


TLO 


Timer low 


8AH 


















00H 


TL1 


Timer low 1 


8BH 


















OOH 


TMOD 


Timer mode 


89H 


GATE 


C/T 


Ml 


MO 


GATE 


C/T 


| M1 


MO 


00H 



NOTES: 

* Bit addressable 

1. Bits GF1, GFO, PD, and IDLof the PCON register are not implemented on the NMOS 8051/8031. 



March 1995 



9-4 5 



Philips Semiconductors 



30C51 Family 



80C51 family programmer's guide 
and instruction set 











8 BYTES 








F8 

FO 
E8 


















FF 






B 
















F7 






















EF 






EO 


ACC 
















E7 






D8 


















DF 






DO 


PSW 
















D7 






C8 


















CF 






CO 


















C7 






B8 


IP 
















BF 






BO 


P3 
















B7 






A6 


IE 
















AF 






AO 


P2 
















A7 






98 


SCON 


SBUF 














9F 






90 


PI 
















97 






88 


TCON 


TMOD 


TLO 


TL1 


THO 


TH1 






8F 






80 


PO 


SP 


DPL 


DPH 








PCON 


87 








BIT ADDRESSABLE 


SU00570 



Figure 4. SFR Memory Map 



March 1995 



2-46 



Philips Semiconductors 



anrm Pamih, 80C51 fami| y Programmer's guide 

80C51 Family and instruction set 



Those SFRs that have their bits i 
provided for quick reference. For r 



I for various functions are listed in this section. A brief description of each bit is 
on refer to the Architecture Chapter of this book. 



PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE. 



CY 


AC 


CY 


PSW.7 


AC 


PSW.6 


FO 


PSW.5 


RS1 


PSW.4 


RSO 


PSW.3 


OV 


PSW.2 




PSW.1 


P 


PSW.O 



FO 



RS1 



RSO 



OV 



Carry Flag. 
Auxiliary Carry Flag. 

Flag available to the user for general purpose. 
Register Bank selector bit 1 (SEE NOTE 1). 
Register Bank selector bit (SEE NOTE 1). 
Overflow Flag. 



Usable as a general purpose flag. 

Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of '1 ' bus in 
the accumulator. 

NOTE: 

1. The value presented by RSO and RS1 selects the corresponding register bank. 



RS1 


RSO 


REGISTER BANK 


ADDRESS 











OOH-07H 





1 


1 


08H-0FH 


1 





2 


10H-17H 


1 


1 


3 


18H-1FH 



PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE. 



SMOD 






- 


GF1 


GFO 


PD 


IDL 



Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1 . the baud rate is doubled when the Serial 
i modes 1,2, or 3. 




SMOD 

Port is used in 

Not implemented, reserved for future use.' 
- Not implemented reserved for future use.* 

Not implemented reserved for future use.* 
GF1 General purpose flag bit. 

GFO General purpose flag bit. 

PD Power Down Bit. Setting this bit activates Power Down operation in the 80C51 . (Available only in CMOS.) 

IDL Idle mode bit. Setting this bit activates Idle Mode operation in the 80C51 . (Available only in CMOS.) 

If 1s are written to PD and IDL at the same time, PD takes precedence. 

* User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new features. 



March 1995 



2-47 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



INTERRUPTS: 

To use any of the interrupts in the 80C51 Family, the following thrr~ 

1. Set the EA (enable all) bit in the IE register to 1. 

2. Set the corresponding individual interrupt enable bit in the IE register to 

3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table 



1 



INTERRUPT SOURCE 


VECTOR ADDRESS 


IE0 


0003H 


TFO 


000BH 


IE1 


001 3H 






TF1 


001 BH 






RI&TI 


0023H 







In addition, for external interrupts, pins INTO and INT1 (P3.2 and P3.3) must be set to 1 , and depending on whether the 
interrupt is to be level or transition activated, bits ITO or IT1 in the TCON register may need to be set to 1 . 

ITx = level activated 

ITx = 1 transition activated 



IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE 

If the bit is 0, the corresponding interrupt is disabled 



the bit is 1, the corresponding interrupt is enabled. 



EA 






ES 


ET1 


EX1 


ET0 


EX0 



EA 


IE.7 




IE.6 




IE.5 


ES 


IE.4 


ET1 


IE.3 


EX1 


IE.2 


ETO 


IE.1 


EXO 


IE.0 



Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1 , each interrupt source is 
individually enabled or disabled by setting or clearing its enable bit. 

Not implemented, reserved for future use.* 

Not implemented, reserved for future use.* 

Enable or disable the serial port interrupt. 

Enable or disable the Timer 1 overflow interrupt. 

Enable or disable External Interrupt 1 . 

Enable or disable the Timer overflow interrupt. 

Enable or disable External Interrupt 0. 



User software should not write 1s to reserved bits. These bits may be used in future 80C51 products to invoke new features. 



March 1995 



2-48 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS: 

In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set t 
Remember that while an interrupt service is in progress, it cannot be interrupted by a lower or s 

PRIORITY WITHIN LEVEL: 

Priority within level is only to resolve simultaneous requests of the same priority level. 

From high to low, interrupt sources are listed below: 

IEO 
TFO 
IE1 
TF1 
Rl orTI 



1. 

level interrupt. 



IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE. 

If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a higher priority. 









PS 


PT1 


PX1 


PTO 


PXO 



IP.7 Not implemented, reserved for future use.* 

IP.6 Not implemented, reserved for future use.* 

- IP.5 Not implemented, reserved for future use.* 

PS IP.4 Defines the Serial Port interrupt priority level. 

PT1 IP.3 Defines the Timer 1 interrupt priority level. 

PX1 IP.2 Defines External Interrupt 1 priority level. 

PTO IP. 1 Defines the Timer interrupt priority level. 

PXO IP.O Defines the External Interrupt priority level. 

* User software should not write 1 s to reserved bits. These bits may be used in future 80C51 products to invoke new features. 



March 1995 



2-49 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



TCON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE. 



TF1 


TR1 


TFO 


TRO 


IE1 


IT1 


IEO 


ITO 



TF1 TCON.7 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as 

processor vectors to the interrupt service routine. 

TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1 ON/OFF. 

TFO TCON.5 Timer overflow flag. Set by hardware when the Timer/Counter overflows. Cleared by hardware as 

processor vectors to the service routine. 

TRO TCON.4 Timer run control bit. Set/cleared by software to turn Timer/Counter ON/OFF. 

IE1 TCON. 3 External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is detected. Cleared by 

hardware when interrupt is processed. 

IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered External 

Interrupt. 

IEO TCON.1 External Interrupt edge flag. Set by hardware when External Interrupt edge detected. Cleared by 

hardware when interrupt is processed. 

ITO TCON.O Interrupt type control bit. Set/cleared by software to specify falling edge/low level triggered External 

Interrupt. 



TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT ADDRES 



GATE 


C/T 


M1 


MO 


GATE 


C/T 


M1 


MO 



















Timer 1 



Timer 



GATE 

C/T 

M1 
MO 

NOTE 1 : 



When TRx (in TCON) is set and GATE = 1 , TIMER/COUNTERx will run only while INTx pin is high (hardware control). 
When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software control). 

Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation 
(input from Tx input pin). 

Mode selector bit. (NOTE 1) 

Mode selector bit. (NOTE 1) 



111 


MO 


Op 


erating Mode 











13-bit Timer (8048 compatible) 





1 


1 


1 6-bit Timer/Counter 


1 





2 


8-bit Auto-Reload Timer/Counter 


1 


1 


3 


(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standart Timer 
control bits. THO is an8-bit Timer and is controlled by Timer 1 control bits. 


1 


1 


3 


(Timer 1 ) Timer/Counter 1 stopped. 



March 1995 2-50 



Philips Semiconductors 



TIMER SET-UP 

Tables 2 through 5 give some values for TMOD which can be used to set up Timer in different modes. 

It is assumed that only one timer is being used at a time. If it is desired to run Timers and 1 simultaneously, in any mode, the 
value in TMOD for Timer must be ORed with the value shown for Timer 1 (Tables 5 and 6). 

For example, if it is desired to run Timer in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER, then the value 
that must be loaded into TMOD is 69H (09H from Table 2 ORed with 60H from Table 5). 

Moreover, it is assumed that the user, at this point, is not ready to turn the timers on and will do that at a different point in the 
program by setting bit TRx (in TCON) to 1 . 



TIMER/COUNTER 
Table 2. As a Timer: 



MODE 


TIMER 
FUNCTION 


TMOD 


INTERNAL 
CONTROL 
(NOTE 1) 


EXTERNAL 
CONTROL 
(NOTE 2) 





13-bit Timer 


00H 


08H 


1 


16-bit Timer 


01 H 


09H 





8-bit Auto-Reload 


02H 


OAH 


3 


Two 8-bit Timers 


03H 


OBH 



Table 3. As a Counter: 



MODE 


FUNCTION 


TMOD 


INTERNAL 
CONTROL 
(NOTE 1) 


EXTERNAL 
CONTROL 
(NOTE 2) 





13-bit Timer 


04H 


OCH 


1 


16-bit Timer 


05H 


ODH 


2 


8-bit Auto-Reload 


06H 


OEH 


3 


One 8-bit Counter 


07H 


OFH 



NOTES: 

1 . The timer is turned ON/OFF by setting/clearing bit TRO in the software. 

2. The Timer is turned ON/OFF by the 1 -to-0 transition on INTO (P3.2) when TRO = 1 (hardware control). 



March 1995 



Semiconductors 



Philips 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



TIMER/COUNTER 1 
Table 4. As a Timer: 



MODE 


TIMER 1 
FUNCTION 


TMOD 


INTERNAL 
CONTROL 
(NOTE 1) 


EXTERNAL 
CONTROL 
(NOTE 2) 





13-bit Timer 


00H 


80H 


1 


16-bit Timer 


10H 


90H 


2 


8-bit Auto-Reload 


20H 


AOH 


3 


Does not run 


30H 


BOH 


Table 5. As a Counter: 


MODE 


COUNTER 1 
FUNCTION 


TMOD 


INTERNAL 
CONTROL 
(NOTE 1) 


EXTERNAL 
CONTROL 
(NOTE 2) 





13-bit Timer 


40H 


COH 




16-bit Timer 


50H 


DOH 




8-bit Auto-Reload 


60H 


EOH 


3 


Not available 







NOTES: 

1 . The timer is turned ON/OFF by setting/clearing bit TR1 in the software. 

2. The Timer is turned ON/OFF by the 1-to-0 transition on INTT (P3.2) when T 



March 1995 



2-52 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



SCON: ! 
|_ SMO 



SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE. 

SM2~~[~REN | TB8 



SM1 



RB8 



Tl 



T 



Rl 



SMO SCON.7 Serial Port mode specifier. (NOTE1) 



Serial Port mode specifier. (NOTE 1) 
SM1 SCON.6 Serial Port mode specifier. (NOTE 1) 

SM2 SCON. 5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, if SM2 is set to 1 then 

Rl will not be activated if the received 9th data bit (RB8) is 0. In mode 1 , if SM2 = 1 then Rl will not be 
activated if a valid stop bit was not received. In mode 0, SM2 should be 0. (See Table 6.) 

REN SCON.4 Set/Cleared by software to Enable/Disable reception. 

TB8 SCON.3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software. 

RB8 SCON.2 In modes 2 & 3, is the 9th data bit that was received. In mode 1 , if SM2 = 0, RB8 is the stop bit that was 

received. In mode 0, RB8 is not used. 

Tl SCON. 1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the 

stop bit in the other modes. Must be cleared by software. 

Rl SCON.O Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the 

stop bit time in the other modes (except see SM2). Must be cleared by software. 

NOTE1- 



SMO 


SM1 


Mode 


Description 


Baud Rate 













Shift Register 


F0SC/12 







1 


1 


8-bit UART 


Variable 


1 





2 


9-bit UART 


Fosc/64 or Fosc/32 




1 


1 


3 


9-bit UART 


Variable 





SERIAL PORT SET-UP: 
Table 6. 



MODE 


SCON 


SM2 VARIATION 



1 

2 
3 


10H 
50H 
90H 
DOH 




Single Processor 
Environment 
(SM2 = 0) 



1 
2 
3 


NA 
70H 
BOH 
FOH 




Multiprocessor 
Environment 
(SM2 = 1) 



GENERATING BAUD RATES 
Serial Port in Mode 0: 

Mode has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of the 
Timer/Counters need to be set up. Only the SCON register needs to be defined. 

Osc Freq 



Baud Rate 



12 



Serial Port in Model: 

Mode 1 has a variable baud rate. The baud rate is generated by Timer 1 . 



March 1995 



Philips Semiconductors 



80C51 Family 



programmer's guide 
and instruction set 



USING TIMER/COUNTER 1 TO GENERATE BAUD RATES: 

For this purpose, Timer 1 is used in mode 2 (Auto- Reload). Refer to Timer Setup section of this chapter. 

K x Osc Freq 
32 x 12 x [256 - (TH1)] 



Baud Rate = 



If SMOD = 0, thenK=1. 

If SMOD = 1 , then K = 2 (SMOD is in the PCON register). 

Most of the time the user knows the baud rate and needs to know the reload value for TH1 . 

thi = ocfi _ K x Osc Freq 
384 x baud rate 



TH1 must be an integer value. Rounding off TH1 to the nearest integer may not produce the desired baud rate. In this case, the 
user may have to choose another crystal frequency. 

Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register (i.e., ORL 
PCON,#80H). The address of PCON is 87H. 



SERIAL PORT IN MODE 2: 

The baud rate is fixed in this mode and is 1/32 or 1/64 of the oscillator frequency, depending on the value of the SMOD bit in 
the PCON register. 

In this mode none of the Timers are used and the clock comes from the internal phase 2 clock. 
SMOD = 1 , Baud Rate = 1/32 Osc Freq. 
SMOD = 0, Baud Rate = 1/64 Osc Freq. 

To set the SMOD bit: ORL PCON,#80H. The address of PCON is 87H. 



SERIAL PORT IN MODE 3: 

The baud rate in mode 3 is variable and sets up exactly the same as in mode 1 . 






























March 1995 



Philips Semiconductors 



80C51 family programmer's guide 
and instruction set 



80C51 Family 



80C51 FAMILY INSTRUCTION SET 



Table 7. 80C51 Instruction Set Summary 







— , 



Interrupt Response Time: Refer to Hardware Description Chapter. 
Instructions that Affect Flag Settings* 1 ) 



Instruction 




Flag 




Instruction 






C 


ov 


AC 




C 


ADD 


X 


X 


X 


CLRC 





ADDC 


X 


X 


X 


CPLC 


X 


SUBB 


X 


X 


X 


ANL C.bit 


X 


MUL 





X 




ANL C,/bit 


X 


DIV 





X 




ORL C.bit 


X 


DA 


X 






ORL C/bit 


X 


RRC 


X 






MOV C.bit 


X 


RLC 


X 






CJNE 


X 


SETBC 


1 











Flag 

OV 



SETB C 1 

0>Note that operations on SFR byte address 208 or bit addresses 209-215 (i.e., the PSW or bits in the PSW) 



will also affect flag settings. 



Notes on instruction set and addressing modes: 

Rn Register R7-R0 of the currently selected Register Bank. 

direct 8-bit internal data location's address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, 

control register, status register, etc. (128-255)]. 

@Ri 8-bit internal data RAM location (0-255) addressed indirectly through register R1 or R0. 

#data 8-bit constant included in the instruction. 

#data 1 6 1 6-bit constant included in the instruction 

addr 16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64k-byte Program 
Memory address space. 

addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2k-byte page of 
program memory as the first byte of the following instruction. 

rel Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 

bytes relative to first byte of the following instruction. 

bit Direct Addressed bit in Internal Data RAM or Special Function Register. 



MNEMONIC 



DESCRIPTION 



BYTE 



OSCILLATOR 
PERIOD 



ARITHMETIC OPERATIONS 



ADD 


A,Rn 


Add register to Accumulator 


1 


12 


ADD 


A.direct 


Add direct byte to Accumulator 


2 


12 


ADD 


A,@Ri 


Add indirect RAM to Accumulator 


1 


12 


ADD 


A,#data 


Add immediate data to Accumulator 


2 


12 


ADDC 


A.Rn 


Add register to Accumulator with carry 


1 


12 


ADDC 


A.direct 


Add direct byte to Accumulator with carry 


2 


12 


ADDC 


A,@Ri 


Add indirect RAM to Accumulator with carry 


1 


12 


ADDC 


A,#data 


Add immediate data to Ac with carry 


2 


12 


SUBB 


A,Rn 


Subtract Register from Acc with borrow 


1 


12 


SUBB 


A.direct 


Subtract direct byte from Acc with borrow 


2 


12 


SUBB 


A,@Ri 


Subtract indirect RAM from Acc with borrow 


1 


12 


SUBB 


A,#data 


Subtract immediate data from Acc with borrow 


2 


12 


INC 


A 


Increment Accumulator 


1 


12 


INC 


Rn 


Increment register 


1 


12 



All mnemonics copyrighted © Intel Corporation 1 980 



March 1995 



2-55 



Philips Semiconductors 



80C51 Family 


80C 


51 famih 


/ programmer's guide 
and instruction set 


Table 7. 


80C51 Instruction 


Set Summary (Continued) 






MNEMONIC 


DESCRIPTION 


nvrc OSCILLATOR 
BYTE PERIOD 


ARITHMETIC OPERATIONS (Continued) 

INC direct Increment direct byte 2 12 


INC 


@Ri 


Increment indirect RAM 


1 


12 


DEC 
DEC 


A 
Rn 


Decrement Accumulator 
Decrement negister 


1 
1 


12 
12 


DEC 


direct 


Decrement direct byte 


2 
1 


12 


DEC 


SRI 


Decrement indirect RAM 


12 


INC 


DPTR 


Increment Data Pointer 




24 


MUL 


AB 


Multiply A and B 


1 


48 


DIV 


AB 


Divide A by B 


1 


48 


DA A 
LOGICAL OPERATIONS 


Decimal Adjust Accumulator 1 


12 


ANL 


A,Rn 


AND Register to Accumulator 


1 


12 


ANL 


A.direct 


AND direct byte to Accumulator 


2 


12 


ANL 


A,@Ri 


AND indirect RAM to Accumulator 


1 


12 


ANL 


A,#data 


AND immediate data to Accumulator 


2 


12 


ANL 
ANL 


direct.A 
direct,#data 


AND Accumulator to direct byte 
AND immediate data to direct byte 


2 
3 


12 
24 


ORL 


A,Rn 


OR register to Accumulator 


1 


12 


ORL 


A.direct 


OR direct byte to Accumulator 


2 12 


ORL 


A,@Ri 


OR indirect RAM to Accumulator 


1 


12 


ORL 


A,#data 


OR immediate data to Accumulator 


2 


12 


ORL 


direct.A 


OR Accumulator to direct byte 


2 


12 


ORL 
XRL 


direct,#data 
A.Rn 


OR immediate data to direct byte 


3 


24 


Exclusive-OR register to Accumulator 


1 


12 


XRL 


A.direct 


Exclusive-OR direct byte to Accumulator 


2 


12 


XRL 


A,@Ri 


Exclusive-OR indirect RAM to Accumulator 


1 


12 


XRL 


A,#data 


Exclusive-OR immediate data to Accumulator 


2 


12 


XRL 


direct.A 


Exclusive-OR Accumulator to direct byte 


2 


12 


XRL 


direct,#data 


Exclusive-OR immediate data to direct byte 


3 


24 


CLR 


A 


Clear Accumulator 


1 


12 


CPL 


A 


Complement Accumulator 


1 


12 


RL 


A 


Rotate Accumulator left 


1 


12 


RLC 


A 


Rotate Accumulator left through the carry 


1 


12 


RR 


A 


Rotate Accumulator right 


1 


12 


RRC 


A 


Rotate Accumulator right through the carry 


1 


12 


SWAP 


A 


Swap nibbles within the Accumulator 


1 


12 


DATA TRANSFER 








MOV 


A.Rn 


Move register to Accumulator 


1 


12 


MOV 


A.direct 


Move direct byte to Accumulator 


2 


12 


MOV 


A,@Ri 


Move indirect RAM to Accumulator 


1 


12 






All mnemonics 


copyrighted © Intel Corporation 1980 



March 1995 



Philips Semiconductors 



80C51 Family 




programmer's guide 
and instruction set 



Table 7. 80C51 Instruction Set Summary (Continued) 





MNEMONIC 


DESCRIPTION 


BYTE 


UoUlLLAlUn 
PERIOD 


DATA TRANSFER (Continued) 






MOV 


A,#data 


Move immediate data to Accumulator 


2 


12 


MOV 


Rn,A 


Move Accumulator to register 


1 


12 


MOV 


Rn.direct 


Move direct byte to register 


2 


24 


MOV 


RN,#data 


Move immediate data to register 


2 


12 


MOV 


direct.A 


Move Accumulator to direct byte 


2 


12 


MOV 


direct, Rn 


Move register to direct byte 


2 


24 


MOV 


directdirect 


Move direct byte to direct 


3 


24 


MOV 


direct, @Ri 


Move indirect RAM to direct byte 


2 


24 


MOV 


direct,#data 


Move immediate data to direct byte 


3 


24 


MOV 


@Ri,A 


Move Accumulator to indirect RAM 


1 


12 


MOV 


@Ri,direct 


Move direct byte to indirect RAM 


2 


24 


MOV 


@Ri,#data 


Move immediate data to indirect RAM 


2 


12 


MOV 


DPTR,#data16 


Load Data Pointer with a 1 6-bit constant 


3 


24 


MOVC 


A,@A+DPTR 


Move Code byte relative to DPTR to Acc 


1 


24 


MOVC 


A,®A+PC 


Move Code byte relative to PC to Acc 


1 


24 


MOVX 


A,@Ri 


Move external RAM (8-bit addr) to Acc 


1 


24 


MOVX 


A,@DPTR 


Move external RAM (16-bit addr) to Acc 


1 


24 


MOVX 


A,@Ri,A 


Move Acc to external RAM (8-bit addr) 


1 


24 


MOVX 


©DPTR.A 


Move Acc t0 external RAM (16-bit addr) 


1 


24 


PUSH 


direct 


Push direct byte onto stack 


2 


24 


POP 


direct 


Pop direct byte from stack 


2 


24 


XCH 


A.Rn 


Exchange register with Accumulator 


1 


12 


XCH 


A.direct 


Exchange direct byte with Accumulator 


2 


12 


XCH 


A,@Ri 


Exchange indirect RAM with Accumulator 


1 


12 


XCHD 


A,@Ri 


Exchange low-order digit indirect RAM with Acc 


1 


12 


BOOLEAN VARIABLE MANIPULATION 








CLR 


C 


Clear carry 


1 


12 


CLR 


bit 


Clear direct bit 


2 


12 


SETB 


C 


Set carry 


1 


12 


SETB 


bit 


Set direct bit 


2 


12 


CPL 


C 


Complement carry 


1 


12 


CPL 


bit 


Complement direct bit 


2 


12 


ANL 


Cbit 


AND direct bit to carry 


2 


24 


ANL 


C,/bit 


AND complement of direct bit to carry 


2 


24 


ORL 


Cbit 


OR direct bit to carry 


2 


24 


ORL 


C,/bit 


OR complement of direct bit to carry 


2 


24 


MOV 


Cbit 


Move direct bit to carry 


2 


12 


MOV 


bit.C 


Move carry to direct bit 


2 


24 


JC 


rel 


Jump if carry is set 


2 


24 


JNC 


rel 


Jump if carry not set 


2 


24 



All mnemonics copyrighted © Intel Corporation 1 980 



March 1995 



2-57 



Philips Semiconductors 



80C51 family programmer's guide 
' and instruction set 



Table 7. 80C51 Instruction Set Summary (Continued) 





MNEMONIC 


DESCRIPTION 


BYTE 


OSCILLATOR 
PERIOD 




BOOLEAN VARIABLE MANIPULATION (Continued) 








JB 


rel 


Jump if direct bit is set 


3 


24 




JNB 


rel 


Jump if direct bit is not set 


3 


24 




JBC 


bit, rel 


Jump if direct bit is set and clear bit 


3 


24 




PROGRAM BRANCHING 










ACALL 


addrn 


Absolute subroutine call 


2 


24 




LCALL 


addr16 


Long subroutine call 


3 


24 




RET 




Return from subroutine 


1 


24 




RETI 




Return from interrupt 


1 


24 




AJMP 


addr11 


Absolute jump 


2 


24 




LJMP 


addr16 


Long jump 


3 


24 




SJMP 


rel 


Short jump (relative addr) 


2 


24 




JMP 


©A+DPTR 


Jump indirect relative to the DPTR 


1 


24 




JZ 


rel 


Jump if Accumulator is zero 


2 


24 




JNZ 


rel 


Jump if Accumulator is not zero 


2 


24 




CJNE 


A.direct.rel 


Compare direct byte to A C c and jump if not equal 


3 


24 




CJNE 


A,#data,rel 


Compare immediate to A cc and jump if not equal 


3 


24 




CJNE 


RN,#data,rel 


Compare immediate to register and jump if not 
equal 


3 


24 




CJNE 


@Ri,#data,rel 


Compare immediate to indirect and jump if not 
equal 


3 


24 


DJNZ 


Rn.rel 


Decrement register and jump if not zero 


2 


24 




DJNZ 


direct.rel 


Decrement direct byte and jump if not zero 


3 


24 




NOP 




No operation 


1 


12 





All mnemonics copyrighted © Intel Corporation 1981 



March 1995 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



INSTRUCTION DEFINITIONS 



ACALL addr11 



Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Absolute Call 

ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments 
the PC twice to obtain the address of the following instruction, then pushes the 1 6-bit result onto the 
stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained 
by successively concatenating the five high-order bits of the incremented PC, opcode bits 7-5, and the 
second byte of the instruction. The subroutine called must therefore start within the same 2k block of the 
program memory as the first byte of the instruction following ACALL. No flags are affected. 

Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After executing the 
instruction, 



ACALL SUBRTN 

at location 0123H, SP will contain 09H, internal RAM locations 08H and 
respectively, and the PC will contain 0345H. 

2 



will contain 25H and 01 H, 



a10a9 a8 1 



| 1 a7 a6 a5 a4 | a3 a2 a1 aO | 



ACALL 

(PC) <- (PC) + 2 
(SP) «- (SP) + 1 
(SP) <- (PC™) 
(SP) «- (SP) + 1 
(SP) <- (PC 1M ) 
( p Cio-o) <- page address 



March 1995 



2-59 



Philips Semiconductors 



80C51 Famil 80C51 family programmer's guide 

" and instruction set 



ADD A,<src-byte> 
Function: Add 

Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry 
and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared 
otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. 

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise OV 
is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two 
positive operands, or a positive sum from two negative operands. 

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. 
Example: The Accumulator holds 0C3H (11000011B) and register holds OAAH (10101010B). The instruction, 
ADD A,R0 

will leave 6DH (01 1 01 1 01 B) in the Accumulator with the AC flag cleared and both the Carry flag and OV 
set to 1 . 



ADD A,Rn 



Cycles: 1 



10 



Encoding: 

Operation: ADD 

(A)<-(A) + (R n ) 

ADD A,direct 

Bytes: 2 
Cycles: 1 



1 r r r 



10 



Encoding: 

Operation: ADD 

(A) *- (A) + (direct) 

ADD A,@Ri 

Bytes: 1 
Cycles: 1 



10 



Encoding: 

Operation: ADD 

(A) <- (A) + ((R,)) 



10 1 



1 1 i 



direct address 



ADD A,#data 

Bytes: 2 
Cycles: 1 



10 



Encoding: 

Operation: ADD 

(A) «- (A) + #data 



10 



immediate data 



March 1995 



2-60 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



ADDC A,<src-byte> 



Function: Add with Carry 



Description: 



Example: 



ADDC A,Rn 
Bytes: 



ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, 
leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a 
carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag 
indicates an overflow occurred. 

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; 
otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the 
sum of two positive operands, or a positive sum from two negative operands. 

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. 

The Accumulator holds 0C3H (11 00001 1B) and register holds OAAH (10101 01 OB) with the carry flag set. 
The instruction, 

ADDC A,R0 

will leave 6EH (01 101 11 0B) in the Accumulator with 



Carry flag and OV set to1. 



Cycles: 1 



Encoding: 
Operation: 

ADDC A.direct 



11 



1 r r r 



ADDC 

(A) «- (A) + (C) + (R n ) 



Cycles: 1 



110 10 1 



Encoding: 

Operation: ADDC 

(A) «- (A) + (C) + (direct) 



direct address 



ADDC A,@Ri 

Bytes: 1 
Cycles: 1 



110 111 



Encoding: 

Operation: ADDC 

(A) <- (A) + (C) + ((Ri)) 

ADDC A,#data 

Bytes: 2 
Cycles: 1 



11 



Encoding: 

Operation: ADDC 

(A) <- (A) + (C) + #data 



10 



immediate data 



March 1995 



2-61 



Philips Semiconductors 



80C51 Family 




y programmer's guide 
and instruction set 







AJMP addr11 



Function: Absolute Jump 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating 
the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and the second byte 
of the instruction. The destination must therefore be within the same 2k block of program memory as the 
first byte of the instruction following AJMP. 

The label "JMPADR" is at program memory location 0123H. The instruction, 
AJMP JMPADR 



is at location 0345H and will l< 

2 
2 



a10 a9 a8 



1 



a7 a6 a5 a4 a3 a2 a1 aO 



AJMP 

(PC) «- (PC) + 2 
(PC 10 -o) <— page address 



ANL <dest-byte>,<src-byte> 



Function: Logical-AND for byte variables 

Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in 
the destination variable. No flags are affected. 

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the 
source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct 
address, the source can be the Accumulator or immediate data. 

Note: When this instruction is used to modify an output port, the value used as the original port data will 
be read from the output data latch, not the input pins. 

Example: If the Accumulator holds 0C3H (11 000011 B) and register holds 55H (01010101 B) then the instruction, 
ANL A,R0 

will leave 41 H (01000001 B) in the Accumulator. 

When the destination is a directly addressed byte, this instruction will clear combinations of bits in any 
RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would 
either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The 
instruction, 

ANL P1,#01110011B 
will clear bits 7, 3, and 2 of output port 1. 



March 1995 



2-62 



Philips Semiconductors 



RfiPRi Family 80051 fami| y programmer's guide 

80U51 hamily and jnstructjon set 



ANL A,Rn 

Bytes: 1 
Cycles: 1 



|~0 i 0~\ Tl r r r 
I 1 1 



Operation: ANL 

(A) «- (A) A (R n ) 

ANL A,direct 

Bytes: 2 
Cycles: 1 



10 10 10 1 



Encoding: 

Operation: ANL 

(A) <- (A) a (direct) 

ANL A,@Ri 

Bytes: 1 
Cycles: 1 



direct address 



10 1 



Encoding: 

Operation: ANL 

(A)<-(A)A((Ri)) 

ANL A,#data 

Bytes: 2 
Cycles: 1 



1 1 i 



10 1 



Encoding: 

Operation: ANL 

(A) <- (A) a #data 

ANL direct.A 

Bytes: 2 
Cycles: 1 



10 



immediate data | 



10 10 10 



Encoding: 

Operation: ANL 

(A) <— (direct) a (A) 

ANL direct,#data 
Bytes: 3 
Cycles: 2 



J | direct 



address 



10 1 



11 



Encoding: 

Operation: ANL 

(direct) <-(direct) a #data 



| immediate data 



March 1995 



2-63 



Philips Semiconductors 




80C51 family programmer's guide 
and instruction set 



ANL C,<src-bit> 

Function: Logical-AND for bit variables 

Description: If the Boolean value of the source bit is a logical then clear the carry flag; otherwise leave the carry flag 
in its current state. A slash (T) preceding the operand in the assembly language indicates that the logical 
complement of the addressed bit is used as the source value, bur the source bit itself is not affected No 
other flags are affected. 

Only direct addressing is allowed for the source operand. 
Example: Set the carry flag if, and only if, P1 .0 = 1 , ACC.7 = 1 , and OV = 0: 
MOV C,P1 .0 ;LOAD CARRY WITH INPUT PIN STATE 
ANL C,ACC.7;AND CARRY WITH ACCUM. BIT 7 
ANL C./OV ;AND WITH INVERSE OF OVERFLOW FLAG 



ANL C.bit 

Bytes: 2 
Cycles: 2 



Encoding: 
Operation: ANL 

ANL C/bit 

Bytes: 2 
Cycles: 2 



10 



10 | bit address 



(C) <- (C) a ( 



10 11 



Encoding: 
Operation: ANL 

(C)<-(C)Al(bit) 







bit address 



- 



March 1995 



2-64 



Philips Semiconductors 



80C51 Family 




80C51 family programmer's guide 
and instruction set 


CJNE <dest-byte>,<src-byte>,rel 







Function: Compare and Jump if Not Equal 

Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The 
branch destination is computed by adding the signed relative-displacement in the last instruction byte to 
the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned 
integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is 
cleared. Neither operand is affected. 

The first two operands allow four addressing mode combinations: the Accumulator may be compared with 
any directly addressed byte or immediate data, and any indirect RAM location or working register can be 
compared with an immediate constant. 

Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence, 



CJNE 
NOT_EQ JC 



R7,#60H,NOT_EQ 



REQ_LOW 



R7 = 60H. 
IF R7 < 60H. 
R7 > 60H. 



sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this 
instruction determines whether R7 is greater or less than 60H. 

If the data being presented to Port 1 is also 34H, then the instruction, 

WAIT: CJNE A,P1,WAIT 

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does 
equal the data read from P1 . (If some other value was being input on P1 , the program will loop at this 
point until the P1 data changes to 34H.) 



CJNE A,direct,rel 
Bytes: 3 
Cycles: 2 



Encoding: 
Operation: 



10 11 



1 1 



direct address 



rel. address 



(PC) <- (PC) + 3 
IF (A) <> (direct) 
THEN 

(PC). 

IF(A)< (direct) 
THEN. 



ELSE 



(PC) + relative offset 




March 1995 



2-65 



Philips Semiconductors 



80C51 family programmer's guide 
and instruction set 



CJNE A,#data,rel 
Bytes: 3 
Cycles: 2 



Encoding: |l 1 1 | o 1 ZZ] (Z™^ 



rel. address 



Operation: 



(PC) <- (PC) + 3 
IF (A) <> data 
THEN 



IF(A)< 
THEN 

ELSE 



(PC) <- (PC) + relative 

(C)<-1 
(C)<-0 



CJNE Rn,#data,rel 
Bytes: 3 
Cycles: 



Encoding: 
Operation: 



2 

H 



t — r~< — n 1 r — ~ 

1 1 I 1 r r r I L 



ELSE 

CJNE @Ri,#data,rel 
Bytes: 3 
Cycles: 2 



(PC) <- (PC) + 3 
IF (R n ) < > data 
THEN 

(PC) <- (PC) + relative offset 

IF(R n )< data 
THEN 

(C)^-1 



(C)^0 



Encoding: 
Operation: 



10 11 



1 1 



immediate data 



rel. address 



(PC) <- (PC) + 3 
IF ((Rj)) < > data 
THEN 

(PC) <- (PC) + relative offset 

IF((Ri))< dafa 
THEN 



ELSE 



(C). 
(C). 



March 1995 



Philips Semiconductors 



>ri ~ CH s= k. 80C51 family programmer's quid 

i0C51 Family and instruction set 



CLR A 

Function: 
Description: 
Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Clear Accumulator 

The Accumulator is cleared (all bits reset to zero). No flags are affected. 
The Accumulator contains 5CH (01011100B). The instruction, 
CLR A 

will leave the Accumulator set to 00H (0O000000B). 
1 

* 

1 



1110 



10 



CLR 

(A)<- 



CLR bit 



Function: Clear bit 

Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag 
or any directly addressable bit. 

Example: Port 1 has previously been written with 5DH (01 01 1 1 01 B). The instruction, 



3d. CLR can 



CLR P1 2 

will leave the port set to 59H (01 01 1 001 B). 



CLR C 

Bytes: 1 
Cycles: 1 



Encoding: 

Operation: CLR 

(C)<-0 

CLR bit 

Bytes: 2 
Cycles: 1 



1 1 1 1 



Encoding: 

Operation: CLR 

(bit) <- 



1 1 | 1 



bit 



March 1995 



2-67 



Philips Semiconductors 



CPL A 

Function: 
Description: 

Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Complement Accumulator 

Each bit of the Accumulator is logically complemented (one's complement). Bits which 
contained a one are changed to a zero and vice-versa. No flags are affected. 

The Accumulator contains 5CH (01011100B). The instruction, 
CPL A 

will leave the Accumulator set to 0A3H (10100011B). 

1 

1 



1111 



1 o o 



CPL 

(A)«- 



1 (A) 



CPL bit 

Function: 
Description: 



Example: 



Complement bit 

The bit variable specified is complemented. A bit which had been a one is changed to zero and 
vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. 

Note: When this instruction is used to modify an output pin, the value used as the original data will be read 
from the output data latch, not the input pin. 

Port 1 has previously been written with 5DH (01 01 11 01 B). The instruction sequence, 
CPL P1.1 
CPL P1.2 

will leave the port set to 5BH (01 01 1 01 1 B). 



CPL C 

Bytes: 1 
Cycles: 1 



10 11 



Encoding: 

Operation: CPL 

(C)<-1 (C) 



11 



CPL bit 

Bytes: 2 
Cycles: 1 



| 1 



1 1 



Encoding: 

Operation: CPL 

(bit)«-l (bit) 



10 



bit address 



March 1 995 2-68 



Philips Semiconductors 



Familv 80051 family P ro g rammer ' s 9 ui( 

ouubi i-amny and instruction s 



DA A 

Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 





Decimal-adjust Accumulator for Addition 

DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variable (each 
in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used 
to perform the addition. 

If Accumulator bits 3-0 are greater than nine (xxxl 01 0-xxx1 1 1 1 ), or if the AC flag is one, six is added to 
the Accumulator, producing the proper BCD digit in the low-order nibble. This internal addition would set 
the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would 
not clear the carry flag otherwise. 

If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxx-111xxxx), these 
high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this 
would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear the carry. The 
carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple 
precision decimal addition. OV is not affected. 

All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal 
conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and 
PSW conditions. 

Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does 
DA A apply to decimal subtraction. 

The Accumulator holds the value 56H (01 01 011 OB) representing the packed BCD digits of the decimal 
number 56. Register 3 contains the value 67H (01100111 B) representing the packed BCD digits of the 
decimal number 67. The carry flag is set.. The instruction sequence, 



ADDC 
DA 



A,R3 
A 



will first perform a standard two's-complement binary addition, resulting in the value 0BEH (10111110B) in 
the Accumulator. The carry and auxiliary carry flags will be cleared. 

The Decimal Adjust instruction will then alter the Accumulator to the value 24H (001 001 00B), indicating 
the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, 
and the carry-in. The carry flag will be set by the Decimal Adjust instruction, indicating that a decimal 
overflow occurred. The true sum 56, 67, and 1 is 124. 

BCD variables can be incremented or decremented by adding 01 H or 99H. If the Accumulator initially 
holds 30H (representing the digits of 30 decimal), the the instruction sequence, 

ADD A,#99H 
DA A 



will leave the carry set and 29H in the Accumulator, since 30 + 99 = 
can be interpreted to mean 30 - 1 = 29. 



129. The low-order byte of the sum 



I 



110 1 



10 



DA 

-contents of Accumulator are BCD 
IF [[(A 3 -o)>9]v[(AC) = 1]] 
THEN(A3_o) <- (A3.0) + 6 
AND 

IF [[(A 7 . 4 )>9]v[(C) = 1]j 
THEN(A 7 . 4 ) ^ (A 7 .„) + 6 



March 1995 



2-69 



DEC byte 



Function: Decrement 



Description: The variable indicated is decremented by 1 . An original value of 00H will underflow to OFFH. No flags are 
affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. 

Wofe: When this instruction is used to modify an output port, the value used as the original data will be 
read from the output data latch, not the input pin. 

Example: Register contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H and 40H, 
respectively. The instruction sequence, 



DEC 
DEC 



@R0 
RO 



DEC @R0 

will leave register set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and 3FH. 



DEC A 

Bytes: 1 
Cycles: 1 



Encoding: 

Operation: DEC 

(A)<- (A)-1 

DEC Rn 

Bytes: 1 
Cycles: 1 



1 1 



Encoding: 



1 



1 r r r 



Operation: DEC 

(Rn) <- (Rn) " 1 



DEC direct 

Bytes: 2 
Cycles: 1 



1 



Encoding: 

Operation: DEC 

(direct) «- (direct) - 1 



10 1 



direct address 



DEC @Ri 

Bytes: 
Cycles: 

Encoding: 



1 



1 1 i 



Operation: DEC 

«Ri))<-((Ri))-l 



March 1995 



2-70 



Philips Semiconductors 



80C51 Family 






80C51 family programmer's guide 
and instruction set 


DIV AB 







Description: 



Example: 



Cycles: 

Encoding: 
Operation: 



DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in 
register B. 

The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The 
carry and OV flags will be cleared. 

Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register will be 
undefined and the overflow flag will be set. The carry flag is cleared in any case. 

The Accumulator contains 251 (OFBH or 111 11 011 B) and B contains 18 (12H or 0001001 OB). The 
instruction, 

DIV AB 



wc 
251 

1 

4 



leave 1 3 in the Accumulator (ODH or 00001 1 01 B) and the value 1 7 (1 1 H or 0001 0001 B) in B, since 
= (13 x 18) + 17. Carry and OV will both be cleared. 



10 



10 



DIV 

(A) 15 . 8 <- (A)/(B) 

(B) 7 -o 



March 1995 



2-71 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



DJNZ <byte>,<rel-addr> 



Function: 
Description: 



Example: 



DJNZ Rn.rel 
Bytes: 
Cycles: 

Encoding: 
Operation: 



Decrement and Jump if Not Zero 

DJNZ decrements the location indicated by 1 , and branches to the address indicated by the second 
operand if the resulting value is not zero. An original value of 00H will underflow to OFFH. No flags are 
affected. The branch destination would be computed by adding the signed relative-displacement value in 
the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. 

The location decremented may be a register or directly addressed byte. 

Note: When this instruction is used to modify an output port, the value used as the original port data will 
be read from the output data latch, not the input pins. 

Internal RAM locations 40H, 50H, and 60H contain the values 01 H, 70H, and 15H, respectively. The 
instruction sequence, 



DJNZ 
DJNZ 
DJNZ 



Encoding: 
Operation: 



40H,LABEL_1 
50H,LABEL_2 
60H,LABEL_3 



will cause a jump to the instruction at LABEL_2 with the values OOh, 6FH, and 1 5H in the three RAM 
locations. The first jump was not taken because the result was zero. 

This instruction provides a simple was of executing a program loop a given number of times, or for adding 
a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruction sequence, 

MOV R2,#8 
TOGGLE: CPL P1.7 

DJNZ R2.TOGGLE 

will toggle P1 .7 eight times, causing four output pulses to appear at bit 7 of output Port 1 . Each pulse will 
last three machine cycles, two for DJNZ and one to alter the pin. 



1 1 



1 



rel. address 



DJNZ 

(PC) <- (PC) + 2 

(Rn)«~ (Rn)-1 
IF (R„) > or (R n ) < 
THEN 

(PC) «- (PC) + rel 



DJNZ direct.rel 
Bytes: 3 
Cycles: 2 



110 1 



10 1 



direct data 



rel. address 



DJNZ 

(PC) <- (PC) + 2 
(direct) <- (direct) - 1 
IF (direct) > or (direct) < 
THEN 

(PC) <- (PC) + rel 



March 1995 



2-72 



Philips Semiconductors 



anrc1 c»r*.a„ 80C51 family programmer's guide 

80C51 Fam.ly ^ jnstructjo y n SQ{ 



INC <byte> 
Function: 
Description: 



Example: 



INC A 

Bytes: 
Cycles: 

Encoding: 
Operation: 

INC Rn 

Bytes: 
Cycles: 

Encoding: 
Operation: 



in OFFH and 40H, 



Increment 

INC increments the indicated variable by 1. An original value of OFFH will overflow to 00H. No flags are 
affected. Three addressing modes are allowed: register, direct, or register-indirect. 

Note: When this instruction is used to modify an output port, the value used as the original port data will 
be read from the output data latch, not the input pins. 

Register contains 7EH (01111110B). Internal RAM locations 7EH and 
respectively. The instruction sequence, 

INC @R0 
INC RO 
INC @R0 

will leave register set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) 00H and 
41 H. 




| 1 



INC 

(A)<- (A) + 1 



1 r r r 



INC 

(Rn) *- (Rn) + 1 



INC direct 

Bytes: 
Cycles: 

Encoding: 
Operation: 

INC @Ri 

Bytes: 
Cycles: 



Operation: 



1 1 



INC 

(direct) <— (direct) + 1 



INC 

(«))«- «Ri)) + 1 



direct address 



| | 1 1 i 



March 1995 



Philips Semiconductors 



ftnr^i FamiK/ 80C51 fami| y programmer's guide 

80C51 Family and instruction set 



INC DPTR 



Function: 

Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Increment Data Pointer 

Increment the 16-bit data 
low-order byte of the data 
flags are affected. 

This is the only 16-bit register which can be incremented. 

Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence, 

INC DPTR 
INC DPTR 
INC DPTR 

will change DPH and DPL to 13H and 01 H. 
1 

2 



I; an overflow of the 
high-order byte (DPH). No 



1 



11 



INC 

(DPTR) • 



(DPTR) + 1 



JB bit.rel 



Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Jump if Bit set 

If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The 
branch destination is computed by adding the signed relative-displacement in the third instruction byte to 
the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No 
flags are affected. 

The data present at input port 1 is 11 001 01 OB. The Accumulator holds 56 (01 01 011 0B). The instruction 
sequence, 

JB P1.2.LABEL1 
JB ACC.2.LABEL2 

will cause program execution to branch to the instruction at label LABEL2. 

3 



1 bit address 



□ 



rel. address 



JB 

(PC) <- (PC) + 3 
IF (bit) = 1 
THEN 

(PC) <- (PC) + rel 



March 1995 



2-74 



Philips Semiconductors 



80C51 Family 


80C51 family programmer's guide 
and instruction set 


JBC bit.rel 





Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



If the indicated bit is a one, branch to the address indicated; otherwise proceed with the next instruction. 
The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed 
relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of 
the next instruction. No flags are affected. 

Note: When this instruction is used to test an output pin, the value used as the original data will read from 
the output data latch, not the input pin. 

The Accumulator holds 56H (01 01 011 OB). The instruction sequence, 

JBC ACC.3.LABEL1 
JBC ACC.2.LABEL2 

will cause program execution to continue at the instruction identified by the LABEL2, with the Accumulator 
modified to 52H (01010010B). 

3 

2 



1 







bit address 



rel. 



JBC 

(PC) <- (PC) + 3 
IF (bit) = 1 
THEN 
(bit) <- 

(PC) «- (PC) + rel 



JC rel 



Function: 
Description: 

Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Jump if Carry is set 

If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The 
branch destination is computed by adding the signed relative-displacement in the second instruction byte 

The carry flag is cleared. 

JC LABEL1 
CPL C 
JC LABEL2 

wnkseUhe carry and cause program execution to continue at the instruction identified by the label 




1 



1 | rel. address" 



JC 

(PC) «- (PC) + 2 
IF (C) = 1 
THEN 

(PC). 



• (PC) + rel 



March 1995 



2-75 



Philips Semiconductors 



p. •.. 80C51 family programmer's guide 

051 Family and instruction set 



JMP ©A+DPTR 



Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Jump indirect 

Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and load the 
resulting sum to the program counter. This will be the address for subsequent instruction fetches. 
Sixteen-bit addition is performed (modulo 2 16 ): a carry-out from the low-order eight bits propagates 
through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are 
affected. 

An even number from to 6 is in the Accumulator. The following sequence of instructions will branch to 
one of four AJMP instructions in a jump table starting at JMP_TBL: 

MOV DPTR,#JMP_TBL 
JMP ©A+DPTR 
JMP_TBL: AJMP LABELO 
AJMP LABEL1 
AJMP LABEL2 
AJMP LABEL3 

If the Accumulator equals 04H when starting this sequence, execution will jump to label LABEL2. 
Remember that AJMP is a two-byte instruction, so the jump instructions start at every other address. 

1 

2 



111 



11 



JMP 

(PC) <- (A) + (DPTR) 



JNB bit.rel 



Function: 
Description: 

Example: 



Cycles: 

Encoding: 
Operation: 



Jump if Bit Not set 

If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. 
The branch destination is computed by adding the signed relative-displacement in the third instruction 
byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not 
modified. No flags are affected. 

holds 56H (01 01 011 OB). The instruction 



The data present at input port 1 is 1100101 
sequence, 

JNB P1.3.LABEL1 
JNB ACC.3.LABEL2 

will cause program execution to continue at the instruction at label LABEL2. 

3 



11 



JNB 
(PC) «- (PC) + 3 
IF (bit) = 
THEN 
(PC) <- (PC) + rel 



I | bit address ~| | rel. address "| 



March 1995 2-76 



Philips Semiconductors 



80C51 Family 


80C51 family programmer's guide 
and instruction set 


JNC rel 




Function: Jump if Carry Not set 





Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The 
branch destination is computed by adding the signed relative-displacement in the second instruction byte 
to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. 

Example: The carry flag is set. The instruction sequence, 

JNC LABEL1 

CPL C 

JNC LABEL2 

will clear the carry and cause program execution to continue at the instruction identified by the label 
LABEL2. 



Bytes: 
Cycles: 

Encoding: 
Operation: 



1 1 



rel. address 



JNC 

(PC) <- (PC) + 2 
IF (C) = 
THEN 
(PC) <- (PC) + rel 



JNZ rel 



Function: Jump if Accumulator Not Zero 

Description: If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with the next 
instruction. The branch destination is computed by adding the signed relative-displacement in the second 
instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are 
affected. 



Example: The Accumulator originally holds 00H. The instruction sequence, 



Bytes: 
Cycles: 

Encoding: 
Operation: 



JNZ 



LABEL2 



will set the Accumulator to 01 H and continue at label LABEL2. 

2 
2 



1 



11 | 



rel. address 



] 



JNZ 

(PC) <- (PC) + 2 
IFA*0 

THEN (PC) «— (PC) + rel 



March 1995 



2-77 



Philips Semiconductors 



flnr^i Famiiv 80051 family P r °9 r a mmer ' s g u 'de 

80C51 Family and instruction set 



JZ rel 

Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Jump if Accumulator Zero 

If all bits of the Accumulator are zero, branch to the indicated address; otherwise proceed with the next 
instruction. The branch destination is computed by adding the signed relative-displacement in the second 
instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are 
affected. 

The Accumulator originally holds 01 H. The instruction sequence, 

JZ LABEL1 

DEC A 

JZ LABEL2 

will change the Accumulator to 00H and cause program execution to continue at the instruction identified 
by the label LABEL2. 



110 







JZ 

(PC) <- (PC) + 2 
IFA = 

THEN (PC) <- (PC) + rel 



LCALL addr16 



Function: Long Call 



LCALL calls a subroutine located at the indicated address. The instruction adds three to the program 
counter to generate the address of the next instruction and then pushes the 1 6-bit result onto the stack 
(low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the PC are 
then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution 
continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



64k-byte program memory s 

Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory location 
1234H. After executing the instruction, 

LCALL SUBRTN 

at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 
26H and 01 H, and the PC will contain 1 235H. 

3 

2 



1 



10 



addr15-addr8 



addr7-addr0 



LCALL 

(PC) «- (PC) + 3 
(SP) *- (SP) + 1 
((SP)) <- (PC 7 . ) 
(SP) <- (SP) + 1 
((SP)) <- (PC 15 . 8 ) 
(PC) <- addr 15 _ 



March 1995 



2-78 



Philips Semiconductors 



80051 Fami ' 



80C51 family programmer's guide 
and instruction 



LJMP addr16 (Implemented in 87C751 and 87C752 for in-circuit emulation only.) 



Function: 
Description: 

Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Long Jump 

LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order 
bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore 
be anywhere in the full 64k program memory address space. No flags are affected. 



The label "JMPADR" is assigned to the instruction at program memory location 1234H. The instruction, 
UMP JMPADR 

at location 0123H will load the program counter with 1234H. 
3 
2 







10 



addrl 5-addr8 



addr7-addr0 



UMP 

(PC) <- addr 15 . 



MOV <dest-byte>,<src-byte> 



Function: 
Description: 



Example: 



MOV A,Rn 
Bytes: 
Cycles: 

Encoding: 
Operation: 



Move byte variable 

The byte variable indicated by the second operand is copied into the location specified by the first 
operand. The source byte is not affected. No other register or flag is affected. 

This is by far the most flexible operation. Fifteen combinations of source and destination addressing 
modes are allowed. 

Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data present at input 
port 1 is 11 001 01 0B (0CAH). The instruction sequence, 



MOV 


R0,#30H 


;R0 < = 30H 


MOV 


A,@R0 


;A < = 40H 


MOV 


R1,A 


;R1 < = 40H 


MOV 


B,@R1 


;B<= 10H 


MOV 


@R1,P1 


;RAM (40H) < = 0CAH 


MOV 


P2.P1 


;P2 #0CAH 



leaves the value 30H in register 0, 40H in both the Accumulator and register 1 , 1 0H in register B, and 
0CAH (11 001 01 0B) both in RAM location 40H and output on port 2. 



1110 



MOV 

(A) <- (R n ) 



March 1995 



2-79 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



•MOV A,direct 

Bytes: 2 
Cycles: 1 



Encoding: 

Operation: MOV 

(A) <- (direct) 

MOV A,@Ri 

Bytes: 1 
Cycles: 1 



1 1 1 io | o 1 o 1 ~ pii"* 



1110 



Encoding: 

Operation: MOV 

(A) <- ((Ri)) 

MOV A,#data 

Bytes: 2 
Cycles: 1 



1 1 i 



: |0 1 1 1 | 



Encoding: 

Operation: MOV 

(A) <- #data 

MOV Rn,A 

Bytes: 1 
Cycles: 1 



10 



1111 



Encoding: 
Operation: MOV 

(Rn) *- (A) 

MOV Rn,direct 

Bytes: 2 
Cycles: 2 



1 r r r 



Encoding: 

Operation: MOV 

(R n )<- (direct) 

MOV Rn,#data 

Bytes: 2 
Cycles: 1 



Encoding: 
Operation: MOV 

(Rn)< 



111 



1 r r r 



immediate data 



1 1 | 1 r r ~ 



direct address 



immediate data 



*MOV A.ACC is not a valid instruction. 



March 1995 



2-80 



Philips Semiconductors 



80C51 Familv 80C51 family programmer's guide 

y and instruction set 



MOV direct,A 

Bytes: 2 
Cycles: 1 



Encoding: 

Operation: MOV 

(direct) <- (A) 



11110 10 1 



l dlreCladdreSS I 



MOV direct.Rn 

Bytes: 2 
Cycles: 2 



1 



II 



Encoding: 

Operation: MOV 

(direct) <- (R„) 

MOV direct.direct 
Bytes: 3 
Cycles: 2 



1 r r r 



Encoding: 



10 



1 



10 1 



Operation: MOV 

(direct) «- (direct) 

MOV direct,@Ri 
Bytes: 2 
Cycles: 2 



dir. addr. (src) 





10 



Encoding: 

Operation: MOV 

(direct) «- ((R|)) 



1 1 i 



direct address 



MOV direct,#data 
Bytes: 3 
Cycles: 2 



111 



Encoding: 

Operation: MOV 

(direct) «- #data 

MOV @Ri,A 

Bytes: 1 
Cycles: 1 



10 1 



direct address") | immediate data 



1111 



Encoding: 
Operation: MOV 

«Ri» *- (A) 



1 1 1 I 



March 1 995 



2-81 



Philips Semiconductors 



)C51 Family 



80C51 family programmer's guide 
and instruction se 



MOV @Ri,direct 
Bytes: 2 
Cycles: 2 



10 10 



Encoding: 

Operation: MOV 

((Ri))<- (direct) 



1 1 i 



MOV @Ri,#data 
Bytes: 2 
Cycles: 1 



Encoding: 
Operation: MOV 

((Ri)) 



111 



1 1 i 



immediate data 



MOV 



:-bit>,<src-bit> 



Function: Move bit data 

Description: The Boolean variable indicated by the second operand is copied into the location specified by the first 
operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No 
other register or flag is affected. 

Example: The carry flag is originally set. The data present at input Port 3 is 1 1 0001 01 B. The data previously written 
to output Port 1 is 35H (00110101 B). The instruction sequence, 

MOV P1.3.C 
MOV C.P3.3 
MOV P1.2.C 



will leave the carry cleared and < 



MOV C,bit 

Bytes: 2 
Cycles: 1 



I (001 11 001 B). 



Encoding: 

Operation: MOV 

(C) <- (bit) 



MOV bit.C 

Bytes: 2 
Cycles: 2 



1 1 1 



bit address 



10 1 



10 



bit address 



Operation: MOV 

(bit)<- (C) 



March 1995 



2-82 



Philips Semiconductors 



80C51 Family 


80C51 family 


programmer's guide 
and instruction set 



MOV DPTR,#data16 




Function: Load Data Pointer with a 1 6-bit constant 





Description: 



Example: 



The Data Pointer is loaded with the 1 6-bit constant indicated. The 1 6-bit constant is loaded into the 
second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third 
byte (DPL) holds the low-order byte. No flags are affected. 

This is the only instruction which moves 1 6 bits of data at once. 

The instruction, 

MOV DPTR,#1234H 

will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H. 



Bytes: 3 
Cycles: 2 



Encoding: 
Operation: 



10 1 







immed. data15-8 



immed. data7-0 



MOV 

(DPTR) <- (#data 15 _ ) 

DPH □ DPL<-#data 15 . 8 D #data 7 . 



MOVC A,@A+<base-reg> 







Function: Move Code byte 

Description: The MOVC instructions load the Accumulator with a code byte, or constant from program memory. The 
address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the 
contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, 
the PC is incremented to the address of the following instruction before being added with the Accumulator; 
otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the 
low-order eight bits may propagate through higher-order bits. No flags are affected. 

Example: A value between and 3 is in the Accumulator. The following instructions will translate the value in the 
Accumulator to one of four values defined by the DB (define byte) directive: 



REL_PC: 



INC 

MOVC 

RET 

DB 

DB 

DB 

DB 



A 

A,@A+PC 

66H 
77H 
88H 
99H 



If the subroutine is called with the Accumulator equal to 01 H, it will return with 77H in the Accumulator. 
The INC A before the MOVC instruction is needed to "get around" the RET instruction above the table. If 
several bytes of code separated the MOVC from the table, the corresponding number would be added to 
the Accumulator instead. 



MOVC A,@A+DPTR 



Bytes: 
Cycles: 



Encoding: 
Operation 



1 



11 



MOVC 
(A) <- ((A) + (DPTR)) 



March 1995 



2-83 



Philips Semiconductors 



80C51 family programmer's guide 
and instruction set 



80C51 Family 



MOVC A.OA+PC 



Bytes: 
Cycles: 

Encoding: 
Operation: 



10 



11 



MOVC 

(PC) <- (PC) + 1 
(A) «- ((A) + (PC)) 



MOVX <dest-byte>,<src-byte> (Not implemented in the 8XC752 or 8XC752) 
Function: Move External 

Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, hence 
the "X" appended to MOV. There are two types of instructions, differing in whether they provide an 
eight-bit or sixteen-bit indirect address to the external data RAM. 

In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit address 
multiplexed with data on P0. Eight bits are sufficient for external I/O expansion decoding or for a relatively 
small RAM array. For somewhat larger arrays, port pins can be used to output higher-order address bits. 
These pins would be controlled by an output instruction preceding the MOVX. 

In the second type of MOVX instruction, The Data Pointer generates a sixteen-bit address. P2 outputs the 
high-order eight address bits (the contents of DPH) while P0 multiplexes the low-order eight bits (DPL) 
with data. The P2 Special Function Register retains its previous contents while the P2 output buffers are 
emitting the contents of DPH. This form is faster and more efficient when accessing very large data arrays 
(up to 64k bytes), since no additional instructions are needed to set up the output ports. 

It is possible in some situations to mix the two MOVX types. A large RAM array with its high-order address 
lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order address bits to 
P2 followed by a MOVX instruction using R0 or R1. 

Example: An external 256 byte RAM using multiplexed address/data lines is connected to the 8051 Port 0. Port 3 
provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. Registers and 1 
contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence, 

MOVX A,@R1 
MOVX @R0,A 

copies the value 56H into both the Accumulator and external RAM location 12H. 



MOVX A,@Ri 



Cycles: 

Encoding: 
Operation: 



1110 



1 



n 



MOVX 

(A) <- ((R|)) 



MOVX A,@DPTR 
Bytes: 1 
Cycles: 2 



Encoding: 
Operation: 



1 







MOVX 
(A) <- ((DPTR)) 



March 1995 



2-84 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's gi 
and instruction 



MOVX @Ri,A 

Bytes: 1 

Cycles: 2 

a . I 1 1 1 1 I 1 i 

a- i 1 



Operation: MOVX 

((Ri)) «- (A) 

MOVX @DPTR,A 
Bytes: 1 
Cycles: 2 



1 1 1 1 



Encoding: 

Operation: MOVX 

((DPTR)) «- (A) 



MUL AB 



Function: 
Description: 

Example: 



Cycles: 

Encoding: 
Operation: 



Multiply 

MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The low-order byte 
of the sixteen-bit product is left in the Accumulator, and the high-order byte in B. If the product is greater 
than 255 (OFFH) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. 

Originally the Accumulator holds the value 80 (50H). Register B holds the value 1 60 (OAOH).The 
instruction, 

MUL AB 

will give the product 12,800 (3200H), so B is changed to 32H (001 1001 0B) and the Accumulator is 
cleared. The overflow flag is set, carry is cleared. 



10 10 



10 



MUL 

(A) 7 -o^ (A)x(B) 

(B) l5-8 



March 1995 



Philips Semiconductors 



)C51 Family 



80C51 family programmer's guide 
and instruction s& 



NOP 



Function: No Operation 
Description: Execution continues at the following instruction. Other than the PC, no registers or 



Example: 



It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 
SETB/CLR sequence would generate a one-cycle pulse, so four additiona cycles 
may be done (assuming are enabled) with the instruction sequence, 

CLR P2.7 
NOP 
NOP 
NOP 
NOP 

SETB P2.7 




Bytes: 
Cycles: 

Encoding: 
Operation: 











NOP 

(PC) *- (PC) + 1 



ORL <dest-byte>,<src-byte> 



Function: 
Description: 



Example: 



Logical-OR for byte variables 

ORL performs the bitwise logical-OR c 
destination byte. No flags are affected. 



l the indicated variables, storing the results in the 

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the 
source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct 
! can be the Accumulator or immediate data. 



Note: When this instruction is used to modify an output port, the value used as the original port data will 
be read from the output data latch, not the input pins. 

If the Accumulator holds 0C3H (11 00001 1B) and R0 holds 55H (01 01 01 01 B) then the instruction, 
ORL A,R0 

will leave the Accumulator holding the value 0D7H (11010111 B). 

When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM 
location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be 
either a constant data value in the instruction or a variable computed in the Accumulator at run-time. The 
instruction, 

ORL P1 ,#001 1001 0B 

will set bits 5, 4, and 1 of output Port 1. 



ORL A,Rn 

Bytes: 1 
Cycles: 1 



Encoding: 
Operation: 



10 



ORL 
(A)«- 



(A) v (R„) 



March 1995 



2-86 



Philips Semiconductors 



Family 



80C51 family programmer's guide 
and instruction set 



ORL A,direct 

Bytes: 2 
Cycles: 1 

| 1 | 1 1 ~ [ direct addn 



Operation: ORL 

(A) <- (A) v (direct) 

ORL A,@Ri 



Cycles: 1 



10 



Encoding: 

Operation: ORL 

(A) <- (A) v ((R|)) 



ORL A,#data 

Bytes: 2 
Cycles: 1 



1 1 i 



10 



Encoding: 

Operation: ORL 

(A)<- (A)v#data 

ORL direct,A 

Bytes: 2 
Cycles: 1 



10 



10 



10 



Encoding: 

Operation: ORL 

(direct) <- (direct) v (A) 

ORL direct,#data 
Bytes: 3 
Cycles: 2 



1 



Encoding: 

Operation: ORL 

(direct) <- (direct) v 



immediate data 



direct address 



| 1 1 



direct address 



| immediate data 



March 1995 



2-87 



Philips Semiconductors 



80C51 Family 




80C51 family programmer's guide 
and instruction set 


ORL C,<src-bit> 







Function: Logical-OR for bit variables 

Description: Set the carry flag if the Boolean value is a logical 1 ; leave the carry in its current state otherwise. A slash 
(V) preceding the operand in the assembly language indicates that the logical complement of the 
addressed bit is used as the source value, but the source bit itself is not affected. No other flags are 
affected. 

Example: Set the carry flag if and only if P1 .0 = 1 , ACC.7 = 1 , or OV = 0: 



ORL 
ORL 
ORL 



CP1.0 

OACC.7 

O/OV 



LOAD CARRY WITH INPUT PIN P10 

OR CARRY WITH THE ACC. BIT 7 

OR CARRY WITH THE INVERSE OF OV. 



ORL C.bit 

Bytes: 2 

Cycles: 2 

Encoding: |o 1 1 1 | 1 



Operation: ORL 

(C) <- (C) v (bit) 

ORL C,/bit 

Bytes: 2 
Cycles: 2 



Encoding: 

Operation: ORL 

(C)<- (C)v( 



1 1 



bit address 



bit address 



March 1995 



2-88 



Philips Semiconductors 



80C51 Family 




80C51 family programmer's guide 
and instruction set 


POP direct 







Function: Pop from stack 

Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is 
decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags 
are affected. 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain 
the values 20H, 23H, and 01 H, respectively. The instruction sequence, 

POP DPH 
POP DPL 

will leave the Stack Pointer equal to the va 
instruction, 

POP SP 

will leave the Stack Pointer set to 20H. Note that in t 
to 2FH before being loaded with the value popped ( 

2 

2 



)H and the Data Pointer set to 0123H. At this point the 



al case the Stack Pointer was decremented 



110 1 







direct address 



POP 

(direct) <- ((SP)) 
(SP) <- (SP) - 1 



PUSH direct 



Function: 
Description: 







Bytes: 
Cycles: 

Encoding: 
Operation: 



Push onto stack 







The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the 
internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected. 



Example: On entering an interrupt routine the Stack 
The instruction sequence, 



holds the value 01 23H. 



PUSH DPL 
PUSH DPH 

will leave the Stack Pointer set to 0BH and store 23H and 01 H in internal RAM locations 0AH and 0BH, 
respectively. 

2 

2 



1 







direct address 



PUSH 

(SP) «- (SP) + 1 
((SP)) «~ (direct) 



March 1995 



Philips Semiconductors 



80C51 Family 




80C51 family programmer's guide 
and instruction set 




RET 







Function: Return from subroutine 

Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack 
Pointer by two. Program execution continues at the resulting address, generally the instruction 
immediately following an ACALL or LCALL. No flags are affected. 



Example: The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH contain the 
values 23H and 01 H, respectively. The instruction, 

RET 



will leave the Stack Pointer equal to the value 09H. Program execution will continue at location 0123H. 



Bytes: 1 
Cycles: 2 



1 1 



Encoding: 
Operation: RET 

(PC 15 - 8 ) «" ((SP)) 
(SP) <r- (SP) - 1 

(PC 7 . ) <- ((SP)) 
(SP) <- (SP) - 1 



RETI 



Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Return from interrupt 

RETI pops the high- and low-order bytes of the PC successively from the stack, and restores the interrupt 
logic to accept additional interrupts at the same priority level as the one just processed. The Stack Pointer 
is left decremented by two. No other registers are affected; the PSW is not automatically restored to its 
pre-interrupt status. Program execution continues at the resulting address, which is generally the 
instruction immediately after the point at which the interrupt request was detected. If a lower- or 
same-level interrupt has been pending when the RETI instruction is executed, that one instruction will be 

n interrupt was detected during the instruction 
and OBH contain the values 23H and 01 H, 



The Stack Pointer originally contains the value OBH 
ending at location 0122H. Internal RAM locatioi 
respectively. The instruction, 

RETI 

will leave the Stack Pointer equal to 09H and return program execution to location 0123H. 
1 



1 1 1 



RETI 

(PC 15 . 8 ) <- ((SP)) 
(SP) <- (SP) - 1 
(PC 7 _ ) «- ((SP)) 
(SP)<-(SP)-1 



March 1995 



2-90 



Philips Semiconductors 



annci comii,, 80C51 family programmer's guide 

80C51 Family and jnstructjon set 



RL A 

Function: Rotate Accumulator Left 

Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit position. No 
flags are affected. 

Example: The Accumulator holds the value 0C5H (11 0001 01 B). The instruction, 
RL A 

leaves the Accumulator holding the value 8BH (10001 01 1B) with the carry unaffected. 
Bytes: 1 
Cycles: 1 

Encoding: |o 1 [o 1 1 | 

Operation: RL 

(A n+ i)<-(A„),n = 0-6 
(A0)<-(A7) 



RLC A 



Function: 
Description: 

Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Rotate Accumulator Left through the Carry flag 

The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into 
the carry flag; the original state of the carry flag moves into the bit position. No other flags are affected. 

The Accumulator holds the value 0C5H (11000101 B), and the carry is zero. The instruction, 
RLC A 

leaves the Accumulator holding the value 8AH (10001 01 0B) with the carry set. 

1 

1 



11 



II 



1 1 



RLC 

(A n+ i) «- (A„), n = 
(A0)<-(C) 
(C) <- (A7) 



0-6 



March 1995 



Philips Semiconductors 



c .. 80C51 family programmer's guide 

051 Family and instruction set 



RR A 

Function: Rotate Accumulator Right 

Description: The eight bits in the Accumulator are rotated one bit to the right. Bit is rotated into the bit 7 position. No 
flags are affected. 

Example: The Accumulator holds the value 0C5H (11 000101 B). The instruction, 
RR A 

leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. 
Bytes: 1 
Cycles: 1 



1 1 



Encoding: 

Operation: RR 

(An)<-(A n+ i),n = 0-6 
(A7) <- (AO) 



RRC A 



Function: Rotate Accumulator Right through the Carry flag 

Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit moves 
into the carry flag; the original state of the carry flag moves into the bit 7 position. No other flags are 
affected. 

Example: The Accumulator holds the value 0C5H (11 0001 01 B), and the carry is zero. The instruction, 
RRC A 

leaves the Accumulator holding the value 62 (01 10001 OB) with the carry set. 
Bytes: 1 
Cycles: 1 



Encoding: | 1 | 1 1 



Operation: RRC 

(A n )«-(A„ +1 ),n = 0-( 
(A7) <- (C) 
(C) <r- (AO) 



March 1995 



2-92 



Philips Semiconductors 



1 Family 



80C51 family programmer's guide 
and instruction set 



SETB <bit> 



Function: Set Bit 

Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No 
other flags are affected. 

Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The 
instructions, 

SETB C 
SETB P1.0 

will leave the carry flag set to 1 and change the data output on Port 1 to 35H (001 1 01 01 B). 



SETB C 

Bytes: 1 
Cycles: 1 



110 1 



Encoding: 

Operation: SETB 

(C)*-1 



11 



SETB bit 

Bytes: 2 
Cycles: 1 



Encoding: 

Operation: SETB 

(bit) «- 1 



1 1 1 10 



bit address 



SJMP rel 
Function: 
Description: 



Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Short Jump 

Program control branches unconditionally to the address indicated. The branch destination is computed 
by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC 
twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 
bytes following it. 

The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction, 
SJMP RELADR 

will assemble into location 0100H. After the instruction is executed, the PC will contain the value 0123H. 

(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore, the 
displacement byte of the instruction will be the relative offset (0123H-0102H) = 21 H. Put another way, an 
SJMP with a displacement of 0FEH would be a one-instruction infinite loop.) 



| 1 | o"~o~ 



rel. address 



SJMP 

(PC) «- (PC) + 2 
(PC) <- (PC) + rel 



March 1995 



2-93 



Philips Semiconductors 



ftnrM Famiiv 80051 fami| y Programmer's guide 

80C51 Family and jnstmctjon set 



SUBB A, <src-byte> 



Function: Subtract with borrow 

Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result 
in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C 
otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for 
the previous step in a multiple precision subtraction, so the carry is subtracted from the Accumulator along 
with the source operand.) AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a 
borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. 

When subtracting signed integers OV indicates a negative number produced when a negative value is 
subtracted from a positive value, or a positive result when a positive number is subtracted from a negative 
number. 

The source operand allows four addressing modes: register, direct, register-indirect, or immediate. 

Example: The Accumulator holds 0C9H (11001 001 B), register 2 holds 54H (01010100B), and the carry flag is set. 
The instruction, 

SUBB A,R2 

will leave the value 74H (01110100B) in the Accumulator, with the carry flag and AC cleared but OV set. 

Notice that 0C9H minus 54H is 75H The difference between this and the above result is due to the carry 
(borrow) flag being set before the operation. If the stale of the carry is not known before starting a single 
or multiple-precision subtraction, it should be explicitly cleared by a CLR C instruction 



SUBB A.Rn 
Bytes: 
Cycles: 

Encoding: 



10 1 1 r r r 



Operation: SUBB 

(A)^(A)-(C)-(R n ) 



SUBB A,direct 

Bytes: 2 
Cycles: 1 



10 1 



Encoding: 

Operation: SUBB 

(A) ^ (A) -(C)- 

SUBB A,@Ri 

Bytes: 1 
Cycles: 1 



10 1 



10 1 1 1 i 



Encoding: 

Operation: SUBB 

(A)<-(A)-(C)-(Ri) 



direct address 



SUBB A,#data 



Cycles: 1 



10 1 



10 



Encoding: 

Operation: SUBB 

(A) <- (A) - (C) - (#data) 



immediate data 



March 1995 



2-94 



Philips Semiconductors 



80C51 Family 



80C51 family programmer's guide 
and instruction set 



SWAP A 



Function: Swap nibbles within the Accumulator 

Description: SWAP A interchanges the low- and high-order nibbles (tour-bit fields) of the Accumulator (bits 3-0 and bits 
7-4). The operation can also be thought of as a four-bit rotate instruction. No flags are affected. 



Encoding: 
Operation: 







10 



SWAP 

(A 3 -o)<z> (A 7 . 4 ) 



Example: The Accumulator holds the value 0C5H (1 1 0001 01 B). The instruction, 
SWAP A 

leaves the Accumulator holding the value 5CH (01011100B). 
Bytes: 1 
Cycles: 1 



XCH A,<byte> 



Function: Exchange Accumulator with byte variable 

Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the 

original Accumulator contents to the indicated variable. The source/destination operand can use register, 
direct, or register-indirect addressing. 

Example: R0 contains the address 20H. The Accumulator holds the value 3FH (001 1 1 1 1 1 B). Internal RAM location 
20H holds the value 75H (01 1 1 01 01 B). The instruction, 

XCH A,@R0 

will leave the RAM location 20H holding the values 3FH (001 1 1 1 1 1 B) and 75H (01 1 1 01 01 B) in the 
Accumulator. 



XCH A,Rn 

Bytes: 
Cycles: 

Encoding: 
Operation: 

XCH A,direct 



Cycles: 

Encoding: 
Operation: 

XCH A,@Ri 
Bytes: 
Cycles: 

Encoding: 
Operation: 



1 1 







1 r r r 



XCH 



(A) # (R n ) 



110 



XCH 

(A) # (direct) 



1 1 1 1 i 



XCH 

(A) # ((R|)) 



10 1 



D 



direct address 



March 1995 



2-95 



Philips Semiconductors 



)C51 Family 



80C51 family programmer's guide 
and instruction set 



XCHD A,@Ri 



Function: 
Description: 

Example: 



Bytes: 
Cycles: 

Encoding: 
Operation: 



Exchange Digit 

XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a 
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified 
register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected. 

R0 contains the address 20H. The Accumulator holds the value 36H (001 1011 OB). Internal RAM location 
20H holds the value 75H (01 1 101 01 B). The instruction, 

XCHD A,@R0 

will leave RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in the Accumulator. 
1 



110 1 



1 1 i 



XCHD 
(A3-0)? 



((Ria-o)) 



XRL <dest-byte>,<src-byte> 



Function: 
Description: 



Example: 



Logical Exclusive-OR for byte variables 

^S^Z^^^^M^ between ,he indica,ed variables ' s,orin9 ,he 

The two operands allow six addressing mode combinations. When the destination is the Accumulator, the 
source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct 
address, the source can be the Accumulator or immediate data. 

{Note: When this instruction is used to modify an output port, the value used as the original port data will 
be read from the output data latch, not the input pins.) 

If the Accumulator holds 0C3H (11 00001 1 B) and register holds 0AAH (1 01 01 01 0B) then the instruction, 
XRL A,R0 

will leave the Accumulator holding the value 69H (01 101 001 B). 

When the destination is a directly addressed byte, this instruction can complement combinations of bits in 
any RAM location or hardware register. The pattern of bits to be complemented is then determined by a 
mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at 
run-time. The instruction, 

XRL P1, #0011 0001 B 

will complement bits 5, 4, and of output Port 1 . 



March 1995 



2-96 



fly 





80C51 family programmer's guide 
and instruction set 



XRL A,Rn 

Bytes: 1 
Cycles: 1 



1 



1 I 1 



Encoding: 

Operation: XRL 

(A)<-(A)WR) 
t«j *- i>v <«nj 



XRL 



Bytes: 2 
Cycles: 1 



110 



Encoding: 

Operation: XRL 

(A) <- (A) v (direct) 



10 1 



direct address 



XRL A,@Ri 



1 



Cycles: 1 



110 



Encoding: 

Operation: XRL 

(A)<-(A)v(Ri) 



XRL A,#data 

Bytes: 2 
Cycles: 1 



1 1 i 



110 10 



Encoding: 

Operation: XRL 

(A) <- (A) v #data 



immediate data 



XRL direct,A 
Bytes: 
Cycles: 

Encoding: 



Operation: XRL 

(direct) <- (direct) v (A) 



110 



1 



direct address | 



XRL direct,#data 



Bytes: 



1 1 1 1 



Encoding: 

Operation: XRL 

(direct) <- (direct) v #data 



direct address immediate data 



March 1995 



2-97 



Philips Semiconductors 



- 



80C51 Family 



80C51 family EPROM products 



EPROM PRODUCTS 

Most of the 80C51 derivative products offered by Philips are 
supported with an EPROM version. 

All EPROM products are available in both windowed DIP and OTP 
package configurations. The windowed DIP package allows the 
EPROM to be erased under a strong UV light source, making 
program development easier and faster. The OTP (One Time 
Programmable) version cannot be erased because there is no 
window through which the die could be exposed to UV light. While 
the EPROM can only be programmed once in the OTP package, the 
part costs less than in windowed DIP and therefore offers an 
advantage for those not desiring to use the masked ROM version of 
the part. 

The EPROM products are fully supported on the industry standard 
EPROM programmers. 

Programming the 87C51 

The setup for programming the microcontroller is shown in Figure 1 . 
Note that the part is running with a 4 to 6 MHz oscillator. The clock 
must be running because the device is executing internal address 
and program data transfers during the programming. 

To program the 87C51 , the address of the EPROM location to be 
programmed is applied to ports 1 and 2 as shown in Figure 1 . The 
code byte to be programmed into this location is applied to port 0. 
RST, PSEN, and the pins of ports 2 and 3 specified in Table 1 are 
held at the "Program Code Data" levels specified in the table. The 
ALE/PROG is then pulsed low 25 times to program the addressed 
location. 



Encryption Table 

The encryption table is a feature of the 87C51 , and its derivatives, 
that protects the code from being easily read by anyone other than 
the programmer. The encryption table is 16 to 64 bytes of code, 
depending on the microcontroller, that are exclusive NORed with the 
program code data as it is read out. The first byte is XNORed with 
the first location read, the second with the second read, etc. through 
the sixteenth byte read. The seventeenth byte is XNORed with the 
first byte of the encryption table, the eighteenth with the second, etc. 
and on in sixteen-byte groups. 

After the Encryption table has been programmed the user has to 
know its contents in order to correctly decode the program code 
data. The encryption table itself cannot be read out. 

The encryption table is programmed in the same manner as the 
program memory, but using the "Pgm Encryption Table" levels 
specified in Table 1 . After the encryption table is programmed, 
verification cycles will produce only encrypted information. 

Security Bit 

There are two security bits on the 87C51 that, when set, prevent the 
program data memory from being read out or programmed further. 
To program the security bits, repeat the programming sequence 
using the "Pgm Security Bif levels specified in Table 1 . 

After the first security bit is programmed, further programming of the 
code memory or the encryption table is disabled. The other security 
bit can of course still be programmed. With only security bit one 
programmed, the memory can still be read out for program 
verification. After the second security bit is programmed, it is no 
longer possible to read out (verify) the program memory. 



A0-A7 

i 



pi 

RST 
P3.6 
P3.7 
XTAL2 

XTAL1 




P2.7 
P2.6 







+12.75V 
25 1IXVS PULSES TO GROUND 



A- 
V 



Figure 1. Programming Configuration 



March 1995 



2-98 



Philips Semiconductors 



80C51 Family 80C51 family EPROM products 



Table 1 . EPROM Programming Modes 



MODE 



RST 



PSEN ALE/PROG EAW 



P2.7 



P2.6 



P3.7 



P3.6 



Read signature 



Program code data 



V PP 



Verify code data 



Pgm encryption table 



0* 



Pgm security bit 1 



V PP 



Pgm security bit 2 



0* 



Vpp 1 

' ' 



1 



NOTES: 

1 . "0" = valid low for that pin, "1" = valid high for that pin. 

2. V PP = 12.75 +0.25V. 

3. Vcc = 5V±1 0% during programming and verification. 
* ALE/PROG receives 25 programming pulses while V PP is held at 1 2.75V. Each programming pulse is low for 1 00ms (±1 0ns) and 

minimum of 10ns. 



high for a 



A0-A7 



1 



5 



L 



pi 

RST 
P3.6 
P3.7 
XTAL2 



vss 



87C51 



VCC 
P0 

EAWpp 
ALE/PROG 

P2.7 
P2.6 
P2.0-P2.3 



PGM DATA 



V 



A6-A11 




Program Verification 

If security bit 2 has not been programmed the on-chip program 
memory can be read out for program verification. To verify the 
nts of the program memory, the address of the location to be 
t is applied to ports 1 and 2 as shown in Figure 2. The other pins 
3 held at the "Verify Code Data" levels indicated in Table 1 . The 
3 of the addressed location will appear on port 0. For this 
ition external pull-ups are required on port as shown in Figure 
)te that if the encryption table has been programmed the data 
ented at port will be the exclusive NOR of the program byte 
i a byte from the encryption table. 

Signature Bytes 

The 87C51 contains two signature bytes that can be read and used 
by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87C51 manufactured by 
Philips. 

The signature bytes are read by the same procedure as a normal 
verification of locations 030H and 031 H, except that P3.6 and P3.7 
need to be pulled to a logic low. The values are: 



Figure 2. Program Verification 

(030H) = 1 5H indicates the part is made by Philips 




(031 H) = 90H 


87C451 


92H 


87C51 


94H 


87C552 


96H 


87C550 


97H 


87C52 


99H 


87C654/87C652 


9BH 


87C528 


9CH 


87C592 


9DH 


87C524 


9EH 


87C598 


BOH 


87C575 


B1H 


87C51FA 


B2H 


87C51FB 


B3H 


87C51FC 


B5H 


89CE558 


B6H 


87C576 


BBH 


87C504 


4BH 


87C055 


(060H) FCH 


87C51FC 



March 1995 



2-99 



Philips Semiconductors 



80C51 Family 




EPROM products 



EPROM Erasure 

[he EPROM occurs when the chip is exposed to light with 
elengths shorter than 4000 angstroms. Sunlight and fluorescent 
hting have wavelengths in this range, so exposure to these light 
urces over an extended period of time (about 1 week in sunlight, 
or 3 years in room level fluorescent lighting) could cause inadvertent 
erasure. It is recommended, for this reason, that an opaque label be 
placed over the window. If the part is subject to elevated 
temperatures or an environment where solvents are used, Kapton 
tape (Fluorglas part number 2345-5 or its equivalent) can be used. 

The recommended erasure procedure is to expose the chip to 
ultraviolet light (at 2537 angstroms) to an integrated dose of at least 
1 5W-sec/cm 2 . Exposing the EPROM to an ultraviolet lamp of 
12,000uW/cm 2 rating for 20 to 40 minutes, at a distance of 1 inch, is 
adequate. 

Programming the 87C750, 87C751 and 87C752 

The 87C750, 87C751 and 87C752 are programmed using a 
Quick-pulse programming algorithm that is similar to that used for 
the 87C51 . It differs from the 87C51 in that a serial data stream is 
used to place the 87C751 in the programming mode. 

Figure 3 shows a block diagram of the programming configuration 
for the 87C751 . Port pin P0.2 is used for the programming voltage 
supply input (V PP signal). Port pin P0.1 is used for the program 
(PGM) signal. 

Port 3 accepts the address input for the EPROM location to be 
programmed. Both the high and low components of the eleven-bit 
address are presented to the part through port 3. Multiplexing of the 
address components is performed using ASEL (P0.0). 

Port 1 is used as a bidirectional data bus during programming and 
verify operations. During the programming mode, it accepts the byte 



to be programmed. In the verify mode, it returns the contents of the 
specified address location. 

The X1 pin is the oscillator input and receives the master system 
clock. This clock should be between 1.2 and 6MHz. 

The RESET pin is used to accept the serial data stream that places 
the 87C751 into various programming modes. This partem consists 
of a 10-bit code with the LSB send first. Each bit is synchronized to 
the clock input X1 . 

To program the 87C751 the part must be put into the programming 
mode by presenting the proper serial code (see Table 2) to the 
RESET pin. To do this RESET should be held high for at least two 
machine cycles. Port pins P0.1 and P0.2 will be at VOH as a result 
of this, but they must be driven high prior to sending the serial data 
stream on the RESET pin. The serial data bits can now be 
transmitted over the RESET pin placing the 87C751 into one of the 
programming modes. Following the transmission of the last data bit, 
the reset pin should be held low. 

Next the address information for the location to be programmed is 
placed on Port 3 and ASEL is used to perform the address 
multiplexing. ASEL should be driven high and then Port 3 driven with 
the high-order address bits. ASEL is then driven low, latching the 
high-order bits internally. Port 3 can now be driven with the low 8 
bits of the address, completing the addressing of the location to be 
programmed. 

A high-voltage V PP level is now applied to the V PP input. This sets 
Port 1 as an input port. The data to be programmed to the EPROM 
array should be placed on Port 1 . A series of 25 programming 
pulses is now applied to the PGM pin (P0.1) to program the 
addressed EPROM location. 



87C751 



A0-A10— 
STROBE — 



* P3 - P3 J 
P0.0/ASEL 



PROGRAMMING . 
PULSES 



V PP /V| H VOLTAGE ■ 
SOURCE 



RESET 
CONTROL 
LOGIC 



VCC 
VSS 



P0.1 
P0.2 
XTAL1 

RESET 



1 



Figure 3. Programming Configuration 



March 1995 



2-100 



Philips Semiconductors 



80C51 Family 80C51 family EPROM products 



Table 2. 87C750, 87C751 , and 87C752 Serial Codes 



OPERATION 


SERIAL CODE 


P0.1 (PGM/) 


P0.2(V PP ) 


Program user EPROM 


296H 


-* 




Vrp 


Verify user EPROM 


296H 


V lH 




VlH 


Program key EPROM 


292H 


_» 




V PP 


Verify key EPROM 


292H 


V|H 




VlH 


Program security bit 1 


29AH 




Vpp 


Program security bit 2 


298H 




Vpp 


Verify security bits 


9QAU 


V, H 


V|H 


Read signature bytes 


294H 


V,H 


Vih 



NOTE: 

* Pulsed from V| H to V| L and returned to V| H . 



Program Verification 

The EPROM array can be verified by placing the part in the 
programming mode as described above and forcing the V PP pin to 
the V h level. Four machine cycles after addressing a location the 
contents of the addressed location will appear on Port 1 . 

87C750, 87C751 and 87C752 Signature Bytes 

The signature bytes for the 87C750, 87C751 and 87C752 are read 
differently and are in different locations than those on the 87C51 . 
Due to its reduced pin count, the part has to be put into "Signature 
Byte Read Mode" by placing a 1 0-bit serial data stream on the Reset 
pin. The proper code and the conditions of P0.1 and P0.2, for this 
mode, are shown in Table 2. 

Once the part has been placed into the Signature Byte Read Mode, 
the signature bytes can be read by the same procedure as a normal 
verification of locations 01 EH and 01 FH. The values are: 

01 EH = 15H indicates the part is made by Philips 
01 FH = 91H-87C751 
01 FH = 95H-87C752 



Programming Features 

The 87C751 has all of the special programming features 
incorporated within its EPROM array that the 87C51 has. It has an 
encryption key table and two security bits. These function exactly as 
they do in the 87C51 . They are programmed or verified by sending 
the proper code over the RESET pin (see Table 2) and then 
following the 87C751 programming procedure as described 
previously. 

Erasure Characteristics 

The erasure procedure is exactly the same as that described for the 
87C51. 



March 1995 



2-101 



2-102 



Philips Semiconductors 



Section 3 

80C51 Family Derivatives 



80C51-Based 

8-Bit Microcontrollers 



80C31/80C51/87C51 

83C51FA/83C51FB/ 
83C51FC/80C51FA 

S7C51FA/87C51FB 

87C51FC 

80CL31/80CL51 

87L51FA/87L51FB 

80C32/87C52 

80C52/80C54/80C58 

87C54/87C58 

83C145; 83C845 
83C055; 87C0S5 

80CL410/83CL410 

80C451/83C451/87C451 
80C453/B3C453/87C453 
83C508/87C508 
P83C524 

87C524 




3-3 



CMOS single-chip 8-bit microcontrollers 3-25 

CMOS single-chip 8-bit microcontrollers 3-61 

CMOS single-chip 8-bit microcontroller 3-89 

Low-voltage single-chip 8-bit microcontrollers 3-117 

CMOS single-chip 3.0V 8-bit microcontrollers 3-150 

CMOS single-chip 8-bit microcontrollers 3-1 66 

CMOS single-chip 8-bit microcontrollers 3-1 88 

d 8-bit microcontrollers 3-215 



80C528/83C528 
87C528 



P8xCE528 

80C550/83C550/87C550 



Microcontrollers for TV and video (MTV) 3-236 

Low voltage/low power single-chip 

8-bit microcontroller with l 2 C 3-270 

CMOS single-chip 8-bit microcontrollers 3-292 

CMOS single-chip 8-bit microcontrollers 3-311 

CMOS single-chip 8-bit microcontrollers 3-334 

8-bit microcontroller 3-351 

CMOS single-chip 8-bit microcontroller 3-372 

CMOS single-chip 8-bit microcontrollers 3-392 

CMOS single-chip 8-bit microcontroller 3-410 

8-bit microcontroller with EMC 3-430 

CMOS single-chip 8-bit microcontroller 

with A/D and watchdog timer 3-450 

8XC552/562 overview 3-473 

8XC552 OVERVIEW 3-473 

83C562 OVERVIEW 3-473 

Differences From the 80C51 3-473 

Program Memory 3-473 

Data Memory 3-473 

Special Function Registers 3-473 

Timer T2 3-474 

Timer T3, The Watchdog Timer 3-480 

Serial I/O 3-481 

Reset Circuitry 3-512 

Interrupts 

I/O Port Structure 

Port 1 Operation 

Port 5 Operation 

Pulse Width Modulated Outputs 3-517 

Analog-to-Digital Converter 3-517 

Power Reduction Modes 3-523 

Memory Organization 3-525 



3-513 
3-517 
3-517 
3-517 



80C552/83C552 



87C552 



P83CE558/P80CE558/ 
P89CE558 

P83CE559/P80CE559 



Single-chip 8-bit microcontroller with 10-bit A/D, 

capture/compare timer, high-speed outputs, PWM 3-530 

Single-chip 8-bit microcontroller with 10-bit A/D, 

capture/compare timer, high-speed outputs, PWM 3-550 

Single-chip 8-bit microcontroller 3-571 

Single-chip 8-bit microcontroller 3-640 

Single-chip 8-bit microcontroller with 8-bit A/D, 

capture/compare timer, high-speed outputs, PWM 3-708 



3-1 



Philips Semiconduntors 



80C51 Family Derivatives 



Section 3 



CONTENTS (Continued) 



80C575/83C575/87C575 
83CS76/87C576 
P80CL580; P83CL580 



P8xCE598 

80C652/83C652 

87C652 

83C654 

87C654 

83CE654 

83C748/87C748 

83C749/87C749 

TPM749 

83C750/87C750 

83C751/87C751 

83C752/87C752 

83C754/87C754 

TPM754 

P83CL781;P83CL782 

80C851/83C851 



CMOS single-chip 8-bit microcontrollers 3-721 

CMOS single-chip 8-bit microcontrollers 3-756 

Low voltage 8-bit microcontrollers 3-798 

8-bit microcontroller with on-chip CAN 3-869 

8-bit microcontroller with on-chip CAN 3-969 

CMOS single-chip 8-bit microcontrollers 3-992 

CMOS single-chip 8-bit microcontroller 3-1010 

CMOS single-chip 8-bit microcontroller 3-1030 

CMOS single-chip 8-bit microcontroller 3-1048 

CMOS single-chip 8-bit microcontroller 

with Electromagnetic Compatibility improvements 3-1069 

CMOS single-chip 8-bit microcontrollers 3-1083 

CMOS single-chip 8-bit microcontrollers 3-1 095 

Microcontroller with TrackPoint™ microcode from IBM ... 3-1110 

CMOS single-chip 8-bit microcontrollers 3-1119 

CMOS single-chip 8-bit microcontrollers 3-1129 

CMOS single-chip 8-bit microcontroller with A/D.PWM .. 3-1147 

CMOS single-chip 8-bit microcontrollers 3-1165 

Microcontroller with TrackPoint™ microcode from IBM ... 3-1187 

Low voltage 8-bit microcontrollers 3-1195 

CMOS single-chip 8-bit microcontroller 

with on-chip EEPROM 3-1251 



3-2 



Philip. 



Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



1/80C51/87C51 



DESCRIPTION 

The Philips 80C31/80C51/87C51 is a high-performance 
microcontroller fabricated with Philips high-density CMOS 
technology. The CMOS 8XC51 is functionally compatible with the 
NMOS 8031/8051 microcontrollers. The Philips CMOS technology 
combines the high speed and density characteristics of HMOS with 
the low power attributes of CMOS. Philips epitaxial substrate 
minimizes latch-up sensitivity. 

The 8XC51 contains a 4k x 8 ROM (80C51) EPROM (87C51), a 128 
x 8 RAM, 32 I/O lines, two 1 6-bit counter/timers, a five-source, 
two-priority level nested interrupt structure, a serial I/O port for either 
multi-processor communications, I/O expansion or full duplex UART, 
and on-chip oscillator and clock circuits. 

In addition, the device has two software selectable modes of power 
reduction — idle mode and power-down mode. The idle mode freezes 
the CPU while allowing the RAM, timers, serial port, and interrupt 
system to continue functioning. The power-down mode saves the 
RAM contents but freezes the oscillator, causing all other chip 
functions to be inoperative. 

FEATURES 

• 8031/8051 compatible 

- 4k x 8 ROM (80C51) 

- 4k x 8 EPROM (87C51) 

- ROMIess(80C31) 

- 128x8 RAM 

- Two 1 6-bit counter/timers 

- Full duplex serial channel 

- Boolean processor 

• Memory addressing capability 

- 64k ROM and 64k RAM 

• Power control modes: 

- Idle mode 

- Power-down mode 

• CMOS and TTL compatible 

• Five speed ranges at V cc = 5V 

- 12MHz 

- 16MHz 

- 24MHz 

- 33MHz 



PIN CONFIGURATIONS 



• Five package styles 

• Extended temperature ranges 

• OTP package available 



pi.o[T 
pi.i|T 

P,. 2 [3 



P1.3[7 
P1.4[T 
P1.5f? 
P1.6|T 

pu|T 
rst[? 

RxD/P3.o[lO 
TXD/P3.1 [n 
TNTWP3.2Q2 
INTT/P3.3Q3 
T0/P3.4Q4 
T1/P3.5Q5 
WR7P3.6Q6 
RC/P3.7Q7 
XTAL2Qi 
XTAL1 Q| 



CERAMIC 

AND 
PLASTIC 
DUAL 
IN-LINE 
PACKAGE 



u 

18 



§ v cc 

39] P0.0/AD0 
38] P0.1/AD1 
37] P0.2/AD2 
36| P0.3/AD3 
36] P0.4/AD4 
34] P0.S/AOS 
33] P0.6/AD6 
32] P0.7/AD7 
3l] EAVVpp 
30] ALE/PROG 
29] PSETJ 
28] P2.7/A15 
27] P2.6/A14 
26] P2 5/A13 
25] P2.4/A12 
24] P2.3/A11 
23] P2.2/A10 
22] P2.1/A9 
2l] P2.0/A8 



1 40 

_□ Q. 



CERAMIC 
AND 

PLASTIC 
LEAD 
CHIP 

CARRIER 



□ 29 




SEE PAGE 3-6 FOR QFP AND LCC PIN FUNCTIONS. 



SU0OOO1 



1996 Aug 16 



3-3 



853-0169 17187 



Philips Semiconductors 





Product specification 




CMOS single-chip 8-bit microcontrollers 


8 




ORDERING INFORMATION 






EPROM 


DRAWING 
NUMBER 


PHILIPS NORTH AMERICA 


ROMIess 


ROM 


□RAWINu 
NUMBER 


TFMPFRATURE RANGE °C 
AND PACKAGE 1 


MHz 


SC87C51CCF40 


0590B 








to +70, Ceramic Dual In-line Package, UV 


3.5 to 12 


SC87C51CCK44 


1472A 








to +70, Ceramic Leaded Chip Carrier, UV 


3.5 to 12 


SC87C51CCN40 


SOT129-1 


SC80C31 BCCN40 


SC80C51 BCCN40 


SOT129-1 


to +70, Plastic Dual In-line Package, OTP 


3.5 to 12 


SC87C51CCA44 


SOT187-2 


SC80C31BCCA44 


SC80C51BCCA44 


SOT187-2 


to +70, Plastic Leaded Chip Carrier, OTP 


3.5 to 12 


SC87C51CCB44 


SOT307-2 


SC80C31 BCCB44 


SC80C51BCCB44 


SOT307-2 


to +70, Plastic Quad Flat Pack, OTP 


3.5 to 12 


SC87C51ACF40 


0590B 








-40 to +85, Ceramic Dual In-line Package, UV 


3.5 to 12 


SC87C51ACN40 


SOT129-1 


SC80C31BACN40 


SC80C51 BACN40 


SOT129-1 


-40 to +85, Plastic Dual In-line Package, OTP 


3.5 to 12 


SC87C51ACA44 


SOT187-2 


SC80C31 BACA44 


SC80C5 1 BACA44 


SOT187-2 


-40 to +85, Plastic Leaded Chip Carrier, OTP 


3.5 to 12 


SC87C51ACB44 


SOT307-2 


SC80C31 BACB44 


SC80C51BACB44 


SOT307-2 


-40 to +85, Plastic Quad Flat Pack, OTP 


3.5 to 12 


SC87C51CGF40 


0590B 








to +70, Ceramic Dual In-line Package, UV 


3.5 to 16 


SC87C51CGK44 


1472A 








to +70, Ceramic Leaded Chip Carrier, UV 


3.5 to 16 


SC87C51CGN40 


SOT129-1 


SC80C31 BCGN40 


SC80C51 BCGN40 


SOT129-1 


to +70, Plastic Dual In-line Package, OTP 


3.5 to 16 


SC87C51CGA44 


SOT187-2 


SC80C31 BCGA44 


SC80C51 BCGA44 


SOT1 87-2 


to +70, Plastic Leaded Chip Carrier, OTP 


3.5 to 16 


SC87C51CGB44 


SOT307-2 


SC80C31BCGB44 


SC80C51 BCGB44 


SOT307-2 


to +70, Plastic Quad Flat Pack, OTP 


3.5 to 16 


SC87C51AGF40 


0590B 








-40 to +85, Ceramic Dual In-line Package, UV 


3.5 to 16 


SC87C51AGN40 


SOT129-1 


SC80C31BAGN40 


SC80C51 BAGN40 


SOT129-1 


-40 to +85, Plastic Dual In-line Package, OTP 


3.5 to 16 


SC87C51AGA44 


SOT187-2 


SC80C31 BAGA44 


SC80C51 BAGA44 


SOT187-2 


-40 to +85, Plastic 


.eaded Chip Carrier, OTP 


3.5 to 16 


SC87C51AGB44 


SOT307-2 


SC80C31BAGB44 


SC80C51 BAGB44 


SOT307-2 


-40 to +85, Plastic 


3uad Flat Pack, OTP 


3.5 to 16 






































SC87C51CPF40 


0590B 










to +70, Ceramic C 


ual In-line Package, UV 


3.5 to 24 


SC87C51CPK44 


1472A 








to +70, Ceramic Leaded Chip Carrier, UV 


3.5 to 24 


SC87C51CPN40 


SOT129-1 


SC80C31 BCPN40 


SC80C51 BCPN40 


SOT129-1 


Oto +70, Plastic Dual In-line Package, OTP 


3.5 to 24 


SC87C51CPA44 


SOT187-2 


SC80C31 BCPA44 


SC80C51 BCPA44 


SOT187-2 


to +70, Plastic Leaded Chip Carrier, OTP 


3.5 to 24 
















SC87C51APF40 


0590B 








-40 to +85, Ceramic Dual In-line Package, UV 




SC87C51APN40 


SOT129-1 


SC80C31 BAPN40 


SC80C51 BAPN40 


SOT129-1 


— W to +85, Plastic Dual In-line Package, OTP 


3.5 to 24 


SC87C51APA44 


SOT187-2 


SC80C31 BAPA44 


SC80C51 BAPA44 


SOT1 87-2 


-40 to +85, Plastic Leaded Chip Carrier, OTP 


3.5 to 24 












































SC87C51CYF40 


0590B 









to +70, Ceramic Dual In-line Package, UV 


3.5 to 33 


SC87C51CYK44 


1472A 








to +70, Ceramic Leaded Chip Carrier, UV 


3.5 to 33 


SC87C51CYN40 


SOT129-1 


SC80C31 BCYN40 


SC80C51 BCYN40 


SOT129-1 


to +70, Plastic Dual In-line Package, OTP 


3.5 to 33 


SC87C51CYA44 


SOT187-2 


SC80C31 BCYA44 


SC80C51 BCYA44 


SOT187-2 


to +70, Plastic Leaded Chip Carrier, OTP 


3.5 to 33 



















2. SOT311 replaced by SOT307-2. 



1996 Aug 16 



3-4 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 
, 



ORDERING INFORMATION (Continued) 



PHILIPS 


ROMIess 
(ORDER NUMBER) 


ROMIess 
(MARKING NUMBER) 


ROM 


DRAWING 
NUMBER 


TEMPERATURE RANGE °C 
AND PACKAGE 1 


Freq 
MHz 


























PCB80C31-2N 


PCB80C31BH2-12P 


PCB80C51BH-2P 


SOT129-1 


to +70, Plastic Dual In-line Package, OTP 


0.5 to 12 


PCB80C31-2 A 


PCB80C31BH2-12WP 


PCB80C51 BH-2WP 


SOT187-2 


to +70, Plastic Leaded Chip Carrier, OTP 


0.5 to 12 




PCB80C31BH2-12H 


PCB80C51 BH-2H 


SOT307-2 2 


to +70, Plastic Quad Flat Pack, OTP 


0.5 to 12 























































































PCB80C31-3N 


PCB80C31BH3-16P 


PCB80C51 BH-3P 


SOT129-1 


to +70, Plastic Dual In-line Package, OTP 


1.2 to 16 


PCB80C31-3A 


PCB80C31BH3-16WP 


PCB80C51 BH-3WP 


SOT187-2 


to +70, Plastic Leaded Chip Carrier, OTP 


1.2 to 16 




PCB80C31BH3-16H 


PCB80C51BH-3H 


SOT307-2 2 


to +70, Plastic Quad F 


lat Pack, OTP 


1.2to16 
















PCF80C31-3N 


PCF80C31BH3-16P 


PCF80C51 BH-3P 


SOT129-1 


-40 to +85, Plastic Dual In-line Package, OTP 


1.2 to 16 


PCF80C31-3A 


PCF80C31BH3-16WP 


PCF80C51 BH-3WP 


SOT187-2 


-40 to +85, Plastic Leaded Chip Carrier, OTP 


1.2 to 16 




PCF80C31BH3-16H 


PCF80C51 BH-3H 


SOT307-2 2 


-40 to +85, Plastic Quad Flat Pack, OTP 


1.2 to 16 




PCA80C31BH3-16P 


PCA80C51BH-3P 


SOT129-1 


-40 to +125, Plastic Dual In-line Package 


1.2 to 16 




PCA80C31BH3-16WP 


PCA80C51 BH-3WP 


SOT187-2 


-40 to +125, Plastic Leaded Chip Carrier 


1.2 to 16 


























PCB80C31-4 N 


PCB80C31BH4-24P 


PCB80C51BH-4P 


SOT1 29-1 


to +70, Plastic Dual In-line Package, OTP 


1.2 to 24 


PCB80C31-4A 


PCB80C31BH4-24WP 


PCB80C51 BH-4WP 


SOT187-2 


to +70, Plastic Leaded Chip Carrier, OTP 


1.2 to 24 




PCB80C31BH4-24H 


PCB80C51 BH-4H 


SOT307-2 2 


to +70, Plastic Quad Flat Pack, OTP 


1.2 to 24 














PCF80C31-4 N 


PCF80C31BH4-24P 


PCF80C51BH-4P 


SOT129-1 


-40 to +85, Plastic Dual In-line Package, OTP 


1 .2 to 24 


PCF80C31-4 A 


PCF80C31BH4-24WP 


PCF80C51 BH-4WP 


SOU 87-2 


-40 to +85, Plastic Leaded Chip Carrier, OTP 


1 .2 to 24 




PCF80C31BH4-24H 


PCF80C51BH-4H 


SOT307-2 2 


-40 to +85, Plastic Leaded Chip Carrier, OTP 


1.2 to 24 


















































PCB80C31-5N 


PCB80C31BH5-30P 


PCB80C51BH-5P 


SOT129-1 


to +70, Plastic Dual In-line Package 


1.2 to 33 


PCB80C31-5A 


PCB80C31 BH5-30WP 


PCB80C51 BH-5WP 


SOT1 87-2 


to +70, Plastic Leaded Chip Carrier 


1.2 to 33 


PCB80C31-5B 


PCB80C31BH5-30H 


PCB80C51 BH-5H 


SOT307-2 2 


to +70, Plastic Quad Flat Pack 


1 .2 to 33 



1996 Aug 16 



3-5 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80C31/80C51/87C51 



CERAMIC AND PLASTIC LEADED CHIP CARRIER 
PIN FUNCTIONS 



NC* 

P1.0 
P1.1 
P1.2 

PI .5 
PI .6 
P1.7 
RST 

P3.0/RXD 
NC* 

P3.1/TXD 
P3.2/INT5 
P3.3/INTT 



■ DO NOT CONNECT 



6 1 

A-E- 


40 

n 








□ 39 


LCC 












U 


u 




18 


28 





16 
17 



28 n 

27 P2.3/A11 

28 P2.4/A12 

29 P2.5/A13 

30 P2.6/A14 



Function 

P2.7/A15 
PSER 
ALE/PROG 
NC* 

ES/Vpp 

P0.7/AD7 

P0.6/AD6 

P0.5/AD5 

P0.4/AD4 



42 P0.1/AD1 

43 P0.0/AD0 

44 V CC 



PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 




Pin 


Function 


Pin 




Pin 


Function 




PI .5 


16 


Vss 


31 


P0.6/AD6 


2 


P1.6 


17 


NC* 


32 


P0.5/AD5 


3 


P1.7 


18 


P2.0/A8 


33 


P0.4/AD4 


4 


RST 


19 


P2.1/A9 


34 


P0.3/AD3 


5 


P3.0/P.XD 


20 


P2.2/A10 


35 


P0.2/AD2 


6 


NC* 


21 


P2.3/A11 


36 


P0.1/AD1 


7 


P3.1/TXD 


22 


P2.4/A12 


37 


PO.OZADO 


8 


P3.2/IRT0" 


23 


P2.5/A13 


36 


Vcc 


9 


P3.3/IRTT 


24 


P2.6/A14 


39 


NC* 


10 


P3.4/T0 


25 


P2.7/A15 
PSER 


40 


P1.0 


11 


P3.5/T1 


26 


41 


P1.1 


12 


P3.6/WR 


27 


ALE/PROG 


42 


P1.2 


13 


P3.7/HD 


28 


NC* 


43 


P.13 


14 


XTAL2 


29 


EAWpp 


44 


PI .4 


15 


XTAL1 


30 P0.7/AD7 







* DO NOT CONNECT 



V C C v S s 



X 



RST 
EATVpp 
PSER ■ 



Cfl 


ALE FTOE 


z 






o 


RxD — *■ 




5 


TxD-« — 




z 

5 


INTO — » 




LL 
> 


IT-JTT — 


t— 


tr 


TO — * 


x~ 

c 


< 
□ 


T1 ► 


c 


z 








fro-* — 





ADDRESS AND 
DATA BUS 



ADDRESS BUS 




1996 Aug 16 



3-6 



Philips Semiconductors 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



Product specification 



BLOCK DIAGRAM 



vcc j 
vssl 





B 




ACC 




REGISTER 











RAM ADOR 

EGIS — 

77 



PORT 2 
DRIVERS 



PORTO 
LATCH 



IE 



PSbN-*-] — 
ALE/PHOG*-!-. 
EAWpp— 1-« 
RST— L» 



TIMING 
AND 
CONTROL 



O n: 

§1 




STACK 
POINTER 



PCON 


SCON 


TMOD 


TCON 




THO 


TLO 


TH1 


TL1 










SBUF 


IE 


IP 


INTERRUPT, SERIAL 
PORT AND TIMER BLOCKS 



L XTAL1 



-HOI—" 



H 



V 



PORT! 
LATCH 



PORT 1 
DRIVERS 



PROGRAM 
COUNTER 



I 



PORT 3 
LATCH 



HHf 



I 



PORT 3 
DRIVERS 



f 



P3.0-P3.7 











1996 Aug 16 



3-7 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



PIN DESCRIPTION 





PIN NO. 






MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAME AND FUNCTION 




20 


22 


16 


I 


Ground: 0V reference. 


V C C 


40 


44 


38 


I 


Power Supply: This is the power supply voltage for normal, idle, and power-down 
operation. 


PO.0-0.7 


39-32 


43-36 


37-30 


I/O 


Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to 
them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data memory. In 
this application, it uses strong internal pull-ups when emitting 1s. Port also outputs the 
code bytes during program verification in the 87C51 . External pull-ups are required during 
program verification. 


P1.0-P1.7 


1-8 


2-9 


40-44, 
1-3 


I/O 


Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As 
inputs, port 1 pins that are externally pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l| L ). Port 1 also receives the low-order address 
byte during program memory verification. 


P2.0-P2.7 


21-28 


24-31 


18-25 


I/O 


Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As 
inputs, port 2 pins that are externally being pulled low will source current because of the 
internal pull-ups. (See DC Electrical Characteristics: l| L ). Port 2 emits the high-order 
address byte during fetches from external program memory and during accesses to 
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it 
uses strong internal pull-ups when emitting 1 s. During accesses to external data memory 
that use 8-bit addresses (MOV @ Ri), port 2 emits the contents of the P2 special function 
register. 


P3.0-P3.7 
RST 


10-17 

10 
11 

12 
13 
14 
15 
16 
17 

9 


11, 
13-19 

11 
13 
14 
15 
16 
17 
18 
19 

10 


5, 
7-13 

5 
7 

8 

9 
10 
11 
12 
13 

4 


I/O 

I 



I 
I 
1 
1 

o 
o 

1 


Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1 s 

written to them are pulled high by the internal pull-ups and can be used as inputs. As 

inputs, port 3 pins that are externally being pulled low will source current because of the 

pull-ups. (See DC Electrical Characteristics: IjJ. Port 3 also serves the special features of 

the 80C51 family, as listed below: 

RxD (P3.0): Serial input port 

TxD (P3.1): Serial output port 

INTO (P3.2): External interrupt 

INTT (P3.3): External interrupt 

TO (P3.4): Timer external input 

T1 (P3.5): Timer 1 external input 

WH (P3.6): External data memory write strobe 

RD~ (P3.7): External data memory read strobe 

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to V ss permits a power-on reset using only an external 
capacitor to Vqc- 


ALE/PROG 


30 


33 


27 


I/O 


Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the 
address during an access to external memory. In normal operation, ALE is emitted at a 
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. 
Note that one ALE pulse is skipped during each access to external data memory. This pin is 
also the program pulse input (PROG) during EPROM programming. 


P5EFJ 


29 


32 


26 


O 


Program Store Enable: The read strobe to external program memory. When the device is 
executing code from the external program memory, PSEN is activated twice each machine 
cycle, except that two PSEN activations are skipped during each access to external data 
memory. PSEN is not activated during fetches from internal program memory. 


EATVpp 


31 


35 


29 


1 


External Access Enable/Programming Supply Voltage: EA" must be externally held low 
to enable the device to fetch code from external program memory locations 0000H to 
0FFFH. If EA" is held high, the device executes from internal program memory unless the 
program counter contains an address greater than 0FFFH. This pin also receives the 
12.75V programming supply voltage (V PP ) during EPROM programming. 


XTAL1 


19 


21 


15 


1 


Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 


XTAL2 


18 


20 


14 


O 


Crystal 2: Output from the inverting oscillator amplifier. 



1996 Aug 16 



3-8 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



Table 1. 80C52/80C54/80C58 Special Function Registers 




CVI1DAI 

SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRESS, SYMBOL 
MSB 








RT FUNCTION 

LSB 


RESET 
VALUE 


ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


OOH 


AUXR# 


Auxiliary 


8EH 


— 


— 






- 






AO 


xxxxxxxOB 


AUXR1# 


Auxiliary 1 (Note 2) 


A2H 


— 








WUPD 






DPS 


xxxxOOxOB 


B* 

DPTR: 
DPH 
DPL 


B register 

Data Pointer (2 bytes) 
Data Pointer High 
Data Pointer Low 


FOH 

83H 
82H 


F7 


M 

F6 


F5 F4 


F3 








FO 


OOH 
OOH 








AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 




It 


Interrupt Enable 


A8H 


EA 


EC 


ET2 


ES 


ET1 


EX1 


ETO 


EXO 


OOH 








BF 


BE 


BD 


BC 


BB 


BA 


B9 


B8 




ID* 


Interrupt Priority 


Don 






PT2 


PS 


PT1 


PX1 


PTO 


PXO 


XUUUUUUUB 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




IPH# 


Interrupt Priority High 


B7H 






PT2H 


PSH 


PT1H 


PX1H 


PTOH 


PXOH 


X0000000B 








87 


86 


85 


84 


83 


82 


81 


80 




PO* 


PortO 


80H 


AD7 


AD6 


AD5 


AD4 


AD3 


AD2 


AD1 


ADO 


FFH 








97 


96 


95 


94 


93 


92 


91 


90 






pom 

Port 2 


90H 










- | T2EX 


T2 


FFH 






A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 




P2* 


AOH 


AD15 


AD14 


AD13 


AD12 


AD11 


AD10 


AD9 


AD8 


FFH 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




P3* 


Port 3 


BOH 


ED 


WR 


T1 


TO 


INTT 


INTO 


TxD 


RxD 


FFH 


























PCON* 1 


Power Control 


87H 


SM0D1 


SMODO 






GF1 


GFO 


PD 


IDL 


OOxxOOOOB 








D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 




PSW* 


Program Status Word 


DOH 


CY 


AC 


FO 


RS1 


RSO 


OV 


- 


P 


OOH 


SADDR# 
SADEN# 


Slave Address 
Slave Address Mask 


A9H 
B9H 




















OOH 
OOH 


SBUF 


Serial Data Buffer 


99H 


9F 


9E 


9D 


9C 


9B 


9A 


99 


98 


xxxxxxxxB 


SCON* 


Serial Control 


98H 


SMO/FE 


SM1 


SM2 


REN 


TBS 


RB8 




Rl 


OOH 


SP 


Stack Pointer 


81H 


8F 


8E 


8D 


8C 


8B 


8A 


89 


88 


07H 


TCON* 


Timer Control 


88H 


TF1 


TR1 


TFO 


TRO 


IE1 


tn 


IE0 


ITO 


OOH 








CF 


CE 


CD 


CC 


CB 


CA 


C9 


C8 




T2MOD# 


Timer 2 Mode Control 


C9H 
















T20E 


DCEN 


xxxxxxOOB 


THO 
TH1 
TLO 
TL1 


Timer High 
Timer High 1 
Timer Low 
Timer Low 1 


8CH 
8DH 
8AH 
8BH 










OOH 
OOH 
OOH 
OOH 










TMOD 


Timer Mode 


89H 


GATE 


c/r 


M1 


MO 


GATE 


c/r 


M1 


MO 


OOH 



* SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 
- Reserved bits. 

1 . Reset value depends on reset source. 

2. Available only on SC80C51 . 



1996 Aug 16 



3-9 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input 
inverting amplifier. The pins can 
oscillator, as shown in the logic 

To drive the device f 
driven while XTAL2 
on the duty cycle of the external 




irce, XTAL1 should be 
There are no requirements 
signal, because the input to 



the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 



IDLE MODE 

CPU puts itself to sleep while all of the on-chip 
active. The instruction to invoke the idle mode is the 
last instruction executed in the normal operating mode before the 
idle mode is activated. The CPU contents, the on-chip RAM, and all 
of the special function registers remain intact during this mode. The 
idle mode can be terminated either by any enabled interrupt (at 
which time the process is picked up at the interrupt service routine 
and continued), or by a hardware reset which starts the processor in 
the same manner as a power-on reset. 



RESET 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-up reset, the RST pin must be high long 
enough to allow the oscillator time to s 
milliseconds) plus two machine cycles. 



POWER-DOWN MODE 

In the power-down mode, the oscillator is stopped and the 
instruction to invoke power-down is the last instruction executed. 
Only the contents of the on-chip RAM are preserved. A hardware 
reset is the only way to terminate the power-down mode, the control 



bits for the reduced power 
PCON. 

Table 2 shows the state of 
modes. 

■■ 




are in the special function register 



ports during low current operating 



Table 2. External Pin Status During Idle and Power-Down Modes 



MODE 


PROGRAM MEMORY 


ALE 


PSEN 


PORTO 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 










Data 


Data 


Data 


Internal 








Data 


Power-down 


External 








Float 


Data 


Data 


Data 



ROM CODE SUBMISSION 

When submitting ROM code for the 80C51 , the following must be specified: 

1 . 4k byte user ROM data 

2. 64 byte ROM encryption key (SC80C51 only) 

3. ROM security bits (SC80C51 onlvl. 



ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


0000H to OFFFH 





DATA 


7:0 


User ROM Data 


1000Hto101FH 


KEY 


7:0 


ROM Encryption Key 


1020H 


SEC 





ROM Security Bit 1 


1020H 


SEC 


1 


ROM Security Bit 2 







Security Bit 1 : When programmed, this bit has two effects on masked ROM parts: 

1 . External MOVC is disabled, and 

2. EA# is latched on Reset. 

Security Bit 2: When programmed, this bit inhibits Verify User ROM. 



1996 Aug 16 



3-10 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit 



80C31/80C51/87C51 



Electrical Deviations from Commercial Specifications for Extended Temperature Range (87CS1) 

DC and AC parameters not included here are the same as in the commercial temperature range table. 

■ 

DC ELECTRICAL CHARACTERISTICS 

Tam,, = -40°C to +85°C, V c0 = 5V ±1 0%, V ss = 0V (Philips North America SC87C51 ); 
For SC87C51 (33MHz only), T amb = 0°C to +70°C, V cc = 5V +5% 

Tana = -40°C to +85°C, V cc = 5V ±1 0%, V ss = 0V (PCB80C31/51 and PCF80C31/51 Philips Parts Only) 



SYMBOL 




TEST 


LIMITS 


UNIT 


PARAMETER 


CONDITIONS 


MIN 


MAX 


V|L 


Input low voltage, except EA (Philips North America) 




-0.5 


0.2V CC -0.15 


V 


VlL 


Input low voltage, except EA (Philips) 




-0.5 


0.2V cc -0.25 


V 


V,L1 


Input low voltage to EA 




-0.5 


0.2V cc -0.45 


V 


V,H 


Input high voltage, except XTAL1, RST 




0.2V CC +1 


Vcc+05 


V 




Input high voltage to XTAL1 , RST 




0.7V OC +0.1 


Vcc+0.5 


V 




Logical input current, ports 1,2,3 


V| N = 0.45V 




-75 


uA 


\ 


Logical 1-to-0 transition current, ports 1 , 2, 3 


V| N = 2.0V 




-750 


HA 


Ice 


Power supply current: 

Active mode 1 @ 16MHz (Philips PCB80C31/51, PCF80C31/51) 
Active mode @ 12MHz (Philips North America SC87C51) 
Idle mode 2 @ 16MHz (Philips PCB80C31/51, PCF80C31/51) 
Idle mode @ 12MHz (Philips North America SC87C51) 
Power-down mode 3 (Philips PCB80C31/51, PCF80C31/51) 
Power-down mode (Philips North America SC87C51) 


V CC = 4.5-5.5V 




25 
20 
6.5 
5 

75 
50 


mA 
mA 
mA 
mA 
uA 
uA 



1 . The operating supply current is measured with all output pins disconnected; XTAL1 driven with t r = tf = 1 0ns; V||_ = Vss + 0.5V; 
Vih = V C c - 0.5V; XTAL2 not connected; EA = RST = Port = V cc . 

2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t, = tf = 1 0ns; V| L = V ss + 0.5V; 
Vih = V C c " 0.5V; XTAL2 not connected; EA = Port = V cc ; RST = V s 

3. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port = V c0 ; RST = V ss . 

ABSOLUTE MAXIMUM RATINGS 1 2 3 





PARAMETER 


RATING 


UNIT 


Operating temperature under bias 




to +70 or -40 to +85 


°C 


Storage temperature range 


-65 to +150 


°c 


Voltage on EA/V PP pin to Vss 


to +13.0 


V 


Voltage on any other pin to Vss 





-0.5 to +6.5 


V 


Maximum let per I/O pin 





15 


mA 


Power dissipation (based on packag 


e heat transfer limitations, not device power consumption) 


1.5 


W 



NOTES: 

1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V ss unless otherwise 
noted. 



1996 Aug 16 



3-11 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 




DC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or ^J0°C to +85°C, V cc = 5V ±20%, V ss = 0V (PCB80C31/51 and PCF80C31/51) (12, 16, and 24MHz versions) 
T amb = 0°C to +70°C or -40°C to +85°C, V oc = 5V +10%, V ss = 0V (87C51 12, 16, and 24MHz versions) (PCB80C31/51 33MHz version); 
For SC87C51 (33MHz only) T amb = 0°C to +70°C, V cc = 5V ±5% 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


Tl/ni^ All 

TYPICAL 1 


MAX 


V|L 


Input low voltage, except EA' 




-0.5 




0.2V C c-0.1 


V 


V|L1 


Input low voltage to EA" 7 









0.2V cc -0.3 


V 


V|H 


Input high voltage, except XTAL1 , RST 7 




0.2V OC +0.9 




Vcc+0.5 


V 


V|H1 


Input high voltage, XTAL1, RST 7 




0.7V CC 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 3 11 


I l= 1.6mA 2 






0.45 


V 


Voli 


Output low voltage, port 0, ALE, PSEN 11 


Iql = 3.2mA 2 






0.45 


V 


V H 


Output high voltage, ports 1 , 2, 3, ALE, PSEN 3 


Ioh ■ -60uA, 
Ioh = -25fiA 
l OH = -10(iA 


2.4 

0.75V CC 
0.9V CC 






V 
V 

y 


V H1 


Output high voltage (port in external bus mode 




Ioh = -800uA, 

1-,. , ^nrii i A 

'OH — ^3UULIM 

Ioh = -80(iA 


2.4 
0.9V OC 






V 

V 

V 


!, L 


Logical input current, ports 1 , 2, 3 7 




V| N = 0.45V 






-50 


M A 


Itl 


Logical 1 -to-0 transition current, ports 1 , 2, 3 7 




See note 4 






-650 


pA 


lu 


Input leakage current, port 




V|N = V| L or V,h 






±10 


pA 


'cc 


Power supply current: 7 

Active mode @ 12MHz 8 (Philips) 

Active mode @ 12MHz 5 (Philips North America) 

Idle mode @ 12MHz 9 (Philips) 

Idle mode @ 12MHz (Philips North America) 

Power-down mode 10 (Philips and 

Philips North America) 


See note 6 




11.5 

1.3 

3 


18 
19 
4.4 
4 
50 


mA 
mA 
mA 
mA 
pA 


Rrst 


Internal reset pull-down resistor 

(Philips North America) 
(Philips) 




50 
50 




300 


k£2 

ka 




Pin capacitance 12 









10 


PF 



1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the Vols of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 1 0OpF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I l can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs ex ceed th e test conditions. 

3. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the 0.9V C c specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 

5- Iccmax a* other frequencies (for Philips North America parts) is given by: Active mode: Iccmax = 1 .43 X FREQ + 1 .90; 

Idle mode: Iccmax = 0.14 X FREQ +2.31 , where FREQ is the external oscillator frequency in MHz. Iccmax is given in mA. See Figure 8. 

6. See Figures 9 through 1 2 for l cc test conditions. 

7. For Philips North America parts when T amb = -40°C to +85°C or Philips parts when T amb = -40°C to +1 25°C, see DC Electrical 
Characteristics table on previous page. 

8. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t r = t f = 1 0ns; V| L = V ss + 5V- 
Vih = V C c - 0.5V; XTAL2 not connected; EA = RST = Port = V C c- 

9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t r = t f = 10ns; V !L = V ss + 5V- 
Vih = V c c - 0.5V; XTAL2 not connected; EA = Port = V C ci RST = V S s 

10. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA" = Port = V cc ; RST = V S s 

11 . Under steady state (non-transient) conditions, I l must be externally limited as folk 

Maximum l OL per port pin: 1 5mA 

Maximum l OL per 8-bit port: 26mA 
Maximum I l total for all outputs: 

If l 0L exceeds the test condition, V 0L may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

1 2. Pin capacitance for the ceramic Dl P package is 1 5pF maximum. 




1996 Aug 16 



3-12 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80C31/80C51/87C51 



DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) 



SYMBOL 






LIMITS 


UNIT 


PARAMETER 


TEST 
CONDITIONS 


MIN 


TYP 1 


MAX 


V|L 


Input low voltage 


4.5V < V CC < 5.5V 


—0.5 




0.2V cc -O.1 


V 




VlH 


Input high voltage (ports 0, 1 , 2, 3, EA) 




0.2Vcc+0.9 




Vcc+0.5 


V 


V|H1 


Input high voltage, XTAL1, RST 




0.7V CC 




Vcc+0.5 


v 


Vol 


Output low voltage, ports 1 , 2, 3 8 


V C c = 4 5V 
l OL =1-6mA 2 






0.4 


V 


Von 


Output low voltage, port 0, ALE, PS EN ' 7 


V cc = 4.5V 

I — . — Q Omfi2 
|QL = O.tlTlA 






0.4 


V 


w 

VOH 


Output high voltage, ports 1 , 2, 3 3 


V cc = 4.5V 
I O h = -30mA 


V 0C - 0.7 






V 


V OH1 


Outp^uHTkjh^voItage (port in external bus mode), 


V C c = 4.5V 
'oh = -3.2mA 


Vcc -0.7 






V 
















IlL 


Logical input current, ports 1 , 2, 3 


V| N = 0.4V 


-1 




-50 


uA 


ITL 




V| N = 2.0V 






-650 


uA 


Logical 1-to-0 transition current, ports 1 , 2, 3 6 


See note 4 






iu 


Input leakage current, port 


0.45 < V| N < V cc - 0-3 






±10 


uA 


ice 


Power supply current (see Figure 8): 
Active mode @ 1 6MHz 5 
Idle mode @ 16MHz 5 


See note 5 




11.5 
1.3 


32 
5 


MA 

ma 




Power-down mode 


Tamb = to +70°C 
Tamb = ^t0to + 85°C 




3 


50 
75 


pA 
pA 


Rrst 


Internal reset pull-down resistor 




40 




225 


kn 


Cjo 


Pin capacitance 10 (except EA") 








15 


pF 



NOTES: 

1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the V lS of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1 -to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 1 0OpF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Iol can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs exceed the test conditions. 

3. Capacitive loading on ports and 2 may cause the Voh on ALE and PSEN to momentarily fall below the (V C c-0-7) specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 
"lee Figures 9 through 12 for l cc test conditions. 

Active Mode: l C c = 1 -5 x FREQ + 8.0; 
Idle Mode: l cc = 0.14 x FREQ +2.31 ; See Figure 8. 
This value applies to T afnb = 0°C to +7 0°C. Fo r T^t, = -40°C to +85°C, l TL = -750pA. 
.oad capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 
Under steady state (non-transient) conditions, I l must be externally limited as follows: 
Maximum l OL per port pin: 15mA ("NOTE: This is 85°C specification.) 

Maximum l i_ per 8-bit port: 26mA 
Maximum total I l f °r all outputs: 71 mA 
If Iol exceeds the test condition, V l may exceed the related specification. Pins are not guaranteed to 
test conditions. 

ALE is tested to V 0H1 , except when ALE is off then V 0H is the voltage specification. 

I. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF 



i sink curr 



current greater than the listed 




1996 Aug 16 



3-13 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



AC ELECTRICAL CHARACTERISTICS FOR SC87C51 12-33MHZ PHILIPS NORTH AMERICA DEVICES 

Tamb = °°C to +70°C or-40°C to +85°C, V C c = 5V ±10%, V S s » OV (SC87C51 12, 16 and 24MHz versions); 



For SC87C51 (33MHz only 


T amb = = 0°C to +70-C, V CC = 5V ±5% 




SYMBOL 


FIGURE 


PARAMETER 




VARIABLE CLOCK 3 


UNIT 


MIN 


MAX 


1/tcLCL 




Oscillator frequency: Speed Versions 

SC87C51 C 
G 
P 
Y 




3.5 
3.5 
3.5 
3.5 


12 
16 
24 

33 


MHz 
MHz 
MHz 
MHz 


tLHLL 


1 


ALE pulse width 


ZtcLCL^tO 




ns 






Address valid to ALE low 


tci_CL-13 




ns 






Address hold after ALE low 


tCLCL-20 




ns 






ALE low to valid instruction in 




4tcLCL"65 


ns 




1 


ALE low to PSEN low 


tCLCL-13 




ns 






PSEN pulse width 




3ICLCL-20 




ns 


tpLIV 




PSEN low to valid instruction In 






3tcLCL-*5 


ns 


'PXIX 




Input instruction hold after PSEN 







ns 






Input instruction float after PSEN 




tCLCL-10 


ns 


tAVIV 




Address to valid instruction in 




5tcLCL-55 


ns 


tpLAZ 




PSEN low to address float 




10 


ns 


Data Memory 


Irlrh 


2, 3 


RD pulse width 


6tcLCL-100 




ns 


tWLWH 


2, 3 


WR pulse width 


6tcLCL"100 




ns 


*RLDV 


2,3 


RD low to valid data in 




5t C LCL-90 


ns 


tRHDX 


2, 3 


Data hold after RD 







ns 


tRHDZ 


2, 3 


Data float after RD 




2ICLCL-28 


ns 


•lldv 


2,3 


ALE low to valid data in 




8tcLCL-150 


ns 


Wdv 


2,3 


Address to valid data in 




9tCLCL-165 


ns 


'llwl 


2,3 


ALE low to RD or WR low 


3t CLCL - 5 n 


3tcLCL+50 


ns 


'avwl 


2,3 


Address valid to WR low or RD low 


4tcLCL-75 




ns 


tQVWX 


2, 3 


Data valid to WR transition 


tCLCL-20 




ns 


tWHQX 


2,3 


Data hold after WR 


tCLCL-20 




ns 


tRLAZ 


2, 3 


RD low to address float 







ns 


twHLH 


2,3 


HDorWRhightoALE high 


tCLCL-20 


tcLOL+25 


ns 


External Clock 


•CHCX 


5 


High time 


12 




ns 


tcLCX 


5 


Low time 


12 




ns 


tCLCH 


5 


Rise time 




20 


ns 


tcHCL 


5 


Fall time 




20 


ns 



NOTES: 



1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

3. For all Philips North America speed versions only. 

4. Interfacing the 87C51 to devices with float times up to 50ns is permitted. This limited bus contention will not cause damage to port drivers. 



1996 Aug 16 



3-14 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80' 



C31/80C51/87C51 



AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES 

t . -n^fn^ivp v = w +?n°/. u„„ = nu rPHRRnnm/fii poFRnra-i/.s-n 1 . 2. 4 . 5 



SYMBOL 


FIGURE 


PARAMETER 


VARIABLE CLOCK 3 


UNIT 


MIN 


MAX 


1/tCLCL 




Oscillator frequency: Speed Versions 

PCB8031/51 —2 
PCA/PCB/PCF80C31/51 -3 
PCB/PCF80C31/51 -4 
PCB/FB80C31/51 -5 


0,5 
1.2 
1.2 
1.2 


12 
16 
24 

33 


MHz 
MHz 
MHz 
MHz 


Ilhll 


1 


ALE pulse width 


2tr-i r*i —40 




ns 


tAVLL 


1 


Address valid to ALE low 


•CLCL-25 




ns 


tl_LAX 


1 


Address hold after ALE low 


'CLCL-25 




ns 


*LLIV 


1 


ALE low to valid instruction in 




4tci_CL-65 


ns 


tLLPL 


1 


ALE low to PSER low 


tcLCL-25 




ns 


tpLPH 


1 


PSEN pulse width 


3tCLCL-45 




ns 


tpLIV 


1 


PSEN low to valid instruction in 




3tcLOL"60 


ns 


tpxix 


1 


Input instruction hold after PSEN 







ns 


tpxiz 


1 


Input instruction float after PSEN 




tCLCL- 25 


ns 


UUIM 


1 


Address to valid instruction in 




5tcLCL-80 


ns 


tpLAZ 


1 


PSEN low to address float 




10 


ns 


Data Memory 


tRLRH 


2,3 


RD pulse width 


6tcLCL-100 




ns 


*WLWH 


2,3 


WR pulse width 


6tci_CL-100 




ns 


'rldv 


2,3 


RD low to valid data in 




5tcLCL-90 


ns 


tRHDX 


2,3 


Data hold after RD 







ns 


tRHDZ 


2, 3 


Data float after RD 




2t CLCL- 28 


ns 


tuDv 


2,3 


ALE low to valid data in 




8ta_CL-150 


ns 


tAVDV 


2,3 


Address to valid data in 




9tcLCL"165 


ns 


<LLWL 


2, 3 


ALE low to RTJ or WR low 


3tcLCL"50 


3tcLCL+50 


ns 


WWL 


2, 3 


Address valid to WR low or RD low 


4t CLCL- 75 




ns 


tQVWX 


2,3 


Data valid to WR transition 


tCLCL-30 




ns 


tWHQX 


2, 3 


Data hold after WR 


tCLCL-25 




ns 


tRLAZ 


2, 3 


RD low to address float 







ns 


t\A/HLH 


2, 3 


RD or WR high to ALE high 


tcLCL-25 


•CLCL+SS 


ns 


External Clock 


tcHCX 


5 


High time 


15 




ns 


ICLCX 


5 


Low time 


15 




ns 


tdCH 


5 


Rise time 




20 


ns 


tcHCL 


5 


Fall time 




20 


ns 



NOTES: 

1 . Parameters are valid over operating 

3. For all Philips speed versions only. 

4. Interfacing the 80C31/51 to devices with float times up 



ure range unless otherwise specified. 

pF, load capacitance for all other outputs = 80pF. 



drivers. 

5. V C c = 5V ±10% for 33MHz 



not cause damage to port 



1996 Aug 16 



3-15 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) 

Tamb = 0°C to +70°C or -40°C to +85°C, V CC = 5V ±1 0%, V SS = 0V 1 • 2| 3 



SYMBOL 


FIGURE 


PARAMETER 


16MHz CLOCK 


VARIABLE CLOCK 


UNIT 


MIN 


MAX 


MIN 


MAX 


1/tcLCL 


1 


Oscillator frequency 

Speed versions : C, G 






3.5 


16 


MHz 


tLHLL 




ALE pulse width 


85 




2ICLCL-40 






*AVLL 




Address valid to ALE low 


22 




tcLCL-^0 




ns 


t|_LAX 




Address hold after ALE low 


32 




tcLCL-30 




ns 


'lliv 




ALE low to valid instruction in 




150 




■MCLCL- 1 "" 


ns 


'llpl 




ALE low to PSEN low 


32 




tCLCL-30 




ns 


tpLPH 




PSEN pulse width 


142 




3t(XCL-45 




ns 


'PLIV 




PSEN low to valid instruction in 4 




82 




3tcLCL-105 


ns 


tpxix 




Input instruction hold after PSEN 












ns 


tpxiz 




Input instruction float after PSEN 




37 




tcLCL-25 


ns 


tAVIV 




Address to valid instruction in 4 




207 




5tci_CL-105 


ns 


IPLAZ 




PSEN low to address float 




10 




10 


ns 


Data Memory 


'rlrh 


2, 3 


RD pulse width 


275 




6tcLCL-100 




ns 


'WLWH 


2, 3 


WR pulse width 


275 




6tCLCL- 1 00 




ns 


(rldv 


2, 3 


RD low to valid data in 




147 




5t C LCL-165 


ns 


IrHDX 


2, 3 


Data hold after RD 












ns 


'rhdz 


2,3 


Data float after RD 




65 




2tcLCL-60 


ns 


tLLDV 


2,3 


ALE low to valid data in 




350 




8t C LCL-150 


ns 


Wov 


2,3 


Address to valid data in 




397 




9tcLCL-165 


ns 


tLLWL 


2,3 


ALE low to RD or WR low 


137 


239 


3tcLCL-50 


3t CL CL+50 


ns 




2, 3 


Address valid to WR low or RD low 


122 




4t C LCL-130 




ns 


tavwx 


2,3 


Data valid to WR transition 


13 




tcLCL-50 




ns 


tWHQX 


2,3 


Data hold after WR 


13 




tCLCL-50 




ns 


toVWH 


3 


Data valid to WR high 


287 




7t CLCL -150 




ns 


tRLAZ 


2,3 


RD low to address float 












ns 


'WHLH 


2,3 


RD or WR high to ALE high 


23 


103 


tCLCL-40 


tcLCL+40 


ns 


External Clock 


'CHCX 


5 




20 




20 


tcLCL-tCLCX 


ns 


'CLCX 


5 


Low time 


20 




20 


tCLCL-tCHCX 


ns 


tcLCH 


5 


Rise time 




20 




20 


ns 


tCHCL 


5 


Fall time 




20 




20 


ns 


Shift Register 


*XLXL 


4 


Serial port clock cycle time 


750 




12tcLCL 




ns 


tQVXH 


4 


Output data setup to clock rising edge 


492 




10t CLC L-133 




ns 


tXHQX 


4 


Output data hold after clock rising edge 


8 




2ICLCL-117 




ns 


'XHDX 


4 


Input data hold after clock rising edge 












ns 


txHDV 


4 


Clock rising edge to input data valid 




492 




10tcLCL-133 


ns 



NOTES: 

1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. See application note AN457 for external memory interfacing. 



1996 Aug 16 



3-16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) 

Tamb = 0-C to +70°C or -40°C to +85°C, V CC = 5V +1 0%, V SS = 0V 1 ■ 2 ' 3 





FIGURE 


PARAMFTFR 


24MHz CLOCK 


VARIABLE CLOCK 4 


33MHz CLOCK 


UNIT 


Ml W 


MAY 
IVIAA 


ml Pi 


HAY 
MAA 


MIN 
MIIN 


MAY 
MAA 


1/T CLCL 




r^cnillatAr from lAn/^w 
w&uiiiaiui iic^uci iuy 

Speed versions : P (24MHz) 
: Y (33MHz) 


3.5 


24 


3.5 


33 


3.5 


33 


MHz 


•lhll 


1 


ALE pulse width 


43 




2t C LCL-^0 




21 




ns 


'avll 


1 


Address valid to ALE low 


17 




tCLCL-25 




5 




ns 


Illax 


1 


Address hold after ALE low 


17 




tcLCL-25 








ns 


tLLIV 


1 


ALE low to valid instruction in 




102 




4tci_CL-65 




55 


ns 


tLLPL 


1 


ALE low to F5EN low 


17 




tCLCL-25 




5 




ns 


tpLPH 


1 


PSEN pulse width 


80 




3tci_CL-45 




45 




ns 


tpLIV 


1 


PSEN low to valid instruction in 




65 




3tcLCL-60 




30 


ns 


tpxix 


1 


Input instruction hold after PSEN 

















ns 


tpxiz 


1 


Input instruction float after PSEN 




17 




♦CLCL-25 




5 


ns 


tAVIV 


1 


Address to valid instruction in 




128 




5tcLCL-80 




70 


ns 


tpLAZ 


1 


PSEN low to address float 




10 




10 




10 


ns 


Data Memory 


*RLRh 


2,3 


RD pulse width 


150 




6tcLCL-1 nn 




82 




ns 


*WLWH 


2. 3 


WR pulse width 


150 




6tcLCL-100 




82 




ns 


*RLDV 


2.3 


RD low to valid data in 




118 




5tCLCL-90 




60 


ns 


•hhdx 


2,3 


Data hold after RD 

















ns 


•bhdz 


2,3 


Data float after RD 




55 




2tcLCL-28 




32 


ns 


•lldv 


2,3 


ALE low to valid data in 




183 




8tcLCL-150 




90 


ns 


Wdv 


2, 3 


Address to valid data in 




210 




9t LOL-1 65 




105 


ns 


'llwl 


2, 3 


ALE low to RD or WR low 


75 


175 


3t C LCL-50 


3t LOL+50 


40 


140 


ns 


Iavwl 


2,3 


Address valid to WR low or RD low 


92 




4tcLCL-75 




45 




ns 


tQVWX 


2, 3 


Data valid to WR transition 


12 




tcLCL-30 









ns 


twHQX 


2, 3 


Data hold after WR 


17 




tCLCL-25 




5 




ns 


tQVWH 


3 


Data valid to WR high 


162 




7tcLCL-130 




80 




ns 


tRLAZ 


2,3 


RD low to address float 

















ns 


twHLH 


2,3 


RDorWRhightoALE high 


17 


67 


tCLCL-25 


tcLCL+25 


5 


55 


ns 


External Clock 


tcHCX 


5 


High time 


17 




17 


tCLCL-tCLCX 






ns 


tCLCX 


5 


Low time 


17 




17 


feLCL-tcHCX 






ns 


tdCH 


5 


Rise time 




5 




5 






ns 


t0HCL 


5 


Fall time 




5 




5 






ns 


Shift Register 


'xLXL 


4 


Serial port clock cycle time 


505 




12 tcLCL 




360 




ns 


Iqvxh 


4 


Output data setup to clock rising edge 


283 




10tcLCL-133 




167 




ns 


'XHQX 


4 


Output data hold after dock rising edge 


3 




2t C LCL-80 








ns 


tXHDX 


4 


Input data hold after clock rising edge 

















ns 


*XHDV 


4 


Clock rising edge to input data valid 




283 




10t C LCL-133 




167 


ns 



NOTES: 



1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz 
"AC Electrial Characteristics", page 3-16. 



1996 Aug 16 



Philips Semiconductors 




Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 
T (= time). The other characters, depending on their positions, 
indicate the name of a signal or the logical status of that s gnal. The 



designations are: 
A - Address 
C - Clock 
D - Input data 
H - Logic level high 

I - Instruction (program memory contents) 
L - Logic level low, or ALE 



P - F5ETT 
Q - Output data 
R - RD signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: t AVLL = Time for address valid to ALE low. 
tl_ L PL= Time for ALE low to PS EN low. 



tLHLL 



*AVLL 



y v 



l lLPL 



tpLPH 



*LLIV 1 

•PLIV 



l LLAX 



tpLAZ 



tAVIV 



tpxix 



- tpxiz- 



) < ; .NSTpJ^^ A0-A7 y < 



>c 



: 



Figure 1. 




Memory Read Cycle 







s H 



tAVLL 



PORT 



jr. 



tLLDV 



tLLWL ► 



tLLAX 



" \ / ' AO-A7 \ 

? \ FROM Rl OR DPL ? 

* 
- 



tAVWL 



*RLRH 



tRLDV 



tAVDV " 



y 



*RHDX " 



> * 



tRHDZ. 



P2.0-P2.7 OR A6-A15 FROM DPH 



K, ' DATA IN ^ *°~ A7 FB0M PCL — ^~!NSTR IN 



A0-A15 FROM PCH 



Figure 2. External Data Ft 



1996 Aug 16 



3-18 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



'avll 



>: 







Illwl 



•llax 



\ / a^at s v ' 

? V FROM Rl OR DPL r\ 



\ 



UvWL 



*WLWH 



/ 



Iqvwx 



twHLH 



*~ twHQX 



>^ A0-A7 FROM PCL — < ^ INSTR IN 



P2.0-P2.7 OR A 







Figure 3. External Data Memory Write Cycle 




OUTPUT DATA . 



WRITE TO SBUF 



CLEAR Rl 



\*~ txLXL "*] 



tQVXH 



~i i i i i i i i i r 

k_jr~i 



V 



>C~>^I3<ZOCZ3C^>CZ3<ZI7 

1-lk.XHOX ♦ 
* *] | SETTI 



'XHDV 



t 

SET Rl 



Figure 4. Shift Register Mode Timing 



VcC-°5 
0.45V . 



r 0.7V C c 
0.2VCO-01 

tCHCL - 



•CLCX - * 



-•CHCX* 
■tcLCH 



'CLCL 



Figure 5. External Clock Drive 



1996 Aug 16 



3-19 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



Vcc-0-5 S. _/ 

\jT 0.2VOC+0.9 

0.45V / \ ° 2V CC^ ' 




NOTE: 

AC inputs during testing are driven at V cc — ( 
Timing measurements are made at V, H min tor a logic T and V, L max (or a logic '0'. 



Figure 6. AC Testing Input/Output 



vload - 



V|_OAD-° 



K 

tv X 



TIMING 
REFERENCE 
POINTS 



>: 



VOH-0.1V 
Vql+OIV 



NOTE: 

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, 
and begins to float when a 100mV change from the loaded VorAoL 'evel occurs. IqiVol £ ±20mA. 



Figure 7. 



ICC mA 20 




MAX ACTIVE MODE 
(ICCMAX» 1 «''«1 + 1.9) 



TYP ACTIVE MODE 



MAX IDLE MODE 



TYP IDLE MODE 



Figure 8. I cc vs. FREQ 
Valid only within frequency specifications of the device under test 



1996 Aug 16 



3-20 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



Vcc 

l— RST 



(NO- 
CLOCK SIGNAL - 



XTAL2 
XTAL1 

Vss 



Vcc 



Vcc 



1 



Vcc 



Figure 9. Ice Test Condition, Active Mode 
All other pins are disconnected 







(NO- 



CLOCK SIGNAL - 



RST 


Vcc 




PO 




EA 


XTAL2 




XTAL1 




Vss 









Vcc 



Figure 10. I cc Test Condition, Idle Mode 



0.45V r 0.2VCC-0.1 

tCHCL— »• 



-tCLCX"» 



-tcLCH 



'CLCL 



Figure 11. Clock Signal Waveform for l cc Teste in Active and Idle Modes 
•CLCH = tCHCL = 5ns 





Vcc 



(NCI- 





Vcc 


RST 






PO 






XTAL2 




XTAL1 




vss 






v cc 



Figure 12. Icc Test Condition, Power Down Mode 
All other pins are disconnected. V cc = 2V to 5.5V 



1996 Aug 16 



3-21 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80C31/80C51/87C51 



EPROM CHARACTERISTICS 

The 87C51 is programmed by using a modified Quick-Pulse 
Programming™ algorithm. It differs from older methods in the value 
used for V PP (progr ammin g supply voltage) and in the width and 
number of the ALE/PROG pulses. 

The 87C51 contains two signature bytes that can be read and used 
by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87C51 manufactured by 
Philips Corporation. 

Table 3 shows the logic levels for reading the signature bytes, and 
for programming the program memory, the encryption table, and the 
security bits. The circuit configuration and waveforms for quick-pulse 
programming are shown in Figures 13 and 14. Figure 15 shows the 
circuit configuration for normal program memory verification. 

Quick-Pulse Programming 

The setup for microcontroller quick-pulse programming is shown in 
Figure 13. Note that the 87C51 is running with a 4 to 6MHz 
oscillator. The reason the oscillator needs to be running is that the 
device is executing internal address and program data transfers. 

The address of the EPROM location to be programmed is applied to 
ports 1 and 2, as shown in Figure 1 3. The code byte to be 
programmed into that location is applied to port 0. RST, PSEN and 
pins of ports 2 and 3 specified in Table 3 are hel d at the 'Program 
Code Data' levels indicated in Table 3. The ALE/PROG is pulsed 
low 25 times as shown in Figure 1 4. 

To program the encryption table, repeat the 25 pulse programming 
sequence for addresses through 1 FH, using the 'Pgm Encryption 
Table' levels. Do not forget that after the encryption table is 
programmed, verification cycles will produce only encrypted data. 

To program the security bits, repeat the 25 pulse programming 
sequence using the 'Pgm Security Bit' levels. After one security bit is 
programmed, further programming of the code memory and 
encryption table is disabled. However, the other security t " 
be programmed. 

Note that the EATVpp pin must not be allowed to go above the 
maximum specified V PP level for any amount of time. Even a narrow 
glitch above that voltage can cause permanent damage to the 
device. The V PP source should be well regulated and free of glitches 
and overshoot. 

Table 3. EPROM Programming Modes 



Program Verification 

If security bit 2 has not been programmed, the on-chip program 
memory can be read out for program verification. The address of the 
program memory locations to be read is applied to ports 1 and 2 as 
shown in Figure 1 5. The other pins are held at the 'Verify Code Data' 
levels indicated in Table 3. The contents of the address location will 
be emitted on port 0. External pull-ups are required on port for this 
operation. 

If the encryption table has been programmed, the data presented at 
port will be the exclusive NOR of the program byte with one of the 
encryption bytes. The user will have to know the encryption table 
contents in order to correctly decode the verification data. The 
encryption table itself cannot be read out. 

Reading the Signature Bytes 

The signature bytes are read by the same procedure as a normal 
verification of locations 030H and 031 H, except that P3.6 and P3.7 
need to be pulled to a logic low. The values are: 
(030H) = 1 5H indicates manufactured by Philips 
(031 H)= 92H indicates 87C51 



Program/Verify Algorithms 

Any algorithm in agreement with the conditions listed in Table 3, and 
which satisfies the timing specifications, is suitable. 

Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is exposed to 
light with wavelengths shorter than approximately 4,000 angstroms. 
Since sunlight and fluorescent lighting have wavelengths in this 
range, exposure to these light sources over an extended time (about 
1 week in sunlight, or 3 years in room level fluorescent lighting) 
could cause inadvertent erasure. For this and secondary effects, 
it is recommended that an opaque label be placed over the 
window. For elevated temperature or environments where solvents 
are being used, apply Kapton tape Fluorglas part number 2345-5, or 
equivalent. 

The recommended erasure procedure is exposure to ultraviolet light 
(at 2537 angstroms) to an integrated dose of at least 1 SW-sec/cm 2 . 
Exposing the EPROM to an ultraviolet lamp of 1 2,000u,W/cm 2 rating 
for 20 to 39 minutes, at a distance of about 1 inch, should be 
sufficient. 

Erasure leaves the array in an all 1s state. 



MODE 


RST 


PSEN 


ALE/PROG 


EATVpp 


P2.7 


P2.6 


P3.7 


P3.6 


Read signature 


1 





1 


1 














Program code data 


1 





0* 


V P p 


1 





1 


1 


Verify code data 


1 





1 


1 








1 


1 


Pgm encryption table 


1 





0* 


Vpp 


1 





1 





Pgm security bit 1 


1 





0' 


V PP 


1 


1 


1 


1 


Pgm security bit 2 


1 





0* 


Vpp 


1 


I 









NOTES: 

1 . '0' = Valid low for that pin, '1 ' = valid high for that pin. 

2. Vpp = 12.75V ±0.25V. 

3. Vcc = 5V±10 % during programming and verification. 

4. "ALE/PROG receives 25 programming pulses while V PP is held at 12.75V. Each programming pulse is low for 100us (±10us) and high for a 
minimum of 10us. 



""Trademark phrase of Intel Corporation. 
1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C31/80C51/87C51 



+5V 



V 



-T- 



pi 

RST 



P3.6 
P3 ? 



vcc 

PO 

EAA/pp 
ALE/PROG 



B7C51 1 

XTAL2 



VSS 



- 



PZ.7 
P2.6 
P2.0-P2.3 



PGM DATA 

+12.75V 



I2.75V 

25 100ys PULSES TO GROUND 


1 


A8-A11 



Figure 13. Programming Configuration 



25 PULSES 



^-TLrLrLn- "ltl 



i 

■ 



10ns MIN — ►) |« 




100ps±10 







Figure 14. PROG Waveform 




- 



V 



pi 

RST 
P3.6 
P3.7 
XTAL2 

XTAL1 
V SS 



VCC 
PO 

EATVpp 
ALE/PROG 
87C51 PSEN 
P2.7 
P2.6 



P2.0-P2.3 



> 



SU00019 



Figure 15. Program Verification 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80C31/80C51/87C51 



EPROM PROGRAMMING AND VERIFICATION CHA 

T amb = 21 ° c to +27°C, V cc = 5V±10%, V ss = OV (See Figure 16) 



1 



SYMBOL 



MIN 



MAX 



UNIT 



Programming supply voltage 



12.5 



13.0 



l PP 



Programming supply current 



50 







mA 



1 'tcLCL 



Oscillator frequency 



MHz 



Wgl 



Address setup to PROG low 



48tcLCL 



*GHAX 



Address hold after PROG 



48tcLCL 



*DVGL 



Data setup to PROG low 



48t CL CL 



tGHDX 



Data hold after PROG 



48t CL CL 



tEHSH 



P2.7 (ENABLE) high to V PP 



48tc LCL 



tSHGL 



Vpp setup to PROG low 



10 



lis 



'ghsl 



Vpp hold after PROG 



10 



(IS 



tGLGH 



PROG width 



90 



110 



*AVQV 



Address to data valid 



48t CL CL 



(IS 



Ielqz 



ENABLE low to data valid 



48t C LCL 



'ehqz 



Data float after ENABLE 







48tcLCL 



tGHGL 



PROG high to PROG low 



10 



US 



P1.0-P1.7 
P2.0-P2.4 



*AVGL 



PROGRAMMING 




< ^ DATA IN > 



tGLGH 
*SHGL 



EATVpp 



P2.7 
ENABLE 



VERIFICATION 



> 



tGHDX 
tGHAX 



tGHGL 



tGHSL 



— 



tELQV 



tEHQZ 



NOTi 



FOR PROGRAMMING VERIFICATION SEE FIGURE 1 
FOR VERIFICATION CONDITIONS SEE FIGURE 15. 



Figure 16. 



1996 Aug 16 



3-24 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



DESCRIPTION 

The 83C51 FA/83C51 FB/80C51 FA Single-Chip 8-Bit Microcontroller 
is manufactured in an advanced CMOS process and is a derivative 
of the 80C51 microcontroller family. The 83C51 FA/83C51 FB/80C51 FA 
has the same instruction set as the 80C51 . 

This device provides architectural enhancements that make it 
applicable in a variety of applications for general control systems. 
The 83C51 FA contains 8k x 8 ROM memory (80C51 FA ROMIess 
version addresses up to 64k of external memory), the 83C51FB 
contains 1 6k x 8 ROM memory, the 83C51 FC contains 32k x 8 
ROM memory, a volatile 256 x 8 read/write data memory, four 8-bit 
I/O ports, three 1 6-bit timer/event counters, a Programmable 
Counter Array (PCA), a multi-source, four-priority-level, nested 
interrupt structure, an enhanced UART and on-chip oscillator and 
timing circuits. For systems that require extra capability, the 
83C51 FA/FB can be expanded using standard TTL compatible 
memories and logic. 

Its added features make it an even more powerful microcontroller for 
applications that require pulse width modulation, high-speed I/O and 
up/down counting capabilities such as motor control. It also has a 
more versatile serial channel that facilitates multiprocessor 

. _ .'C51FB datasheet for EPROM/OTP specifications. 




, PINC0NFIGU 




T2/P1.o[T 
T2EX/P1.1[2 
ECP,.2[3 
CEX0/P1.3|T 
CEX1/P1.4[T 
CEX2/P1.5[| 
CEX3/P1.6[T 
CEX4/P1.7[¥ 
RST[T 
FMWa.oflO 
TxD/P3.l[Ti 
1NT6/P3.2[ia 

wnvp3.3[T3 
TO/P3.4Q4 

T1/P3.5[T5 
WH/P3.6[l6 
RD/P3.7Q7 
XTAL2[ji 
XTAL1 |Ti 
Vss[20 



IN-LINE 
PACKAGE 



«| Vcc 
39] PO O/ADO 
38] P0.1/AD1 
37] P0.2/AD2 
36] P0.3/AO3 
3| P0.4/AD4 
34] P0.5/AD5 
33] P0.6/AD6 
32] P0.7/AD7 
3l] ES 
30| ALE 
29] PSEM 
Ss] P2.7/A15 
27] P2.6/A14 
26] P2.5/A13 
25] P2.4/A12 
24) P2.3/A11 
13] P2.2/A10 
22] P2.1/A9 
2l] P2.0/A8 



FEATURES 

• 80C51 central processing unit 

• Full static operation 

• 8k x 8 ROM: 83C51FA; 
16kx8ROM:83C51FB; 
32k x 8 ROM: 83C51FC 
ROMIess: 80C51FA 

all capable of addressing external memory to 64k bytes 

- Two level program security system 

- 64 byte encryption array 

• 256 x 8 RAM, expandable externally to 64k bytes 

• Speed range up to 33MHz 

• Three 16-bit timer/counters 

- T2 is an up/down counter 

• 7 interrupt sources 

• 4 level priority 

• Programmable Counter Array (PCA) 

- High speed output 

- Capture/compare 

- Pulse Width Modulator 

- Watchdog Timer 

• Four 8-bit I/O ports 

• Full-duplex enhanced UART 

- Framing error detection 

- Automatic address recognition 

• Power control modes 

- Idle mode 

- Power-down mode 

• Once (On Circuit Emulation) Mode 

• Five package styles 

• Programmable clock out 

• Low EMI (inhibit ALE) 

• Second DPTR register (ROM only) 

• Asynchronous port Reset 



1996 Aug 16 



3-25 



853-173017198 



Philips Semiconductors 




Product specification 







CMOS 



83C51 FA/83C51 FBI 
single-chip 8-bit microcontrollers 83C51 FC/80C51 FA 

— — 







ORDERING INFORMATION 



ROMIess 


ROM 

8Kx8 


ROM 

16K x8 


ROM 

32Kx8 


TEMPERATURE RANGE °C 
AND PACKAGE 


VOLTAGE 
RANGE 

(V) 1 


FREQ. 
(MHZ) 


DWG. 
# 


S80C51 FA^tN40 


S83C51FA-4N40 


S83C51FB-4N40 


S83C51FC-4N40 


to +70, 
40-Pin Plastic Dual In-line Pkg. 


2.7I0 5.5 1 


3.5 to 16 


SOT129-1 


S80C51FA-4A44 


S83C51FA-4A44 


S83C51FB-4A44 


S83C51FC-4A44 


to +70, 

44-Pin Plastic Leaded Chip Carrier 


2.7 to 5.5' 


3.5 to 16 


SOT1 87-2 


S80C51FA-4B44 


S83C51FA-4B44 


S83C51FB-4B44 


S83C51FC-4B44 


to +70, 
44-Pin Plastic Quad Flat Pack 


2.7 to 5.5 1 


3.5 to 16 


SOT307-2 


S80C51FA-5N40 


S83C51FA-5N40 


S83C51FB-5N40 


S83C51FC-5N40 


-10 to +85, 
40-Pin Plastic Dual In-line Pkg. 


2.7to5.5 1 


3.5 to 16 


SOT1 29-1 


S80C51FA-5A44 


S83C51FA-5A44 


S83C51FB-5A44 


S83C51FC-5A44 


-40 to +85, 
44-Pin Plastic Leaded Chip Carrier 


2.7to5.5 1 


3.5 to 16 


SOT187-2 


S80C51FA-SB44 


S83C51FA-5B44 


S83C51FB-5B44 


S83C51FC-5B44 


-40 to +85, 
44-Pin Plastic Quad Flat Pack 


2.7to5.5 1 


3.5 to 16 


SOT307-2 


S80C51FA-AN40 


S83C51FA-AN40 


S83C51FB-AN40 


S83C51FC-AN40 


to +70, 
40-Pin Plastic Dual In-line Pkg. 


5 


3.5 to 24 


SOT129-1 


S80C5 1 FA-AA44 


S83C51FA-AA44 


S83C51FB-AA44 


S83C51FC-AA44 


to +70, 
44-Pin Plastic Leaded Chip Carrier 


5 


3.5 to 24 


SOT187-2 


S80C51FA-AB44 


S83C51FA-AB44 


S83C51FB-AB44 


S83C51FC-AB44 


to +70, 
44-Pin Plastic Quad Flat Pack 


5 


3.5 to 24 


SOT307-2 


S80C51FA-BN40 


S83C51FA-BN40 


S83C51FB-BN40 


S83C51FC-BN40 


-40 to +85, 
40-Pin Plastic Dual In-line Pkg. 


5 


3.5 to 24 


SOT129-1 


S80C51FA-BA44 


S83C51FA-BA44 


S83C51FB-BA44 


S83C51FC-BA44 


-40 to +85, 
44-Pin Plastic Leaded Chip Carrier 


5 


3.5 to 24 


SOT1 87-2 


S80C51FA-BB44 


S83C51FA-BB44 


S83C51FB-BB44 


S83C51FC-BB44 


-40 to +85, 
44-Pin Plastic Quad Flat Pack 


5 


3.5 to 24 


SOT307-2 


S80C51FA-IN40 


S83C51FA-IN40 


S83C51FB-IN40 


S83C51FC-IN40 


to +70, 
40-Pin Plastic Dual In-line Pkg. 


5 


3.5 to 33 


SOT1 29-1 


S80C51FA-IA44 


S83C51FA-IA44 


i 

S83C51FB-IA44 


S83C51FC-IA44 


to +70, 
44-Pin Plastic Leaded Chip Carrier 


5 


3.5 to 33 


SOT1 87-2 


S80C51FA-IB44 


S83C51FA-IB44 


S83C51FB-IB44 


S83C51FC-IB44 


to +70, 
44-Pin Plastic Quad Flat Pack 


5 


3.5 to 33 


SOT307-2 


S80C51FA-JN40 


S83C51FA-JN40 


S83C51FB-^JN40 


S83C51FC-JN40 


-40 to +85, 
40-Pin Plastic Dual In-line Pkg. 


5 


3.5 to 33 


SOT1 29-1 


S80C51FA-xJA44 


S83C51FA-JA44 


S83C51FB-JA44 


S83C51FC^IA44 


-40 to +85, 
44-Pin Plastic Leaded Chip Carrier 


5 


3.5 to 33 


SOT187-2 


S80C51FA-JB44 


S83C51FA^JB44 


S83C51FB-JB44 


S83C51FCXJB44 


-40 to +85, 
44-Pin Plastic Quad Flat Pack 


5 


3.5 to 33 


SOT307-2 



NOTE: 

1 . S80C51 FA devices are specified for 5V only. 



1996 Aug 16 



3-26 



Philips Semiconductors 



Product specification 



single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



BLOCK DIAGRAM 







PORTO 
DRIVERS 



yccj 
I 

vssl 

I 
I 



: f¥ 

Iz. 



t- 



PORT 2 
DRIVERS 



¥ 



PORT 2 
LATCH 



IE ¥ 



B 




ACC 


REGISTER 





STACK 
POINTER 



I 



<> <> 


V 


TMP2 




TMP1 



n 



PSEW*-| — 



EA- 
RST— 





2 






o 


cc 


TIMING 


o 


LU 


AND 


=) 


W 


CONTROL 




a 

LU 




CO 


fx 









PSW 
TV - 



SFRs 
TIMERS 
P.CA 



7^ 77 



|_XJAL1 



1" 



¥ 



¥ 



----- Hf — 







PROGRAM 
ADDRESS 



BUFFER 



PROGRAM 
COUNTER 



£3 



J> DPTR ^> 



1996 Aug 16 



3-27 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 83C51 rc/80C51 



Table 1 . 83C51 FA/83C51 FB/83C51 FC/80C51 FA Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 


BIT ADDRESS, SYMBOL. OR ALTERNATIVE PORT FUNCTION 
MSB LSB 


nccpT 
ttCSt 1 

VALUE 


ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 




E2 


E1 


EO 


00H 


AUXR# 


Auxiliary 


8EH 
















AO 


xxxxxxxOB 


AUXR1# 


Auxiliary 1 3 


A2H 


















DPSO 


xxxxOxxOB 


B* 


B register 


FOH 




F6 


F5 




F3 




F2 


Pi 

r I 


Fn 


00H 


CCAP0H# 


Module Capture High 
Module 1 capture nign 


FAH 
FBH 


















xxxxxxxxB 
xxxxxxxxB 


CCAP2H# 


Module 2 Capture High 


FCH 






















xxxxxxxxB 


CCAP3H# 
CCAP4H# 


Module 3 Capture High 
Module 4 Capture High 


FDH 
FEH 




















xxxxxxxxB 
xxxxxxxxB 


PPADDI it 


Module Capture Low 


CAM 

LAM 






















xxxxxxxxB 


CCAP1L# 


Module 1 Capture Low 


EBH 




















xxxxxxxxB 


PPAP9I it 


Module 2 Capture Low 


ECH 


















xxxxxxxxB 


CCAP3L# 


Module 3 Capture Low 


EDH 


















xxxxxxxxB 


CCAP4L# 


Module 4 Capture Low 


EEH 






















xxxxxxxxB 


CCAPMO* 


Module Mode 


DAH 


- 


ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


X0000000B 




IVIUUUIC 1 iviuue 


DBH 


- 


ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


Ff^(~F 


X0000000B 


COArM2# 


Module 2 Mode 


DCH 


- 


ecow 


CAPP 


CAPN 


MAT 


TOG 


PWM 


coor 


X0000000B 


CCAPM3* 


Module 3 Mode 


DDH 


- 


ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


X0000O00B 


CCAPM4# 


Module 4 Mode 


DEH 


- 


ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


X0000000B 








DF 


DE 


DD 


DC 


DB 




DA 


D9 


D8 




CCON*# 


PCA Counter Control 


D8H 


CF 


CR 


- | CCF4 


CCF3 


I CCF2 


CCF1 


CCFO 


00X00000B 


CH# 


PCA Counter High 


F9H 






















00H 


CL# 


PCA Counter Low 


E9H 






















00H 


CMOD# 


PCA Counter Mode 


D9H 


CIDL 


WDTE 










CPS1 


I 

CPSO 


I 

ECF 


OOxxxOOOB 


DPTR: 


Data Pointer (2 bytes) 


























DPH 


Data Pointer High 


83H 






















00H 


DPL 


Data Pointer Low 


82H 






















O0H 








AF 


AE 


AD 


AC 


AB 




AA 


A9 


A8 






Interrupt Enable 


A8H 


EA 


EC 


ET2 


* 


ET1 




EX1 


ETO 


EXO 


00H 








BF 


BE 


BD 


BC 


BB 




BA 


B9 


B8 




, 


Intiirn int Drirtrihi 

interrupt rnoniy 


B8H 




PPC 


PT2 


PS 


PT1 




PX1 


PTO 


PXO 


X0000000B 








B7 


B6 


B5 


B4 


B3 




B2 


B1 


BO 




IPH# 


Interrupt Priority High 


B7H 




PPCH | 


PT2H 


PSH | 


PT1H 




PX1H 


PTOH 


PXOH 


X0000000B 








87 


86 


85 


84 


83 




82 


81 


80 




PO* 


PortO 


80H 


AD7 | 


AD6 


AD5 


AD4 


AD3 


AD2 


AD1 


ADO 


FFH 


PI* 






97 


96 


95 


94 


93 




92 


91 


90 




Portl 


90H 


CEX4 | 


CEX3 | 


CEX2 | 


CEX1 | 


CEXO 


I 


ECI | 


T2EX 


T2 


FFH 








A7 


A6 


A5 


A4 


A3 




A2 


A1 


AO 




P2* 


Port 2 


AOH 


AD15 


AD14 | 


AD13 | 


AD12 | 


AD11 


I 


AD10 


AD9 


AD8 


FFH 








B7 


B6 


B5 


B4 


B3 




B2 


B1 


BO 




P3* 


Port 3 


BOH 


RTJ 


WR 


T1 


TO I 


WIT 


I 


INTO" | 


TxD 


RxD 


FFH 












PCON# 


Power Control 


87H 


SM0D1 | 


SMODO | 


_i 


POF 2 | 


GF1 


1 




» I 


PD 


IDL 


OOxxOOOOB 



# SFRs are modified from or added to the 80C51 SFRs. 

- Reserved bits. 

1 . Reset value depends on reset source. 

2. Bit will not be affected by Reset. 

3. Not available on 80C51 FA (ROMIess) at this time. 



1996 Aug 16 



3-28 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



Table 1 . 83C51 FA/83C51 FB/83C51 FC/80C51 FA Special Function Registers (Continued) 



SYMBOL 



DESCRIPTION 



DIRECT 
ADDRESS 



BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 
MSB LSB 



RESET 
VALUE 



PSW 

RACAP2H# 

RACAP2L# 

SADDR# 
SADEN# 

SBUF 

SCON* 
SP 

TCON- 



T2CON" 
T2MOD# 

THO 

TH1 

TH2# 

TLO 

TL1 

TL2# 

TMOD 



Program Status Word 
Timer 2 Capture High 
Timer 2 Capture Low 

Slave Address 
Slave Address Mask 

Serial Data Buffer 

Serial Control 
Stack Pointer 

Timer Control 



Timer 2 Control 
Timer 2 Mode Control 

Timer High 
Timer High 1 
Timer High 2 
Timer Low 
Timer Low 1 
Timer Low 2 

Timer Mode 



DOH 
CBH 
CAH 

A9H 
B9H 



99H 



98H 
81H 



88H 



C8H 
C9H 

8CH 
8DH 
CDH 
8AH 
8BH 
CCH 

89H 



D6 



D5 



D4 



D3 



D2 



D1 



CY 



AC I 



7TJ 



RS1 



RSO 



OV 



— 







DO 



9F 


9E 


9D 


9C 


9B 


9A 


99 


98 


SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 




R, 


8F 


8E 


8D 


8C 


8B 


8A 


89 


88 


TF1 


TR1 


TFO 


TRO 


IE1 


IT1 


,E0 


ITO 


CF 


CE 


CD 


cc 


CB 


CA 


C9 


C8 


TF2 


EXF2 


RCLK 


TCLK 


EXEN2 


TR2 


C/T2 


CP/RE5 














T20E 


DCEN 



00H 
00H 
00H 

00H 
00H 

xxxxxxxxB 

OOH 
07H 



GATE | C/T | M1 | MO | GATE | C/T | M1 | MO 



OOH 



OOH 

xxxxxxOOB 

OOH 
OOH 
OOH 
OOH 
OOH 
OOH 

OOH 



* SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 
- Reserved bits. 



1996 Aug 16 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers ^IFO^™ 



PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS PLASTIC QUAD FLAT PACK PIN FUNCTIONS 



Pln Function 

2 P1.0/T2 

3 P1.1fT2EX 

4 P1.2/ECI 

5 P1.3/CEX0 

6 P1.4/CEX1 

7 P1.5/CEX2 

8 P1.6/CEX3 

9 P1.7/CEX4 
10 RST 

P3.0/RXD 
NC- 

P3.1/TxD 



11 

12 
13 



14 



15 P3.3/INTT 
* DO NOT CONNECT 




Pin Function 

31 P2.7/A 15 
P5EN 
ALE 
NC" 
EA 

P0.7/AD7 
P0.6/AD6 
P0.5/AD5 
P0.4/AD4 

40 P0.3/AD3 

41 P0.2/AD2 

42 P0.1/AD1 

43 P0.0/AD0 

44 V cc 




Pin 


Function 


le" 


Function 


Pin 


Function 


1 


P1.5/CEX2 


Vss 


31 


P0.6/AD6 


2 


P1.6/CEX3 


17 


NC 


32 


P0.5/AD5 


3 


P1.7/CEX4 


18 


P2.0/A8 


33 


P0.4/AD4 


4 


RST 


19 


P2.1/A9 


34 


P0.3/AD3 


5 


P3.0/RXD 


20 


P2.2/A10 


35 


P0.2/AD2 


e 


NC- 


21 


P2.3/A11 


36 


P0.1/AD1 


7 


P3.irTxD 


22 


P2.4/A12 


37 


P0.0/AD0 


e 


P3.2/1NT5 


23 


P2.5/A13 


38 


Vcc 


9 


P3.3/IRTT 


24 


P2.6/A14 


39 


NC* 


10 


P3.4/T0 


25 


P2.7/A15 


40 


P1.0/T2 


11 


P3.5/T1 


26 


PSEN 


41 


P1.W2EX 


12 


P3.6/WR 


27 


ALE 


42 


P1.2/ECI 


13 


P3.7/HD 


28 


NC- 


43 


P1.3/CEX0 


14 


XTAL2 


29 


ES 


44 


P1.4/CEX1 


15 


XTAL1 


30 


P0.7/AD7 







PIN DESCRIPTIONS 



SU00716B 



MNEMONIC 



PIN NUMBER 



DIP 



LCC 



QFP 



TYPE 



NAME AND FUNCTION 



Vss 
Vcc 

PO.0-0.7 



P1.0-P1.7 



P2.0-P2.7 



20 
40 



39-32 



1-8 



1 

2 
3 
4 
5 
6 
7 
8 

21-28 



22 
44 



43-36 



2-9 



2 
3 
4 
5 
6 
7 
8 
9 

24-31 



16 
38 



37-30 



40-44, 
1-3 



40 
41 
42 
43 
44 

1 

2 

3 

18-25 



I/O 



I/O 



I/O 
I 
I 

I/O 
I/O 
I/O 
I/O 
I/O 
I/O 



Ground: 0V reference. 

Power Supply: This is the power supply voltage for normal, idle, and power-down 
operation. 

Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to 
them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data memory. In 
this application, it uses strong internal pull-ups when emitting 1s. Port also outputs the 
code bytes during program verification. External pull-ups are required during program 
verification. 

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 1 pins that are externally pulled low will source current because of the internal pull-ups. 
(See DC Electrical Characteristics: Iil). Port 1 also receives the low-order address byte 
during program memory verification. Alternate functions include: 

T2 (P1 .0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) 

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 

ECI (P1.2): External Clock Input to the PCA 

CEX0 (P1.3): Capture/Compare External I/O for PCA module 

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 2 pins that are externally being pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l !L ). Port 2 emits the high-order address byte 
during fetches from external program memory and during accesses to external data memory 
that use 16-bit addresses (MOVX ODPTR). In this application, it uses strong internal 
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit 

™ port 2 emits the contents of the P2 special function register. 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit mici 




83C51 FA/83C51 FB/ 
83C51FC/80C51FA 



PIN DESCRIPTIONS (Continued) 



MNEMONIC 



PIN NUMBER 



DIP 



LCC 



QFP 



TYPE 



NAME AND FUNCTION 



P3.0-P3.7 



RST 



ALE 



F5EN 



EA 



XTAL1 
XTAL2 



10-17 



10 
11 

12 
13 
14 
15 
16 
17 



30 



29 



31 



19 
18 



11, 
13-19 



11 
13 
14 
15 
16 
17 
18 
19 
10 



33 



32 



35 



21 
20 



5, 
7-13 



5 
7 
8 
9 
10 
11 
12 
13 
4 



27 



26 



29 



15 
14 



I/O 



Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s 



written to them are pulled high by the internal pull-ups and 



port 3 pins that are externally being pulled low will source current 



the special features of the 80C51 



I 

O 
I 
I 
I 
I 

o 
o 
I 



can be used as inputs. As inputs, 



of the pull-ups. 



(See DC Electrical Characteristics: l| L ). Port 3 also serves t 
family, as listed below: 

RxD (P3.0): Serial input port 
TxD (P3.1): Serial output port 
INTO (P3.2): External interrupt 
INTT (P3.3): External interrupt 
TO (P3.4): Timer external input 
T1 (P3.5): Timer 1 externa! input 
WR (P3.6): External data memory write strobe 
HD (P3.7): External data memory read strobe 

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to Vss permits a power-on reset using only an external 
capacitor to V cc . 

Address Latch Enable: Output pulse for latching the low byte of the address during an 
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the 
oscillator frequency, and can be used for external timing or clocking. Note that one ALE 
pulse is skipped during each access to external data memory. ALE can be disabled by 
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. 

Program Store Enable: The read strobe to external piogram memory. When the 8XC51 FX 
is executing code from the exte rnal pr ogram memory, PSEN is activated twice each 
machine cycle, except that tw o PSEN activations are skipped during each access to 
external data memory. PSEN is not activated during fetches from internal program memory. 

External Access Enable: EA must be externally held low to enable the device to fetch code 
from external program memory locations 0000H and 7FFFH. If EA" is held high, the device 
executes from internal program memory unless the program counter contains an address 
greater than 7FFFH. If security bit 1 is programmed, EA w II be internally latched on Reset. 

Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
O | Crystal 2: Output from the inverting oscillator amplifier. 



NOTE: 

To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V C c + 0.5V or V ss - 



0.5V, respectively. 



- 



1996 Aug 16 



Philips Semiconductors 



Product specification 



fi^PRi PA/A^r^m pr/ 

CMOS single-chip 8-bit microcontrollers Q3C51 FC/80C51 FA 



TIMER 2 OPERATION 
Timer 2 

Timer 2 is a 1 6-bit Timer/Counter which can operate as either an 
event timer or an event counter, as selected by C/T2* in the special 
function register T2CON (see Figure 1 ). Timer 2 has three operating 
modes:Capture, Auto-reload (up or down counting) ,and Baud Rate 
Generator, which are selected by bits in the T2CON as shown in 
Table 2. 

Capture Mode 

In the capture mode there are two options which are selected by bit 
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or 
counter (as selected by C/T2* in T2CON) which, upon overflowing 
sets bit TF2, the timer 2 overflow bit. This bit can be used to 
generate an interrupt (by enabling the Timer 2 interrupt bit in the 
IE register/SFR table). If EXEN2= 1 , Timer 2 operates as described 
above, but with the added feature that a 1 - to -0 transition at external 
input T2EX causes the current value in the Timer 2 registers, TL2 
and TH2, to be captured into registers RCAP2L and RCAP2H, 
respectively. In addition, the transition at T2EX causes bit EXF2 in 
T2CON to be set, and EXF2 like TF2 can generate an interrupt 
(which vectors to the same location as Timer 2 overflow interrupt. 
The Timer 2 interrupt service routine can interrogate TF2 and EXF2 
to determine which event caused the interrupt). The capture mode is 
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in 
this mode. Even when a capture event occurs from T2EX, the 
counter keeps on counting T2EX pin transitions or osc/12 pulses.). 

Auto-Reload Mode (Up or Down Counter) 

In the 1 6-bit auto-reload mode, Timer 2 can be configured (as either 
a timer or counter (C/T2* in T2CON)) then programmed to count up 
or down. The counting direction is determined by bit DCEN(Down 
Counter Enable) which is located in the T2MOD register (see 

, 



Figure 3). When reset is applied the DCEN=0 which means Timer 2 
will default to counting up. If DCEN bit is set, Timer 2 can count up 
or down depending on the value of the T2EX pin. 

Figure 4 shows Timer 2 which will count up automatically since 
DCEN=0. In this mode there are two options selected by bit EXEN2 
in T2CON register. If EXEN2=0, then Timer 2 counts up to OFFFFH 
and sets the TF2 (Overflow Rag) bit upon overflow. This causes the 
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L 
and RCAP2H. 

The values in RCAP2L and RCAP2H are preset by software means. 
If EXEN2=1 , then a 1 6-bit reload can be triggered either by an 
overflow or by a 1-to-0 transition at input T2EX. This transition also 
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be 
generated when either TF2 or EXF2 are 1 . 

In Figure 5 DCEN=1 which enables Timer 2 to count up or down. 
This mode allows pin T2EX to control the direction of count. When a 
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will 
overflow at OFFFFH and set the TF2 flag, which can then generate 
an interrupt, if the interrupt is enabled. This timer overflow also 
causes the 16-bit value in RCAP2L and RCAP2H to be reloaded 
into the timer registers TL2 and TH2. 

When a logic is applied at pin T2EX this causes Timer 2 to count 
down. The timer will underflow when TL2 and TH2 become equal to 
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets 
the TF2 flag and causes OFFFFH to be reloaded into the timer 
registers TL2 and TH2. 

The external flag EXF2 toggles when Timer 2 underflows or 
overflows. This EXF2 bit can be used as a 1 7th bit of resolution if 
needed. The EXF2 flag does not generate an interrupt in this mode 
of operation. 

















(MSB) 














(LSB) 


TF2 


EXF2 


RCLK 

' ' 


TCLK 


EXEN2 


TR2 


C/T2" 


CP/RES 





Symbol Position Name and Significance 



TF2 
EXF2 

RCLK 
TCLK 
EXEN2 



TR2 

cm 



T2CON.7 
T2CON.6 

T2CON.5 
T2CON.4 
T2CON.3 

T2CON.2 
T2CON.1 



CP/RT2 T2CON.0 



Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set 
when either RCLK or TCLK = 1 . 

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and 
EXEN2 = 1 . When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down 
counter mode (DCEN = 1). 

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock 
in modes 1 and 3. RCLK = causes Timer 1 overflow to be used for the receive clock. 
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock 
in modes 1 and 3. TCLK = causes Timer 1 overflows to be used for the transmit clock. 

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative 
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = causes Timer 2 to 
ignore events at T2EX. 

Start/stop control for Timer 2. A logic 1 starts the timer. 
Timer or counter select. (Timer 2) 

= Internal timer (OSC/12) 

1 = External event counter (falling edge triggered). 

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1 . When 
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when 
EXEN2 = 1 . When either RCLK = 1 or TCLK = 1 , this bit is ignored and the timer is forced to auto-reload 
on Timer 2 overflow. 

SU00728 



Figure 1. Timer/Counter 2 (T2CON) Control Register 



1996 Aug 16 



3-32 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



Table 2. Timer 2 Operating Modes 



RCLK + TCLK 


CP/RT3 


TR2 


MODE 








1 


1 6-bit Auto-reload 





1 


1 


16-bit Capture 


1 


X 


1 


Baud rate generator 


X 


x 





(off) 



osc 




» 12 





C/TS.O 




















TL2 


TH2 




C/TZ = 1 








(8-bits) 


(8-Ms) 


— K 




Control 









Capture 



•s — 



Timer 2 
Interrupt 



Figure 2. Timer 2 In Capture Mode 



T2MOD Address = 0C9H 
Not Bit Addressable 



Reset Value = XXXX XXOOB 

















T20E 




DCEN 




Bit 7 
Symbol Function 


6 


5 


4 


3 


2 


1 






— Not implemented, reserved for future use." 

T20E Timer 2 Output Enable bit. 

DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. 

User software should not write 1 s to reserved bits. These bits may be used in future 8051 family products to invoke new features. 
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1 . The value read from a reserved bit is 
indeterminate. 

SU00729 



Figure 3. Timer 2 Mode (T2MOD) Control Register 



1996 Aug 16 



3-33 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51 FC/80C51 FA 



osc 




* 12 





C/T2= 1 







TL2 


TH2 


(8-BITS) 


(8-BITS) 




OSC 




»12 






T2F 


IN — 



COUNT 
DIRECTION 
1 =UP 
= DOWN 



(UP COUNTING RELOAD VALUE) 



T2EX PIN 



Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 



-• 



1996 Aug 16 



3-34 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 





NOTE: OSC. Free, is divided by 2. no! 12. 





Timer 1 
Overflow 




TL2 


TH2 


(8-bils) 


(8-bils) 



•or t 
"i" -o- 



SMOD 
RCLK 




Nole availability of additional external interrupt. 



Tab 



le 3. Timer 2 Generated 
Baud Rates 



Figure 6. Timer 2 in Baud Rate Generator Mode 



The baud rates in modes 1 and 3 
overflow rate given below: 



Baud Rate 


Osc Freq 


Timer 2 


RCAP2H 


RCAP2L 


375K 


12MHz 


FF 


FF 


9.6K 


12MHz 


FF 


D9 


2.8K 


12MHz 


FF 


B2 


2.4K 


12MHz 


FF 


64 


1.2K 


12MHz 


FE 


C8 


300 


12MHz 


FB 


1E 


110 


12MHz 


F2 


AF 


300 


6MHz 


FD 


8F 


110 


6MHz 


F9 


57 



Modes 1 and 3 Baud Rates 



are determined by Timer 2's 

Timer 2 Overflow Rate 
16 



The timer can be configured for either "timer" or "counter" operation. 
In many applications, it is configured for "timer" operation (C/T2'=0). 
Timer operation is different for Timer 2 when it is being used as a 
baud rate generator. 

Usually, as a timer it would increment every machine cycle (i.e., 1/12 
the oscillator frequency). As a baud rate generator, it increments 
every state time (i.e., 1/2 the oscillator frequency). Thus the baud 
rate formula is as follows: 



Modes 1 and 3 Baud Rates = 

Oscillator Frequency 



Baud Rate Generator Mode 

Bits TCLK and/or RCLK in T2CON (Table 2) allow the serial port 
transmit and receive baud rates to be derived from either Timer 1 or 
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit 
baud rate generator. When TCLK= 1, Timer 2 is used as the serial 
port transmit baud rate generator. RCLK has the same effect for the 
serial port receive baud rate. With these two bits, the serial port can 
have different receive and transmit baud rates - one generated by 
Timer 1 , the other by Timer 2. 

Figure 6 shows the Timer 2 in baud rate generation mode. The baud 
rate generation mode is like the auto-reload mode.in that a rollover 
in TH2 causes the Timer 2 registers to be reloaded with the 1 6-bit 
value in registers RCAP2H and RCAP2L, which are preset by 
software. 



1996 Aug 16 



[32 X [65536 - (RCAP2H, RCAP2L)]] 

Where: (RCAP2H, RCAP2L)= The content of RCAP2H and 
RCAP2L taken as a 1 6-bit unsigned integer. 

The Timer 2 as a baud rate generator mode shown in Figure 6, is 
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a 
rollover in TH2 does not set TF2, and will not generate an interrupt. 
Thus, the Timer 2 interrupt does not have to be disabled when 
Timer 2 is in the baud rate generator mode. Also if the EXEN2 
(T2 external enable flag) is set, a 1-to-0 transition in T2EX 
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but 
will not cause a reload from (RCAP2H, RCAP2L) to (TH2.TL2). 
Therefore when Timer 2 is in use as a baud rate generator, T2EX 
can be used as an additional external interrupt, if needed. 



Philips Semiconductors Product specification 

^..^ a " . 83C51 FA/83C51 FB/ 

CMOS single-chip 8-bit microcontrollers 83C51 FC/80C51 FA 



When Timer 2 is in the baud rate generator mode, one should not try 
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is 
incremented every state time (osc/2) or asynchronously from pin T2; 
under these conditions, a read or write of TH2 or TL2 may not be 
accurate. The RCAP2 registers may be read, but should not be 
written to, because a write might overlap a reload and cause write 
and/or reload errors. The timer should be turned off (clear TR2) 
before accessing the Timer 2 or RC 

Table 3 shows commonly used baud rates and t 
obtained from Timer 2. 



Baud Rate 



To obtain the reload value for RCAP2H and RCAP2L, the above 
equation can be rewritten as: 



RCAP2H, RCAP2L = 65536 



( fpsc \ 
32 x Baud Rate j 



Summary Of Baud Rate Equations 

Timer 2 is in baud rate generating mode. If Timer 2 
through pin T2(P1 .0) the baud rate is: 




Timer 2 Overflow Rate 
16 



If Timer 2 is being clocked internally , the baud r 



Baud Rate = ; 



[32 x [65536 
Where fosc= Oscillator Frequency 

Table 4. Timer 2 as a Timer 



f osc 

(RCAP2H, RCAP2L)]] 



Timer/Counter 2 Set-up 

Except for the baud rate generator mode, the values given for 
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 
must be set, separately, to turn the timer on. see Table 4 for set-up 
of Timer 2 as a timer. Also see Table 5 for set-up of Timer 2 as a 
counter. 



POWER OFF FLAG 

The Power Off Flag (POF) is set by on-chip circuitry when the Vcc 
level on the 8XC51 FA/83C51 FB/83C51 FC rises from to 5V. The 
POF bit can be set or cleared by software allowing a user to 
determine if the reset is the result of a power-on or a warm start 
after powerdown. The V c c level must remain above 3V for the POF 
to remain unaffected by the V cc level. 



MODE 


T2CON 


INTERNAL CONTROL 
(Note 1) 


EXTERNAL CONTROL 
(Note 2) 


16-bit Auto-Reload 


00H 


08H 


16-bit Capture 


01 H 


09H 


Baud rate generator receive and transmit same baud rate 


34H 


36H 


Receive only 


24H 


26H 


— z : — i 

Transmit only 


14H 


16H 


Table 5. Timer 2 as a Counter 


MODE 


TMOD 


INTERNAL CONTROL 
(Note 1) 


EXTERNAL CONTROL 
(Note 2) 


16-bit 


02H 


OAH 


Auto-Reload 


03H 


OBH 



NOTES: 

1 . Capture/reload occurs only on timer/counter overflow. 

2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate 
generator mode. 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS 



8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 
oscillator. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements 
on the duty cycle of the external clock signal, because the input to 
the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 

Reset 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-on reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. At power-on, the voltage on 
Vcc and RST must come up at the same time for a proper start-up. 
Ports 1 , 2, and 3 will asynchronously be driven to their reset 
condition when a voltage above V !H1 (min.) is applied to RESET. 

Idle Mode 

In the idle mode (see Table 6), the CPU puts itself to sleep while all 
of the on-chip peripherals stay active. The instruction to invoke the 
idle mode is the last instruction executed in the normal operating 
mode before the idle mode is activated. The CPU contents, the 
on-chip RAM, and all of the special function registers remain intact 
during this mode. The idle mode can be terminated either by any 




rocess is picked up at the 
or by a hardware reset 
manner as a power-on reset. 



enabled interrupt (at which 
interrupt service routine and . 
which starts the processor in 

Power-Down Mode 

To save even more power, a Power Down mode (see Table 6) can 
be invoked by software. In this mode, the oscillator is stopped and 
the instruction that invoked Power Down is the last instruction 
executed. The on-chip RAM and Special Function Registers retain 
their values until the Power Down mode is terminated. 

Either a hardware reset or external interrupt can be used to exit from 
Power Down. Reset redefines all the SFRs but does not change the 
on-chip RAM. An external interrupt allows both the SFRs and the 
on-chip RAM to retain their values. 

To properly terminate Power Down the reset or external interrupt 
should not be executed before Vcc is restored to its normal 
operating level and must be held active long enough for the 
oscillator to restart and stabilize (normally less than 1 0ms). 

With an external interrupt, INTO and INT1 must be enabled and 
configured as level-sensitive. Holding the pin low restarts the 
oscillator but bringing the pin back high completes the exit. Once the 



interrupt is serviced, the next instruction to be executed after RETI 
i that put the device into 



Design Consideration 

• When the idle mode is terminated by a hardware reset, the device 
normally resumes program execution, from where it left off, up to 
two machine cycles before the internal rest algorithm takes 
control. On-chip hardware inhibits access to internal RAM in this 
event, but access to the port pins is not inhibited. To eliminate the 
possibility of an unexpected write when Idle is terminated by reset, 
the instruction following the one that invokes Idle should not be 
one that writes to a port pin or to external memory. 

ONCE™ Mode 

The ONCE ("On-Circuit Emulation") Mode facilitates testing and 
debugging of systems using the 8XC51 FA/FB without the 
8XC51FA/FB/FC having to be removed from the circuit. The ONCE 
Mode is invoked by: 

1 . Pull ALE low while the device is in reset and PS EN is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in ONCE Mode, the Port pins go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the 8XC51 FA/FB is 
in this mode, an emulator or test CPU can be used to drive the 
circuit. Normal operation is restored when a normal reset is applied. 

Programmable Clock-Out 

The 8XC51 FA/83C51 FB has a new feature. A 50% duty cycle clock 
can be programmed to come out on P1 .0. This pin, besides being a 
regular I/O pin, has two alternate functions. It can be programmed: 

1 . to input the external clock for Timer/Counter 2, or 

2. to output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 
1 6MHz operating frequency. 

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in 
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit 
TR2 (T2CON.2) also must be set to start the timer. 

The Clock-Out frequency depends on the oscillator frequency and 
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) 
as shown in this equation: 




In the Clock-Out mode Timer 2 roll-overs will not generate an 
interrupt. This is similar to when it is used as a baud-rate generator. 
It is possible to use Timer 2 as a baud-rate generator and a clock 
generator simultaneously. Note, however, that the baud-rate and the 
Clock-Out frequency will be the same. 



6. External Pin Status During Idle and Power-Down Mode 



MODE 


PROGRAM 
MEMORY 


ALE 


PSEN 


PORT 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Float 


Data 


Data 


Data 



1996 Aug 16 



3-37 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



Programmable Counter Array (PCA) 

The Programmable Counter Array is a special Timer that has five 
16-bit capture/compare modules associated with it. Each of the 
modules can be programmed to operate in one of four modes: rising 
and/or falling edge capture, software timer, high-speed output, or 
pulse width modulator. Each module has a pin associated with it in 
port 1 . Module is connected to P1 .3(CEX0), module 1 to 
P1 .4(CEX1 ), etc. The basic PCA configuration is shown in Figure 7. 

The PCA timer is a common time base for all five modules and can 
be programmed to run at: 1/12 the oscillator frequency, 1/4 the 
oscillator frequency, the Timer overflow, or the input on the ECI pin 
(P1 .2). The timer count source is determined from the CPS1 and 
CPSO bits in the CMOD SFR as follows (see Figure 10): 

CPS1 CPSO PCA Tinier Count Source 

1/1 2 oscillator frequency 

1 1/4 oscillator frequency 

1 Timer overflow 

1 1 External Input at ECI pin 

In the CMOD SFR are three additional bits associated with the PCA. 
They are CIDL which allows the PCA to stop during idle mode, 
WDTE which enables or disables the watchdog function on 
module 4, and ECF which when set causes an interrupt and the 
PCA overflow flag CF (in the CCON SFR) to be set when the PCA 
timer overflows. These functions are shown in Figure 8. 

The watchdog timer function is implemented in module 4 (see 
Figure 17). 

The CCON SFR contains the run control bit for the PCA and the 
flags for the PCA timer (CF) and each module (refer to Figure 11). 
To run the PCA the CR bit (CCON.6) must be set by software. The 
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when 
the PCA counter overflows and an interrupt will be generated if the 
ECF bit in the CMOD register is set, The CF bit can only be cleared 



by software. Bits through 4 of the CCON register are the flags for 
the modules (bit for module 0, bit 1 for module 1 , etc.) and are set 
by hardware when either a match or a capture occurs. These flags 
also can only be cleared by software. The PCA interrupt system 
shown in Figure 9. 

Each module in the PCA has a special function register associated 
with it. These registers are: CCAPMO for module 0, CCAPM1 for 
module 1 , etc. (see Figure 12). The registers contain the bits that 
control the mode that each module will operate in. The ECCF bit 
(CCAPMn.O where n=0, 1 , 2, 3, or 4 depending on the module) 
enables the CCF flag in the CCON SFR to generate an interrupt 
when a match or compare occurs in the associated module. PWM 
(CCAPMn. 1 ) enables the pulse width modulation mode. The TOG 
bit (CCAPMn.2) when set causes the CEX output associated with 
the module to toggle when there is a match between the PCA 
counter and the module's capture/compare register. The match bit 
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON 
register to be set when there is a match between the PCA counter 
and the module's capture/compare register. 

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) 
determine the edge that a capture input will be active on. The CAPN 
bit enables the negative edge, and the CAPP bit enables the 
positive edge. If both bits are set both edges will be enabled and a 
capture will occur for either transition. The last bit in the register 
ECOM (CCAPMn.6) when set enables the comparator function. 
Figure 1 3 shows the CCAPMn settings for the various PCA 
functions. 

There are two additional registers associated with each of the PCA 
modules. They are CCAPnH and CCAPnL and these are the 
registers that store the 1 6-bit count when a capture occurs or a 
compare should occur. When a module is used in the PWM mode 
these registers are used to control the duty cycle of the output. 



PCA TIMER/COUNTER 



16 BITS 




MODULE 





TIME BASE FOR PCA MODULES 

MODULE FUNCTIONS: 
16-BIT CAPTURE 
16-BIT TIMER 

16-BIT HIGH SPEED OUTPUT 
8-BIT PWM 

WATCHDOG TIMER (MODULE 4 ONLY) 



■Q P1.3/CEX0 
P1.4/CEX1 
P1.5/CEX2 
-f~| P1.6/CEX3 



P1.7/CEX4 











Figure 7. Programmable Counter Array (PCA) 



1996 Aug 16 



3-38 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 83C5 1 1 rc/SOCsffS 



TIMER 
OVERFLOW 



EXTERNAL INPUT ■— i 
(P1.2/ECI) L_l 








F=^> 



TOPCA 
MODULES 



16-BIT UP COUNTER 



CIDL 


WDTE 








CPS1 


CPSO 


EOF 


I 


I 


CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



CMOD 
(D9H) 



CCON 
(D8H) 



PCA TIMER/COUNTER 



MODULE 2 




JO [ ECF [ 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 




CCON 
(D8H) 



INTERRUPT 

PRIORITY 

DECODER 



Figure 9. PCA Interrupt System 



1996 Aug 16 



3-39 



Philips Semiconductors 



Product specification 



. o ^ . • „ 83C51FA/83C51FB/ 

CMOS single-chip 8-bit microcontrollers 83C51 FC/80C51 FA 



CMOD Address = OD9H 
Bit Addressable 



Reset Value = OOXX X000B 



CIDL 


WDTE 








CPS1 


CPSO 


ECF 


7 

ction 


6 


5 


4 


3 




1 






CIDL 



WDTE 



CPS1 
CPSO 



ECF 



Counter Idle control: CIDL = programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs 
it to be gated off during idle. 

Watchdog Timer Enable: WDTE = disables Watchdog Tims 
Not implemented, reserved for future use.* 
PCA Count Pulse Select bit 1 . 



PCA Count Pulse Select bit 0. 
CPS1 CPSO Selected PCA Input" 

Internal clock, f sc + 12 

1 1 Internal clock, fosc * 4 

1 2 Timer overflow 

1 1 3 External clock at ECI/P1 .2 pin (max. rate = fosc < 



PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = disables 
that function of CF. 



User software should not write 1s to reserved bits. These bits may be used in future & 
new bit will be 0. and its active value will be 1. The value read from a reserved bit is in 
lose = oscillator frequency 



Figure 10. CMOD: PCA Counter Mode Register 





CCON Address = OD8H 

Bit Addressable 



Reset Value = 00X0 0000B 





CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCF0 


Bit: 


7 


6 


5 


4 


3 


2 


1 





Symbol Function 

















CF 
CR 



CCF4 
CCF3 
CCF2 
CCF1 
CCF0 

NOTE: 



PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is 
set. CF may be set by either hardware or software but can only be cleared by software. 

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA 
counter off. 

Not implemented, reserved for future use". 

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 



User software should nol write 1 s 10 reserved bits. These bits may be used in future 8051 family products to invoke new 
new bit will be 0, and its active value will be 1 . The value read from a reserved bit is indeterminate. 



In that case, the reset or inactive value of the 



Figure 11. CCON: PCA Counter Control Register 







1996 Aug 16 



3-40 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers 83C5 1 1 rc/SOCsffS 



CCAPMn Address CCAPMO ODAH 

CCAPM1 ODBH 

CCAPM2 ODCH 

CCAPM3 ODDH 

CCAPM4 ODEH 

Not Bit Addressable 



Reset Value = X000 0000B 







ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 


Bit: 7 
Symbol Function 


6 


5 


4 


3 


2 


1 






ECOMn 
CAPPn 
CAPNn 
MATn 

TOGn 

PWMn 
ECCFn 



Not implemented, reserved for future use*. 
Enable Comparator. ECOMn = 1 enables the comparator function. 
Capture Positive, CAPPn = 1 enables positive edge capture. 
Capture Negative, CAPNn = 1 enables negative edge capture. 
Match. When MATn = 1 , a match of the PCA counter with this module's compan 



fit, flagging an interrupt. 
Toggle. When TOGn = 1 , a match of the PCA counter with this module's 
pin to toggle. 

Pulse Width Modulation Mode. PWMn = 1 enables the 
Enable CCF interrupt. Enables compare/capture flag CCFn 




ire register causes the CCFn bit 
register causes the CEXn 



l modulated output. 
> generate an interrupt. 



"User software should not write 1 s to reserved bits. These bits may be used in future 8051 family products to invoke new fealures. In that case, the reset or inactive value of the n 
bit will be 0. and its active value will be 1 . The value read from a reserved bit is indeterminate. 



Figure 12. CCAPMn: PCA Modules Compare/Capture Registers 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 


MODULE FUNCTION 


X 























No operation 


X 


X 


1 














X 


1 6-bit capture by a positive-edge trigger on CEXn 


X 


X 





1 











X 


16-bit capture by a negative trigger on CEXn 


X 


X 


1 


1 











X 


1 6-bit capture by a transition on CEXn 


X 


1 








1 








X 


1 6-bit Software Timer 


X 


1 








1 


1 





X 


16-bit High Speed Output 


X 


1 














1 





8-bit PWM 


X 


1 








1 


X 





X 


Watchdog Timer 



Figure 13. PCA Module Modes (CCAPMn Register) 



PCA Capture Mode 

To use one of the PCA modules in the capture mode either one or 
both of the CCAPM bits CAPN and CAPP for that module must be 
set. The external CEX input for the module (on port 1 ) is sampled for 
a transition. When a valid transition occurs the PCA hardware loads 
the value of the PCA counter registers (CH and CL) into the 
module's capture registers (CCAPnL and CCAPnH). If the CCFn bit 
for the module in the CCON SFR and the ECCFn bit in the CCAPMn 
SFR are set then an interrupt will be generated. Refer to Figure 14. 

16-bit Software Timer Mode 

The PCA modules can be used as software timers by setting both 
the ECOM and MAT bits in the modules CCAPMn register. The PCA 
timer will be compared to the module's capture registers and when a 
match occurs an interrupt will occur if the CCFn (CCON SFR) and 
the ECCFn (CCAPMn SFR) bits for the module are both set (see 
Figure 15). 



High Speed Output Mode 

In this mode the CEX output (on port 1) associated with the PCA 
module will toggle each time a match occurs between the PCA 
counter and the module's capture registers. To activate this mode 
the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must 
be set (see Figure 16). 

Pulse Width Modulator Mode 

All of the PCA modules can be used as PWM outputs. Figure 17 
shows the PWM function. The frequency of the output depends on 
the source for the PCA timer. All of the modules will have the same 
frequency of output because they all share the PCA timer. The duty 
cycle of each module is independently variable using the module's 
capture register CCAPLn. When the value of the PCA CL SFR is 
less than the value in the module's CCAPLn SFR the output will be 
low, when it is equal to or greater than the output will be high. When 
CL overflows from FF to 00, CCAPLn is reloaded with the value in 
CCAPHn. the allows updating the PWM without glitches. The PWM 
and ECOM bits in the module's CCAPMn register must be set to 
enable the PWM mode. 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 83C51 rc/8(X?51F7\ 



CF 


OR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 







CCON 
(D8H) 



CEXn fj- 



(TOCCFn) 



CAPTURE 



PCA INTERRUPT 



PCA TIMER/COUNTER 







CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 





















In, n= to 4 
IAH - DEH) 



Figure 14. PCA Capture Mode 



WRITE TO 
CCAPnH RESET 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



















CCON 
(D8H) 



WRITE TO 
CCAPnL 



CCAPnH 


CCAP " L (TOCCFn) 









1&-BIT COMPARATOR 























CH 


CL 



PCA TIMER/COUNTER 



E 



PCA INTERRUPT 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




t 



















CCAPMn, n= to 4 
(DAH - DEH) 



Figure 15. PCA Compare Mode 



1996 Aug 16 



3-42 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers oo^J^i 3 ^!?/ 



WRITE TO 
CCAPnH RESET 



CP 


CR 1 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 













CCON 
(D8H) 



WRITE TO 
CCAPnL 





1 


CCAPnH 


CCAPnL 



1 \ 







a 



16-BIT COMPARATOR 













CH 


0. 



(TO CCFn) 



i c<3 



PCA INTERRUPT 



«0 CEXn 



PCA TIMER/COUNTER 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 




ECCFn 




t 










1 






CCAPMn, n: .4 
(DAH-DEH) 



Figure 16. PCA High Speed Output Mode 




□ 



8-BIT 
COMPARATOR 



7> 



CL >= CCAPnL 



»Q CEXn 



PCA TIMER/COUNTER 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 



(DAH-DEH) 



Figure 17. PCA PWM Mode 



1996 Aug 16 



3-43 



Philips Semiconductors 



Product specification 



5-bit microcontrollers 



83C51FA/83C5 
-31FC/80G 



CIDL 


WDTE 








CPS1 


CPSO 


ECF 




















CMOD 
(D9H) 



WRITE TO 
CCAP4H 




_ 



CCAP4H 


CCAP4L 


- 







16-BIT COMPARATOR 

"7^ 



— ^ PS ► RESET 



PCA TIMER/COUNTER 



EI 



CCAPM4 
(DEH) 



Enhanced UART 

The UART operates in all of the usual modes that are described in 
the first section of Dafa Handbook IC20, 80C51 -Based 8-Bit 
Microcontrollers. In addition the UART can perform framing error 
detect by looking for missing stop bits, and automatic address 
recognition. The 8XC51 FA/83C51 FB UART also fully supports 
multiprocessor communication as does the standard 80C51 UART. 

When used for framing error detect the UART looks for missing stop 
bits in the communication. A missing bit will set the FE bit in the 
SCON register. The FE bit shares the SCON.7 bit with SMO and the 
function of SCON.7 is determined by PCON.6 (SMODO) (see 
Figure 19). If SMODO is set then SCON.7 functions as FE. SCON.7 
functions as SMO when SMODO is cleared. When used as FE 
SCON.7 can only be cleared by software. Refer to Figure 20. 



Timer 

Mode is the Shift Register mode and SM2 is ignored. 

Using the Automatic Address Recognition feature allows a master to 
selectively communicate with one or more slaves by invoking the 
Given slave address or addresses. All of the slaves may be 
contacted by using the Broadcast address. Two special Function 
Registers are used to define the slave's address, SADDR, and the 
address mask, SADEN. SADEN is used to define which bits in the 
SADDR are to b used and which bits are "don't care". The SADEN 
mask can be logically ANDed with the SADDR to create the "IGiven" 
address which the master will use for addressing each of the slaves. 
Use of the Given address allows multiple slaves to be recognized 
while excluding others. The following examples will help to show the 
versatility of this scheme: 



Automatic Address Recognition 

Automatic Address Recognition is a feature which allows the UART 
to recognize certain addresses in the serial bit stream by using 
hardware to make the comparisons. This feature saves a great deal 
of software overhead by eliminating the need for the software to 
examine every serial address which passes by the serial port. This 
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART 
modes, mode 2 and mode 3, the Receive Interrupt flag (Rl) will be 
automatically set when the received byte contains either the "Given" 
address or the "Broadcast" address. The 9 bit mode requires that 
the 9th information bit is a 1 to indicate that the received information 
is an address and not data. Automatic address recognition is shown 
in Figure 21. 

The 8 bit mode is called Mode 1 . In this mode the Rl flag will be set 
if SM2 is enabled and the information received has a valid stop bit 
following the 8 address bits and the information is either a Given or 
Broadcast address. 



Slave 



SADDR = 

SADEN = 

Given = 

SADDR = 

SADEN = 

Given = 



1100 0000 
1111 110 1 
1100 00X0 

1100 0000 

mi mo 



1100 ooox 

In the above example SADDR is the same and the SADEN data is 
used to differentiate between the two slaves. Slave requires a in 
bit and it ignores bit 1 . Slave 1 requires a in bit 1 and bit is 
ignored. A unique address for Slave would be 1100 0010 since 
slave 1 requires a in bit 1 . A unique address for slave 1 would be 
1100 0001 since a 1 in bit will exclude slave 0. Both slaves can be 
selected at the same time by an address which has bit = (for 
slave 0) and bit 1 = (for slave 1). Thus, both could be addressed 
with 1100 0000. 



1996 Aug 16 



3-44 



Philips Semiconductors 



CMOS single-chip 8-bit microcontrollers 



Product specification 

83C51 FA/83C51 FB/ 
83C51FC/80C51FA 



slaves 1 and 2 while exc 


udinc 


slave 0: 


Slave 


SADDR 




1100 0000 




SADEN 


= 


1111 1001 




Given 




1100 OXXO 


Slave 1 


SADDR 




1110 0000 




SADEN 




1111 1010 




Given 




1110 oxox 


Slave 2 


SADDR 




1110 0000 




SADEN 




1111 1100 




Given 




1110 ooxx 



In the above example the differentiation among the 3 slaves is in the 
lower 3 address bits. Slave requires that bit = and it can be 
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = and 



it can be uniquely addressed by 1110 and 0101 . Slave 2 requires 
that bit 2 = and its unique address is 1 1 1 001 1 . To select Slaves 
and 1 and exclude Slave 2 use address 1110 0100, since it is 
necessary t make bit 2 = 1 to exclude slave 2. 

The Broadcast Address for each slave is created by taking the 
logical OR of SADDR and SADEN. Zeros in this result are teated as 
don't-cares. In most cases, interpreting the don't-cares as ones, the 
broadcast address will be FF hexadecimal. 

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR 
address 0B9H) are leaded with 0s. This produces a given address 
of all "don't cares" as well as a Broadcast address of all "don't 
cares", this effectively disables the Automatic Addressing mode and 
allows the microcontroller to use standard 80C51 type UART drivers 
which do not make use of this feature. 







SCON Address = 98H 
Bit Addressable 



Reset Value = 0000 0OOOB 



SM0/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


7 


6 


5 


4 


3 


2 


1 






Symbol 



Bit: 

(SMOD0 = 0/1)* 
Function 



FE 



SMO 
SM1 



SM2 



REN 
TB8 
RB8 

Tl 

Rl 



Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid 
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. 

Serial Port Mode Bit 0, (SMOD0 must = to access bit SMO) 

Serial Port Mode Bit 1 



SMO 


SM1 


Mode 


Description 


Baud Rate" 











shift register 


fosc/12 





1 


1 


8-bit UART 


variable 


1 





2 


9-bit UART 


foso/64 or fosc/32 


1 


1 


3 


9-bit UART 


variable 



Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the 
received 9th data bit (RB8) is 1 , indicating an address, and the received byte is a Given or Broadcast Address. 
In Mode 1 , if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a 
Given or Broadcast Address. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In modes 2 and 3, the 9th data bit that was received. In Mode 1 , if SM2 = 0, RB8 is the stop bit that was received. 
In Mode 0, RB8 is not used. 

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the 
other modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in 
the other modes, in any serial reception (except see SM2). Must be cleared by software. 



NOTE: 

•SMODO is located at PCON6. 
" f osc = oscillator frequency 



Figure 19. SCON: Serial Port Control Register 



1996 Aug 16 



3-45 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 83C51 rc/awSf^ 





DO y\ 02 D3 D4 ^ 


C 05 / 


^ D6^^ D7^ 


X 08 / 












START 
BIT 


DATA BYTE 




— 


ONLY IN 
MODE 2, 3 


STOP 
BIT 



SET FE BIT IF STOP BIT IS (FRAMING ERROR) 
SMO TO UART MODE CONTROL 



SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 






SMOD1 


SMODO 


OSF 


POF 


LVF 


GFO 


GFI 


IDL 



PCON 
(87H) 



: SCON.7 = SMO 

1 :SCON.7 = FE 



Figure 20. UART Framing Error Detection 



I o 



SMO 


SM1 


SM2 


REN 


TBS 


RB8 


Tl 


Rl 



RECEIVED ADDRESS DO TO D7 
PROGRAMMED ADDRESS 



COMPARATOR 



IN UART MODE 2 OR MODE 3 AND SM2 = 1: 

INTERRUPT IF REN=1 , RBS=1 AND 'RECEIVED ADDRESS" a "PROGRAMMED ADDRESS" 

- WHEN ALL DATA BYT Is^AV^BEEN^EraiVED^T TO WAIT FOR NEXT ADDRESS. 



SCON 
(9BH) 



Figure 21. UART Multiprocessor Communication, Automatic Address Recognition 

- 



1996 Aug 16 



3-46 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers 83C5 1 1 rc/SOCSIlS 



Interrupt Priority Structure 

The 8XC51 FA/FB has a 7-source t 
There are 3 SFRs associated with the interrupts on the 
8XC51 FA/FB. They are the IE and IP. (See Figures 22 and 23.) In 
addition, there is the IPH (Interrupt Priority High) register that makes 
the four-level interrupt structure possible. The IPH is located at SFR 
address B7H. The structure of the IPH register and a description of 
its bits is shown below: 

IPH (Interrupt Priority High) (B7H) 

7 6 5 4 3 2 1 

| - | PPCH | PT2H | PSH | PT1H | PX1H | PTOH | PXOH | 

External interrupt priority high 
Timer interrupt priority high 
External interrupt 1 priority high 
Timer 1 interrupt priority high 
Serial Port interrupt high 
Timer 2 interrupt priority high 
PCA interrupt priority high 
Not implemented 

The function of the IPH SFR is simple and when combined with the 
IP SFR determines the priority of each interrupt. The priority of each 
interrupt is determined as shown in the following table: 



IPH.O 


PXOH 


IPH.1 


PTOH 


IPH.2 


PX1H 


IPH.3 


PT1H 


IPH.4 


PSH 


IPH.5 


PT2H 


IPH.6 


PPCH 


IPH.7 











PRIORITY BITS 


IN" 


rERRUPT PRIORITY LEVEL 


IPH.x 


IP.X 








Level (lowest priority) 





1 


Level 1 


1 





Level 2 


1 


1 


Level 3 (highest priority) 



The priority scheme for servicing the interrupts is the same as that 
for the 80C51 , except there are four interrupt levels on the 8XC51 FX 
rather than two as on the 80C51 . An interrupt will be serviced as 
long as an interrupt of equal or higher priority is not already being 
serviced. If an interrupt of equal or higher level priority is being 
serviced, the new interrupt will wait until it is finished before being 
serviced. If a lower priority level interrupt is being serviced, it will be 
stopped and the new interrupt serviced. When the new interrupt is 
finished, the lower priority level interrupt that was stopped will be 
completed. 



Table 7. Interrupt Table 



SOURCE 


POLLING PRIORITY 


REQUEST BITS 


HARDWARE CLEAR? 


VECTOR ADDRESS 


xo 


1 


IE0 


N(L) 1 Y(T)2 


03H 


TO 


2 


TPO 


Y 


OBH 


X1 


3 


IE1 


N(L) Y(T) 


13H 


T1 


4 


TF1 


Y 


1BH 


SP 


5 


R1.TI 


N 


23H 


T2 


6 


TF2, EXF2 


N 


2BH 


PCA 


7 


CF, CCFn 
n = 0-4 


N 


33H 



NOTES: 

1 . L = Level activated 

2. T = Transition activated 



1996 Aug 16 



3-47 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51 FC/80C51 FA 



7 


6 


5 


4 


3 


2 


1 





EA 


EC 


ET2 


ES 


ET1 


EX1 


ETO 


EXO 



: (0A8H) 



Enable Bit = 1 enables the interrupt. 
Enable Bit = disables it. 



BIT 


SYMBOL 


FUNCTION 




IE.7 


EA 


Global disable bit. If EA = 0, all interrupts are disabled. If EA = 


1 , each interrupt can be individually 






enabled or disabled by setting or clearing its enable bit. 


IE.6 


EC 


PCA interrupt enable bit. 




IE.5 


ET2 


Timer 2 interrupt enable bit. 




IE.4 


ES 


Serial Port interrupt enable bit. 




IE.3 


ET1 


Timer 1 interrupt enable bit. 




IE.2 


EX1 


External interrupt 1 enable bit. 




IE.1 


ETO 


Timer interrupt enable bit. 




IE.0 


EXO 


External interrupt enable bit. 











Figure 22. 


IE Registers 








7 


6 


5 


4 


3 


2 


1 





IP (OBSH) 




PPC 


PT2 


PS 


PT1 

' 


PX1 



PTO 


PXO 



SU00S71 



Priority Bit = 1 assigns high priority 
Priority Bit = assigns low priority 



BIT 


SYMBOL 


FUNCTION 


IP.7 




Not implemented, reserved for future use. 


IP.6 


PPC 


PCA interrupt priority bit. 


IP.5 


PT2 


Timer 2 interrupt priority bit. 


IP.4 


PS 


Serial Port interrupt priority bit. 


IP.3 


PT1 


Timer 1 interrupt priority bit. 


IP.2 


PX1 


External interrupt 1 priority bit. 


IP.1 


PTO 


Timer interrupt priority bit. 


IP.O 


PXO 


External interrupt priority bit. 



Figure 23. IP Registers 



1996 Aug 16 



3-48 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



Reduced EMI Mode 

The AO bit (AUXR.O) in the AUXR register when set disables the 
ALE output. 

8XC51FA/83C51FB/83C51FC Reduced EMI Mode 
AUXR (8EH) 



I - I - I 



I - I - I - I 



AO: Turns off ALE output. 



u 


1 
t 






DPTRl 
DPTRO 






1 




Figure 24. 



Dual DPTR 

The dual DPTR structure (see Figure 24) is a way by which the 
83C51 FA, 83C51FB, and 83C51 FC will specify the address of an 
external data memory location. ("NOTE: not available on 80C51 FA 
[ROMIess] at this time.) There are two 16-bit DPTR registers that 
dress the external memory, and a single bit called DPS = 
R1/bit0 that allows the program code to switch between them. 

I New Register Name: AUXR1# 

> SFR Address: A2H 

> Reset Value: xxxxxxxOB 

7 6 5 

n 



3 



Where: 

DPS = AUXR1/bitO = Switches between DPTRO and DPTR1 



DPTR Instructions 

The instructions that refer to DPTR refer to the data pointer that is 
currently selected using the AUXR1/bit register. The six 
instructions that use the DPTR are as follows: 

INC DPTR Increments the data pointer by 1 

MOV DPTR, #data16 Loads the DPTR with a 16-bit constant 
MOV A, @ A+DPTR Move code byte relative to DPTR to 

MOVX A, 6 DPTR Move external RAM (16-bit address) to 
ACC 

Move ACC to external RAM (16-bit 
address) 

Jump indirect relative to DPTR 




JMP @ A + DPTR 



Select Reg 
DPTRO 
DPTR1 



DPS 

1 



The data pointer can be accessed on a byte-by-byte basis be 
specifying the Low or High byte in an instruction which accesses the 
l note AN458 for more details. 



The DPS bit status should be saved by software when switching 
between DPTRO and DPTR1 . 



ABSOLUTE MAXIMUM RATINGS 1 2 3 





PARAMETER 


RATING 


UNIT 


Operating temperature under bias 




Oto+70 or -40 to +85 


°C 


Storage temperature range 




-65 to +150 


°c 


Voltage on EATVpp pin to V ss 


to +13.0 


V 


Voltage on any other pin to V ss 


-0.5 to +6.5 


V 


Maximum Iol per I/O pin 


15 


mA 


Power dissipation (based on package heat transfer limitations, not device power consumption) 


1.5 


w 



NOTES: 



1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V ss unless otherwise 
noted. 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



DC ELECTRICAL CHARACTERISTICS 

Tamb = °°C to +70°C or -40°C to +85°C, V cc = 2.7V to 5.5V ±1 0%, V S s = 0V; (-4 and -5 devices; 1 6MHz devices except S80C51 FA [ROMIess]) 



SYMBOL 


PARAMETER 


TEST 


LIMITS 


UNIT 


CONDITIONS 


MIN 


TYP 1 


MAX 






Input low voltage 


t.uv < vcc >J,OV 


-0.5 




0.2V CC -0.1 


y 




2.7V<V CC < 4.0V 


-0.5 




0.7 


V 


VlH 


Input high voltage (ports 0,1,2, 3, EA") 




0.2V cc +0.9 




Vcc+0.5 


V 


V W 1 


Input high voltage, XTAL1 , RST 




7V,~,~ 
vcc 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 8 


V cc = 2.7V 
I l= 16mA 2 






0.4 


V 


Von 


Output low voltage, port 0, ALE, PSEN 8 . 7 



V cc = 2.7V 
Iol = 3.2mA 2 






0.4 


V 


VOH 


Hi itni it hinh wnltano nnrtc 1 9 ^ J 

uuipui nign voltage, puf lb i , o 


V cc = 2.7V 
l OH = -20uA 


V C C - 0.7 






V 


Vcc = 4.5V 
Ioh = -30nA 


V CC "0.7 






V 


v OH1 




Output high voltage (port in external bus mode), 
ALE 9 , P5ER 3 


V CC = 2.7V 
l H = -3.2mA 


V CC -0.7 






v 


k. 


Logical input current, ports 1,2,3 


V, N = 0.4V 


-1 




-50 


HA 


Itl 


Logical 1-to-0 transition current, ports 1, 2, 3 6 


V| N = 2.0V 
See note 4 






-650 


uA 


'LI 


Input leakage current, port 


U.^O < V |fg < Vcc U.o 






±10 


UA 


Ice 


Power supply current (see Figure 32): 
Active mode @ 16MHz 
83C51FA/FB/FC 
80C51 FA 


See note 5 






15 
32 


mA 
mA 




Idle mode @ 16MHz 
83C51 FA/FB/FC 
80C51FA 








4 

5 


mA 
mA 




Power-down mode 


T amb = 0°Cto70°C 
Tamb = "40°C to +85°C 




3 


50 
75 


uA 
uA 


Rrst 


Internal reset pull-down resistor 




40 




225 


kft 


Cio 


Pin capacitance 10 (except EA") 








15 


PF 



NOTES: 



1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the V OL s of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1 -to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 1 0OpF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Iol can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs exceed the test conditions. 

3. Capacitive loading on ports and 2 may cause the V 0H on ALE and PSEN to momentarily fall below the V cc -0.7 specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V|n is approximately 2V. 

5. See Figures 33 through 36 for l cc test conditions. 

Active mode: l cc = 0.9 x FREQ. + 1.1mA 

Idle mode: l cc = 0.18 x FREQ. +1 ,01mA; See Figure 32. 

6. This value applies to Tamb = 0°C to +70°C For T^ = -40°C to +85°C, l TL = -750uA. 

7. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

8. Under steady state (non-transient) conditions, Iol must be externally limited as follows: 

Maximum I l per port pin: 1 5mA ("NOTE: This is 85°C specification.) 

Maximum I l per 8-bit port: 26mA 

Maximum total I l f °r all outputs: 71 mA 
If Iol exceeds the test condition, V 0L may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

9. ALE is tested to V 0H i , except when ALE is off then V h is the voltage specification. 

10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF 
(except EA is 25pF). 



83C51FA/83C51FB/ 
83C51 FC/80C51 FA 



1996 Aug 16 



3-50 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51 FA/83C51 FB/ 
83C51FC/80C51FA 



DC ELECTRICAL CHARACTERISTICS 

Tamb = °° c >° + 70 ° c °' -*°° c 10 +85"C, (-A, -B, -I, and -J devices; S80C51 FA -4, -5); 5V ±10%; V s 



= 0V 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 


V| L 


Input low voltage 


4.5V < V cc < 5.5V 


-0.5 




0.2V CC -0.1 


V 


V|H 


Input high voltage (ports 0, 1 , 2, 3, EA) 




0.2V cc +0-9 




Vcc+0.5 


V 


V,H1 


Input high voltage, XTAL1 , RST 




0.7V CC 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 3 8 


Vcc = 4.5V 
l L= 1.6mA 2 






0.4 


V 


V L1 


Output low voltage, port 0, ALE, F5ER * 8 


V CC = 4.5V 
l 0L = 3.2mA 2 






0.4 


V 




uuipui nign vouage, pons i , j 


V CC = 4.5V 
I h = -30|iA 


Vcc -0.7 






V 


V H1 


ALE 9 , P5EN 3 


V CC = 4.5V 
Ioh = -3.2mA 


V CC - 0.7 






V 


IlL 


Logical input current, ports 1 , 2, 3 


V, N = 0.4V 


-1 




-50 


uA 


Itl 


Logical 1 -to-0 transition current, ports 1 , 2, 3 6 


V| N = 2.0V 
See note 4 






-650 


uA 


Ili 


Input leakage current, port 


0.45 < V, N < V cc - 0.3 






±10 


uA 


Ice 


Power supply current (see Figure 32): 
Active mode @ 16MHz 5 
Idle mode @ 16MHz 5 
Power-down mode 


See note 5 

Tamb=0°Cto70°C 
Tamb = ^>0°C to +85°C 




3 


15 
4 
50 
75 


(iA 
(iA 
HA 
HA 


Rrst 


Internal reset pull-down resistor 




40 




225 


kn 


Cio 


Pin capacitance 10 (except EA) 








15 


PF 



1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the Vols of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1 -to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 1 0OpF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Iol can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs ex ceed th e test conditions. 

3. Capacitive loading on ports and 2 may cause the Voh on ALE and PSEN to momentarily fall below the Vcc-0.7 specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 

5. See Figures 33 through 36 for Ice lest conditions. 

Active mode: l C c = 0.9 x FREQ. + 1 .1 mA 
Idle mode: Ice = 0.18 x FREQ. +1.0mA; See Figure 32. 

6. This value applies to Tamb = 0°C to +7 0°C. Fo r T^b = -40°C to +85°C, Itl = -750uA. 

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

8. Under steady state (non-transient) conditions, Iol must be externally limited as follows: 

Maximum Iql per port pin: 15mA (*NOTE: This is 85°C specification.) 

Maximum Iql per 8-bit port: 26mA 

Maximum total Iol for all outputs: 71 mA 
If Iol exceeds the test condition, V l may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

9. ALE is tested to V m , except when ALE is off then Voh is the voltage specification. 

1 0. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 1 5pF 
(except EA is 25pF). 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to +85°C, V oc = +2.7V to +5.5V (except S80C51FA V cc = 5.0V ±10%), V ss = 0V 1 ' 2 ' 3 









16MHz CLOCK 


VARIABLE CLOCK 




SYMBOL 


FIGURE 


PARAMETER 


MIN 


MAX 


MIN 


MAX 


UNIT 


1 /tcLCL 


25 


Oscillator frequency 

Speed versions : 4; 5 






3.5 


16 


MHz 


tLHLL 


25 


ALE pulse width 


85 




21CLCL-40 




ns 


tAVLL 


25 


Address valid to ALE low 


22 




tcLCL^O 




ns 


t|_LAX 


25 


Address hold after ALE low 


32 




tCLCL-30 




ns 


•lliv 


25 


ALE low to valid instruction in 




150 




4tcLCL"100 


ns 


*LLPL 


25 


ALE low to P5ETC low 


32 




tCLCL-30 




ns 


tpLPH 


25 


PSEN pulse width 


142 




3tcLCL-^5 




ns 


tpuv 


25 


PSEN low to valid instruction in 




82 




3tcLCL"105 


ns 


tpxix 


25 


Input instruction hold after PSEN 












ns 


<PXIZ 


25 


Input instruction float after PSEN 




37 




tcLCL-25 


ns 


Wiv 


25 


Address to valid instruction in 




207 




5tcLCL-105 


ns 


tpuc 


25 


PSEN low to address float 




10 




10 


ns 


Data Memc 
















•rlrh 


26, 27 


RD pulse width 


275 




6ICUCL-100 




ns 


•WLWH 


26, 27 


WR pulse width 


275 




6tcLCL~100 




ns 


'rldv 


26, 27 


RD low to valid data in 




147 




5t CLCL -165 


ns 


*RHDX 


26, 27 


Data hold after RD 












ns 


tRHDZ 


26, 27 


Data float after KB 




65 




2tcLCL"60 


ns 


tLLDV 


26,27 


ALE low to valid data in 




350 




8ta_CL-150 


ns 


•avdv 


26, 27 


Address to valid data in 




397 




9t CLC L-165 


ns 


*LLWL 


26, 27 


ALE low to RD or WR low 


137 


239 


3t C LCL-50 


3t C LCL+50 


ns 


tAVWL 


26, 27 


Address valid to WR low or RD low 


122 




4t CLCL -130 




ns 


Iqvwx 


26, 27 


Data valid to WR transition 


13 




tCLCL-50 




ns 


twHQX 


26, 27 


Data hold after WR 


13 




tcLCL-50 




ns 


(qvwh 


27 


Data valid to WR high 


287 




7ICLCL-150 




ns 


tRLAZ 


26, 27 


RD low to address float 












ns 


l WHLH 


26, 27 


RD or WR high to ALE high 


23 


103 


tcLCL-^>0 


tCLCL+40 


ns 


External Clock 


tcHCX 


29 


High time 


20 




20 


tCLCL-tCLCX 


ns 


l CLCX 


29 


Low time 


20 




20 


•cLCL-tCHCX 


ns 


tdCH 


29 


Rise time 




20 




20 


ns 


tCHCL 


29 


Fall time 




20 






ns 


Shift Register 












tXLXL 


28 


Serial port clock cycle time 


750 




1 2tcLCL 




ns 


toVXH 


28 


Output data setup to clock rising edge 


492 




10ICLCL-133 




ns 


txHQX 


28 


Output data hold after clock rising edge 


8 




2tCLCL-H7 




ns 


•xHDX 


28 


Input data hold after clock rising edge 












ns 


txHDV 


28 


Clock rising edge to input data valid 




492 




10tc LCL -133 


ns 



NOTES: 

1 . Parameters are valid over operating temperature range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 83C51 FA/FB/FC and 80C51 FA to devices with float times up to 45ns is permitted. This limited bus contention will not cause 
damage to Port drivers. 

4. See application note AN457 for external memory interface. 



83C51FA/83C51FB/ 
83C51 FC/80C51 FA 



1996 Aug 16 



3-52 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to +85°C, V cc = 5V ±10%, V SS = OV 1 ' 2 ' 3 



SYMBOL 


FIGURE 


PARAMETER 


24MHz CLOCK 


VARIABLE CLOCK 4 


33MHz CLOCK 


UNIT 


MIN 


MAX 


MIN 


MAX 


MIN 


MAX 


1 /tcLCL 


25 




Oscillator frequency 

Speed versions : A; B (24MHz) 
: I; J (33MHz) 


3.5 


24 


3 5 


33 


3.5 


33 


MHz 


(lhll 


25 


ALE pulse width 


43 




2tcLCL-40 






21 




ns 


*avll 


25 


Address valid to ALE low 


17 




•CLCL- 25 






5 




ns 


Illax 


25 


Address hold after ALE low 


17 




•cLCL-25 










ns 


Illiv 


25 


ALE low to valid instruction in 




102 




4tcLCL-65 




55 


ns 


'llpl 


25 


ALE low to PSEN low 


17 




tcLCL- 25 




5 




ns 


IPLPH 


25 


PSEN pulse width 


80 




3tCLCL~*5 




45 




ns 


tpLIV 


25 


PSEN low to valid instruction in 




65 




3tci_CL-60 




30 


ns 


tpxix 


25 


Input instruction hold after PSEN 

















ns 


tpxiz 


25 


Input instruction float after PSEN 




17 




tCLCL-25 




5 


ns 


Wiv 


25 


Address to valid instruction in 




128 




5tcLCL"80 




70 


ns 


tpLAZ 


25 


PSEN low to address float 




10 




10 




10 


ns 


Data Memory 


<rlrh 


26, 27 


RD pulse width | 150 




6t CLCL -100 




82 




ns 


twLWH 


26, 27 


WR pulse width | 150 




6t C LCL-100 




82 




ns 


tRLDV 


26, 27 


RD low to valid data in 




118 




5tcLCL-90 




60 


ns 


'rhdx 


26. 27 


Data hold after RD 

















ns 


Irhdz 


26, 27 


Data float after RD 




55 




2tci_CL-28 




32 


ns 


'lldv 


26, 27 


ALE low to valid data in 




183 




8tcLCL-150 




90 


ns 


Iavdv 


26, 27 


Address to valid data in 




210 




9t C LCL-165 




105 


ns 


tLLWL 


26, 27 


ALE low to RD or WR low 


75 


175 


3t C LCL-50 


3t C LCL+50 


40 


140 


ns 


<AVWL 


26, 27 


Address valid to WR low or RD low 


92 




4tcLCL-75 




45 




ns 


Iqvwx 


26, 27 


Data valid to WR transition 


12 




tcLCL-30 









ns 


*WHQX 


26, 27 


Data hold after WR 


17 




tcLCL-25 




5 




ns 


tQVWH 


27 


Data valid to WR high 


162 




7tcLCL-130 





80 




ns 


tRLAZ 


26, 27 


RD low to address float 



















ns 


tWHLH 


26, 27 


RDorWRhightoALE high 


17 


67 


t0LCL-25 


tcLCL 


+25 


5 


55 


ns 


External Clock 


•CHCX 


29 


High time 


17 




17 


'CLCL-'CLCX 






ns 


'CLCX 


29 


Low time 


17 




17 


tCLCL-'CHCX 






ns 


tcLCH 


29 


Rise time 




5 




5 






ns 


tCHCL 


29 


Fall time 




5 










ns 


Shift Register 


'XLXL 


28 


Serial port clock cycle time 


505 




12tcLCL 




360 




ns 


Iqvxh 


28 


Output data setup to clock rising edge 


283 




10tcLCL-133 




167 




ns 


tXHQX 


28 


Output data hold after clock rising edge 


3 




2t C LCL-80 








ns 


txHD> 


28 


Input data hold after clock rising edge 

















ns 


'XHDV 


28 


Clock rising edge to input data valid 




283 




10t cl _ cu -133 




167 


ns 



NOTES: 

1 . Parameters are valid over operating temperature range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpR load capacitance for all other outputs = 80pF. 

3. Interfacing the 83C51 FA/FB/FC and 80C51 FA to devices with float times up to 45ns is permitted. This limited bus contention will not cause 
damage to PortO drivers. 

4. Variable clock is specified for oscillator frequencies greater than 1 6MHz to 33MHz. For frequencies equal or less than 1 6MHz, see 1 6MHz 
"AC Electrial Characteristics", page 3-52. 



83C51FA/83C51FB/ 
83C51 FC/80C51 FA 



1996 Aug 16 



3-53 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers 83C5 1 1 rc/80C51 F ^ 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 
T (= time). The other characters, depending on their positions, 
indicate the name of a signal or the logical status of that signal. The 
designations are: 
A - Address 
C - Clock 
D - Input data 
H - Logic level high 

I - Instruction (program mp™™' n^aMA 
. - Logic level low, or ALE 



n — i_uyiu icvci uiyu «- ■ ■«« 

I - Instruction (program memory contents) Examples: 
L- Logic leve, low, or ALE 



P - P5ETC 
Q - Output data 
R - HD signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 



Wll = T ,me for address valid to ALE low. 
ty.PL =Time for ALE low to PS EN low. 



tLHLL 



x 



*AVLL 



y v 



'llpl 



tpLPH 



*LLIV ' 

tpLIV. 



tLLAX 



tpLAZ 



tAVIV 



'PXIX 



- tpxiz- 



A0-A15 




Figure 25. External 




Memory Read Cycle 



— 



<AVLL 



zx 



y 



t|_LDV 



'uwl 

— 



•llax 



A0-A7 
FROM Rl OR DPL 



'avwl 



tRLRH 



*RLDV 



tAVDV 



y 



'rhdx ■ 



tWHLH -*■ 



N / 



N / 



Irhdz. 



< ; DATA IN 



A0-A7 FROM PCL 



^ INSTR IN 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 



SU0002S 



Figure 26. External Data Memory Read Cycle 



1996 Aug 16 



3-54 



Philips Semiconductors 




Product specification 


CMOS single-chip 8-bit microcontrol 


lers 


83C51FA/83C51FB/ 


83C51FC/80C51FA 





tAVLL 



X 



*~ t WH LH 



'llwl 



U.LAX 



\ /' AO-A7 S v/ '' 

? V FROMRIORDPL A 



twLWH 



\ A 



tQVWX 



"\ / 



tAVWL 



tQVWH 



DATA OUT 



*~ tWHQX 



XX 



A0-A7 FROM PCL 



P2.0-P2.7 OR A6-A1 5 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 27. External Data Memory Write Cycle 



I 2 I 3 



OUTPUT DATA . 



•qvxh 



txHQX 



WRITI 



I ~**| \*~ 'XHDX 

tXHDV P *] | SET Tl 



I 

CLEAR Rl 



t 

SET Rl 



Figure 28. Shift Register Mode Timing 



VcC-05 
0.45V . 



r 0.7VCC 
0.2VOC-0-1 

tCHCL " 



~tcLCX~* 
*CLCL 



*-*CHCX-» 
tCLCH 



1996 Aug 16 



3-55 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers to£=V^?o,S? c \ F « 



vcc-05 




0.2VCC+0-9 




NOTE: 

AC inputs during testing are driven at V C c -0.5 tor a logic T and 0.45V tor a logic '0 
Timing measurements are made at V, H min tor a logic T and V, L max tor a logic '0' 



Figure 30. AC Testing Input/Output 




vload+o'v 



Vload - 



vload-o.iv 



TIMING 
REFERENCE 
POINTS 



>: 



Voh-0.1V 
Vql->0 IV 



NOTE: 

For timing purposes, a port is no longer floating when a 100mV change trom 
load voltage occurs, and begins to float when a 100mV change trom the loaded 
VohA/ol level occurs. lotV'oL ^ ±20mA. 

SU00718 

1 



Figure 31 . Float Waveform 



65 
60 
55 



ice 
mA 



80C51FA 



























ice 


MA 

MAX = 


X ACTI\ 
.5 X FR 


IE MOD 
EQ. + 8 


E 

/ 






































































































T 


CP ACT 


VEMO 




































































W 


X IDLE 


MODE_ 


















TYP IDLE M< 

I 


)DE 



4MHz 8MHz 12MHz 1' 

FREQ AT XT/ 



'cc 

mA 



83C51FA/FB/FC 











































I 


1 

x;MAX 


llAXAC 
= 0.9X 


WE M( 
=REQ. ^ 


>DE 

1.1 y/ 


















































TYP 


ACTIVE MODE 
















MAX IDLE MODE 














TYP IDLE MODE 





4MHz 8MHz t! 



KHz 20MHz 24MHz 28MHz 32MHz 36MHz 
3 AT XTAL1 



Figure 32. I cc vs. FREQ 
Valid only within frequency specifications of the device under test 



1996 Aug 16 



Philips Semiconductors Product specification 

~~~~~ L . . „ 83C51 FA/83C51 FB/ 

CMOS single-chip 8-bit microcontrollers 83C51 FC/80C51 FA 



(NO- 
CLOCK SIGNAL - 





Vcc 




PO 


RST 




EA 


XTAL2 




XTAL1 




Vss 





Ice 



- 



Figure 33. I cc Test Condition, Active Mode 
All other pins are disconnected 



<NC>- 
CLOCK SIGNAL - 





Vcc 


RST 






PO 




EA 


XTAL2 




XTAL1 




v ss 





Vcc 



Vcc 




VcC-0.5 
0.45V 



0.7VOO 
0.2V CC -0.1 

tCHGL" 



*-tcLcx-» 

tCLCL 



*-tcHCX"»- 
•CLCH 



35. Clock Signal Waveform for l cc Tests in 



tcLCH = «chcl = 5ns 



Vcc 



(NC)- 





Vcc 


RST 


PO 


XTAL2 




XTAL1 




vss 







Vcc 



Figure 36. I cc Test Condition, Power Down Mode 
All other pins are disconnected. V cc = 2V to 5.5V 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



83C51FA/83C51FB/ 
83C51FC/80C51FA 



Security Bits 

With none of the security bits programmed the code in the program 
memory can be verified. If the encryption table is programmed, the 
code will be encrypted when verified. When only security bit 1 (see 
Table 8) is programmed, MOVC instructions executed from external 
program memory are disabled from fetching code bytes from the 

Table 8. Program Security Bits 



internal memory, EA is latched on Reset and all further programming 
of the EPROM is disabled. When security bits 1 and 2 are 
programmed, in addition to the above, verify mode is disabled. 

Encryption Array 

64 bytes of encryption array are initially unprogrammed (all 1s). 



PROGRAM LOCK BITS 1 . 2 



SB1 



SB2 



PROTECTION DESCRIPTION 



No Program Security features enabled. 

(Code verify will still be encrypted by the Encryption Array if programmed.) 



U 



NOTES: 

1 . P - programmed. U - 

2. Any other combination c 



MOVC instructions executed from external program memory are disabled from fetching code bytes from 
internal memory, EA" is sampled and latched on Reset, and further programming of the EPROM is disabled. 



83C51FA ROM CODE SUBMISSION 

When submitting ROM code for the 83C51 

1. 8k byte user ROM data 

2. 64 byte ROM encryption key 

3. ROM security bits. 




must be specified: 



ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


OOOOHtolFFFH 


DATA 


7:0 


User ROM Data 


2000Hto201FH 


KEY 


7:0 


ROM Encryption Key 
FFH = no encryption 


2020H 


SEC 




ROM Security Bit 1 

= enable security 

1 = disable security 


2020H 


SEC 


1 


ROM Security Bit 2 

= enable security 

1 = disable security 



Security Bit 1 : When programmed, this bit has two effects on masked ROM parts: 

1 . External MOVC is disabled, and 

2. EA is latched on Reset. 

Security Bit 2: When programmed, this bit inhibits Verify User ROM. 



If the ROM Code file does not include the options, the following information must be included with the ROM code. 
For each of the following, check the appropriate box, and send to Philips along with the code: 



Security Bit #1: 


□ 


Enabled 


□ 


Disabled 


Security Bit #2: 


□ 


Enabled 


□ 


Disabled 


Encryption: 


□ 


No 


□ 


Yes If Yes, must send key file. 



1996 Aug 16 



3-58 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers rc/80C51FA 



83C51FB ROM CODE SUBMISSION 

When submitting ROM code for the 83C51 FB, the following must be specified: 

1 . 1 6k byte user ROM data 

2. 64 byte ROM encryption key 



3. ROM security bits. 



ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


0000H to 3FFFH 


DATA 


7:0 


User ROM Data 


4000Hto401FH 


KEY 


7:0 


ROM Encryption Key 
FFH = no encryption 


4020H 


SEC 





ROM Security Bit 1 

= enable security 

1 = disable security 


4020H 


SEC 


1 


ROM Security Bit 2 

= enable security 

1 = disable security 



Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 

1 . External MOVC is disabled, and 

2. EE is latched on Reset. 

Security Bit 2: When programmed, this bit inhibits Verify User ROM. 



If the ROM Code file does not include the options, the following information must be included with the ROM code. 
For each of the following, check the appropriate box, and send to Philips along with the code: 

Security Bit #1: □ Enabled □ Disabled 

Security Bit #2: □ Enabled □ Disabled 

Encryption: □ No □ Yes If Yes, must send key file. 



1996 Aug 16 



3-59 



83C51FC ROM CODE SUBMISSION 

When submitting ROM code for the 83C51 FC, the following must be specified: 

1 . 1 6k byte user ROM data 

2. 64 byte ROM encryption key 



3. ROM security bits. 



ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


0000H to 7FFFH 


DATA 


7:0 


User ROM Data 


8000Hto801FH 


KEY 


7:0 

u 1 


ROM Encryption Key 
FFH = no encryption 


8020H 


SEC 




ROM Security Bit 1 

= enable security 

1 = disable security 


8020H 


SEC 


1 


ROM Security Bit 2 

- enable security 

1 = disable security 



Security Bit 1 : When programmed, this bit has two effects on masked ROM parts: 

1. External MOVC is disabled, and 

2. EA is latched on Reset. 

Security Bit 2: When programmed, this bit inhibits Verify User ROM. 



If the ROM Code file does not include the options, the following information must be included with the ROM code. 
For each of the following, check the appropriate box, and send to Philips along with the code: 

Security Bit #1: □ Enabled □ Disabled 

Security Bit #2: □ Enabled □ Disabled 

Encryption: □ No □ Yes If Yes, must send key file. 



1996 Aug 16 



3-60 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



DESCRIPTION 

The 87C51 FA and 87C51 FB Single-Chip 8-Bit Microcontrollers are 
manufactured in an advanced CMOS process and are derivatives of 
the 80C51 microcontroller family. The 87C51 F 
instruction set as the 80C51 . 

This device provides architectural enhancements that make it 
applicable in a variety of applications for general control systems. 
The 87C51 FA contains 8k x 8 memory, and the 87C51 FB contains 
16k x 8 memory. They both contain a volatile 256 x 8 read/write data 
memory, four 8-bit I/O ports, three 1 6-bit timer/event counters, a 
Programmable Counter Array (PCA), a multi-source, 
two-priority-level, nested interrupt structure, an enhanced UART and 
on-chip oscillator and timing circuits. For systems that require extra 
capability, the 87C51 FA/FB can be expanded using standard in- 
compatible memories and logic. 

Its added features make it an even more powerful microcontroller for 
applications that require pulse width modulation, high-speed I/O and 
up/down counting capabilities such as motor control. It also has a 
more versatile serial channel that facilitates multiprocessor 
communications. 

See 83C51 FA/83C51 FB/83C51 FC/80C51 FA datasheet for ROM 
and ROMless devices. 

FEATURES 

• 80C51 central processing unit 

• 87C51FA: 8k x 8 EPROM 
87C51FB: 1 6k x 8 EPROM 

- expandable externally to 64k bytes 

- Quick Pulse programming algorithm 

- Two level program security system 

• 256 x 8 RAM, expandable externally to 64k bytes 

• Three 16-bit timer/counters 

- T2 is an up/down counter 

• Programmable Counter Array (PCA) 

- High speed output 

- Capture/compare 

- Pulse Width Modulator 

- Watchdog Timer 

• Four 8-bit I/O ports 

• Full-duplex enhanced UART 

- Framing error detection 

- Automatic address recognition 

• Power control modes 

- Idle mode 

- Power-down mode 

• Once (On Circuit Emulation) Mode 

• Five package styles 

• OTP package available 



PIN 



CONFIGURA" 



TIONS 



T2/P1.o[7 
T2EX/P1.1[7 
ECI/P1.2|T 
CEX0/P1.3[T 
CEX1/P1.4[T 
CEX2/P1.5[? 
CEX3/P1.6[7 



CEX4/P1.7QT 




DUAL 
IN-LINE 
PACKAGE 



w| V CC 

39] PO O/ADO 

38] P0.1/A01 
— 1 

37] P0.2/AD2 
5| P0.3/AD3 
3| P0.4/AD4 
3i] P0.5/AD5 
H P0.6/AD6 
32] P07/AD7 
3l] ES 
30] ALE 
29] PSEN 
28] P2.7/A15 
27] P2.6/A14 
26] P2.5/A13 
25] P2.4/A12 
24] P2.3/A11 
23] P2.2/A10 
22] P2.1/A9 
|T] P2.0/A8 



1996 Aug 16 



3-61 



853-1692 17199 



Philips Semiconductors Product specification 
. 

CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



ORDERING INFORMATION 



8kx8 
EPROM 1 


16k x 8 
EPROM 1 


TEMPERATURE RANGE °C AND PACKAGE 

i LivirLnni unL ii i « vj i — mils rnwi\nuL 


FREQ. 
(MHz) 


DRAWING 
NUMBER 


S87C51FA-4N40 


S87C51 FB-4N40 


OTP 


to +70, 40-Pin Plastic Dual In-line Package 


3.5 to 16 


SOT129-1 


S87C51FA-4F40 


S87C51 FB-4F40 


UV 


to +70, 40-Pin Ceramic Dual In-line Package w/Window 


3.5 to 16 


0590B 


S87C51FA-4A44 


S87C51FB-4A44 


OTP 


to +70, 44-Pin Plastic Leaded Chip Carrier 


3.5 to 16 


SOT187-2 


S87C51FA-4K44 


S87C51FB-4K44 


UV 


to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 


3.5 to 16 


1472A 


S87C51FA-4B44 


QB7CS1 FB-4B44 


OTP 


to +70, 44-Pin Plastic Quad Flat Pack 


3.5 to 16 


SOT307-2 


S87C51FA-5N40 


S87C51FB-5N40 


OTP 


-40 to +85, 40-Pin Plastic Dual In-line Package 


3.5 to 16 


SOT129-1 


S87C51FA-5F40 


S87C51FB-5F40 


UV 


-40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 


3.5 to 16 


0590B 


S87CS1FA-5A44 


S87C51FB-5A44 


OTP 


-40 to +85, 44-Pin Plastic Leaded Chip Carrier 


3.5 to 16 


SOT187-2 


S87C51FA-5B44 


S87C51FB-5B44 


OTP 


-40 to +85, 44-Pin Plastic Quad Flat Pack 


3.5 to 16 


SOT307-2 


S87C51FA-AN40 


S87C51FB-AN40 


OTP 


to +70, 40-Pin Plastic Dual In-line Package 


3.5 to 24 


SOT129-1 


S87C51FA-AF40 


S87C51FB-AF40 


UV 


to +70, 40-Pin Ceramic Dual In-line Package w/Window 


3.5 to 24 


0590B 


S87C51 FA-AA44 


S87C51FB-AA44 


OTP 


to +70, 44-Pin Plastic Leaded Chip Carrier 


3.5 to 24 


SOT187-2 


S87C51FA-AK44 


S87C51FB-AK44 


UV 


to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 


3.5 to 24 


1472A 


S87C51FA-BN40 


S87C51FB-BN40 


OTP 


-40 to +85, 40-Pin Plastic Dual In-line Package 


3.5 to 24 


SOT129-1 


S87C51 FA-BF40 


S87C51FB-BF40 


UV 


-40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 


3.5 to 24 


0590B 


S87C51FA-BA44 


S87C51FB-BA44 


OTP 


-40 to +85, 44-Pin Plastic Leaded Chip Carrier 


3.5 to 24 


SOT 187-2 



NOTE: 

% OTP = One Time Programmable EPROM. UV = Erasable EPROM. 



1996 Aug 16 



3-62 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



BLOCK DIAGRAM 



P0.0-P0.7 P2.0-P2.7 







vocj 
vssi 

I 



PORT 






PORT 2 




DRIVERS 




DRIVERS 




<> <> 




> <> 





7T 



PORT 
LATCH 



PORT 2 
LATCH 



in i 



B 




ACC 


REGISTER 





JL 



STACK 
POINTER 











TMP2 




TMP1 



ALU CL 



PSW 



I 



ALE/PH05>-l-« 
EWVpp— U 
RST- 



TIMING 
AND 
CONTROL 



TIMERS 
P.C.A 

<T <T 



PORT 1 
LATCH 



OSCILLATOR 



HOI- 



It 



PORT 1 
DRIVERS 



PROGRAM A- 
ADDRESS \i — 
REGISTER 



PC 
INCRE- 
MENTER 



JL 



c=3 



PORT 3 
LATCH 



I 



PORT 3 
DRIVERS 



----- «» UHf 



P3.0-P3.7 



1996 Aug 16 



3-63 



Table 1 . 87C51 FA/87C51 FB Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 
MSB LSB 


RESET 
VALUE 


ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


00H 


AUXR# 


Auxiliary 


8EH 




_ 


_ 


_ 


- 




_ 


AO 


xxxxxxxOB 


B* 


B register 


FOH 


F7 


F6 


F5 


F4 


F3 


F2 


F1 


FO 


00H 


CCAP0H# 
CCAP1H# 
CCAP2H# 
CCAP3H# 
CCAP4H# 
CCAP0L# 
CCAP1L# 


Module Capture High 
Module 1 Capture High 
Module 2 Capture High 
Module 3 Capture High 
Module 4 Capture High 
Module Capture Low 
Module 1 Capture Low 
Module 2 Capture Low 
Module 3 Capture Low 

Mf-iHiilo^l P'anti iro I r\\jj 
[VIUUUIc *t OdpiUFc LUW 


FAH 
FBH 
FCH 
FDH 
FEH 
EAH 
EBH 
















xxxxxxxxB 
xxxxxxxxB 
xxxxxxxxB 
xxxxxxxxB 
xxxxxxxxB 
xxxxxxxxB 
xxxxxxxxB 


CCAP2L* 
CCAP3L* 


ECH 
EDH 
EEH 


















xxxxxxxxB 
xxxxxxxxB 

yyyyyyyyR 

AAAAAAAALJ 
















CCAPMO# 


Module Mode 


DAH 


_ 


ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


X0000000B 


Kj\jr\iiV\ 1 # 


MrtHiilP 1 Mnrip 
iviouuit; i rviuue 

Moauie ti ivioae 


DBH 




ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 






nr^u 
uun 




ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


XUUUUUUUD 


CCAPM3* 


Module 3 Mode 


DDH 




ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


X0000000B 


CCAPM4# 


Module 4 Mode 


DEH 




ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


X0000000B 








DF 


DE 


DD 


DC 


DB 


DA 


D9 


D8 




CCON*# 


PCA Counter Control 


D8H 


CF 


OR 


- 


CCF4 


CCF3 


CCF2 


CCF1 


CCFO 


OOxOOOOOB 


CH# 
CL# 


PCA Counter High 
PCA Counter Low 


F9H 
E9H 




00H 
00H 


CMOD# 


PCA Counter Mode 


D9H 


CIDL 


WDTE 








CPS1 


CPSO 


ECF 


OOxxxOOOB 


DPTR: 
DPH 
DPL 


Data Pointer (2 bytes) 
Data Pnintpr Hinh 
Data Pointer Low 


83H 
82H 


















00H 
00H 








AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 




IE* 


Interrupt Enable 


A8H 


EA 


EC 


ET2 


ES 


ET1 


Bl 


ETO 


EXO 


00H 








BF 


BE 


BD 


BC 


BB 


BA 


B9 


88 




IP* 


Intorrupt Priority 


B8H 


- 


PPC 


PT2 


PS 


PT1 


PX, 


PTO 


PXO 


ynnnnnnnR 

XUUUUUUUD 








87 


86 


85 


84 


83 


82 


81 


80 




PO* 


PortO 


80H 


AD7 


AD6 


AD5 


AD4 


AD3 


AD2 


AD1 


ADO 


FFH 








97 


96 


95 


94 


93 


92 


91 


90 




P1* 


Port 1 


90H 


CEX4 


CEX3 


CEX2 


CEX1 


CEXO 


ECI 


T2EX 


T2 


FFH 








A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 




P2* 


Port 2 


AOH 


AD15 


AD14 


AD13 


AD12 


AD11 


AD10 


AD9 


AD8 


FFH 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




P3* 


Port 3 


BOH 


RTJ 


WR 


T1 


TO 


TNTT 


INTO 


TxD 


RxD 


FFH 












PCON# 


Power Control 


87H 


SM0D1 


SMODO 




POF 1 


GF1 


GFO 


PD 


IDL 


OOxxxxOOB 













" SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 
1 . Reset value depends on reset source. 



1996 Aug 16 



3-64 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



Table 1 . 87C51 FA/87C51 FB Special Function Registers (Continued) 



PORT 



SYMBOL 



DESCRIPTION 



DIRECT 
ADDRESS 



BIT ADDRESS, SYMBOL, OR ALTERNATIVE 
MSB 



FUNCTION 

LSB 



RESET 
VALUE 



D7 



D6 



D5 



D4 



D3 



D2 



D1 



DO 



PSW* 

RACAP2H# 
RACAP2L* 



SADDR# 
SADEN# 



SBUF 



SCON" 
SP 



TCON* 



T2CON* 
T2MOD# 

THO 

TH1 

TH2# 

TLO 

TL1 

TL2# 

TMOD 



Program Status Word 

Timer 2 Capture High 
Timer 2 Capture Low 

Slave Address 
Slave Address Mask 

Serial Data Buffer 

Serial Control 
Stack Pointer 

Timer Control 



Timer 2 Control 
Timer 2 Mode Control 



Timer High 
Timer High 1 
Timer High 2 
Timer Low 
Timer Low 1 
Timer Low 2 

Timer Mode 



DOH 

CBH 
CAH 

A9H 
B9H 

99H 

98H 
81H 

88H 



CBH 
C9H 

8CH 
8DH 
CDH 
8AH 
8BH 
CCH 

89H 



CY | AC | FO | RS1 



RSO 



OV 



9F 



9E 



9D 



9C 



9B 



9A 



SMO | SM1 | SM2 | REN | TB8 | RB8 | Tl 

8F 8E 8D 8C 8B 8A 89 

TF1 TR1 | TFO | TRO | IE1 | IT1 IEO 



Rl 



88 



I TO 



CF 



CE 



CD 



CC 



CB 



CA 



C9 



C8 



TF2 



EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 



J 



T20E 2 DCEN 



00H 

00H 
00H 

00H 
00H 

xxxxxxxxB 

00H 
07H 



00H 

xxxxxxOOB 

00H 
00H 
00H 
OOH 
00H 
OOH 



GATE | C/T | Ml | MO | GATE | C/T | M1 | ~M0 



OOH 



* SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 
2. T20E - see Programmable Clock-Out. 



1996 Aug 16 



3-65 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



CERAMIC AND PLASTIC LEADED CHIP CARRIER 
PIN FUNCTIONS 























6 


1 


40 












I — i 
P- 


1 — i 


I — i 












/ 















' L 










J 39 


























LCC 






















□ 29 












u 












18 




28 








Pin 


Function 


Pin 


Function 






Pin 


Function 


1 


NC" 


16 


P3.4/T0 






31 


P2.7/A15 


2 


P1.0/T2 


17 


P3.5/T1 






32 


PSEN 


3 


P1.1fT2EX 


18 


P3.6/WR" 






33 


ALE 


4 


P1.2/ECI 


19 


P3.7/HD 






34 


NC" 


S 


P1.3/CEX0 


20 


XTAL2 






35 


E* 


6 


P1.4/CEX1 


21 


XTAL1 






36 


P0.7/AD7 


7 


P1.5/CEX2 


22 


Vss 






37 


P0.6/AD6 


6 


PI .6/CEX3 


23 


NC* 






38 


P0.5/AD5 


9 


P1.7/CEX4 


24 


P2.0/AB 






39 


P0-4/AD4 


10 


RST 


25 


P2.1/A9 






40 


P0.3/AD3 


11 


P3.0/RxD 


26 


P2.2/A10 






41 


P0.2/AD2 


12 


NC" 


27 


P2.3/A11 






42 


P0.1/AD1 


13 


P3.1/TxD 


28 


P2.4/A12 






43 


P0.0/AD0 


14 


P3.2/1UT5 


29 


P2.5M13 






44 


Vcc 


15 


P3.3/INTT 


30 


P2.6/A14 






• DO NOT CONNECT 












SU007I5B 



PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 



O 



PQFP 



12 



Pin 


Function 


Pin 




Pin 


Function 


1 


P1.5/CEX2 


16 


Vss 


31 


P0.6/AD6 


2 


P1.6/CEX3 


17 


NC* 


32 


P0.5/AD5 


3 


P1-7/CEX4 


18 


P2.0/A8 


33 


P0.4/AD4 


4 


RST 


19 


P2.1/A9 


34 


P0.3/AD3 


5 


P3.0/RXD 


20 


P2.2/A10 


35 


P0.2MD2 


e 


NC* 


21 


P2.3/A11 


36 


P0.1/AD1 


7 


P3.1/TxD 


22 


P2.4/A12 


37 


P0.0/AD0 


B 


P3.2/IWTtJ 


23 


P2.5/A13 


38 


Vcc 


9 


P3.3/1NTT 


24 


P2.6/A14 


39 


NC* 


10 


P3.4/T0 


25 


P27/A15 


40 


P1.0/T2 


11 


P3.5/T1 


26 


P5ETC 


41 


P1.1/T2EX 


12 


P3.6/WR" 


27 


ALE 


42 


P1.2/ECI 


13 


P3.7/RT5 


28 


NC 


43 


P1.3/CEX0 


14 


XTAL2 


29 


EX 


44 


P1.4/CEX1 


15 


XTAL1 


30 


P0.7/AD7 







■ DO NOT CONNECT 



PIN DESCRIPTIONS 





PIN NUMBER 






MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAME AND FUNCTION 


Vss 


20 


22 


16 


I 


Ground: 0V reference. 


Vcc 


40 


44 


38 


I 


Power Supply: This is the power supply voltage for normal, idle, and power-down 












operation. 


PO.0-0.7 


39-32 


43-36 


37-30 


I/O 


Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to them 
float and can be used as high-impedance inputs. Port is also the multiplexed low-order 
address and data bus during accesses to external program and data memory. In this 
application, it uses strong internal pull-ups when emitting 1 s. Port also outputs the code 
bytes during program verification and receives code bytes during EPROM programming. 
External pull-ups are required during program verification. 


P1.0-P1.7 


1-8 


2-9 


40-44, 
1-3 


I/O 


Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 1 pins that are externally pulled low will source current because of the internal pull-ups. 
(See DC Electrical Characteristics: l| L ). Port 1 also receives the low-order address byte 
during program memory verification. Alternate functions include: 




1 


2 


40 


1 


T2 (P1.0): Timer/Counter 2 external count input/Clockout (See Programmable Clock-Out.) 




2 


3 


41 


1 


T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 




3 


4 


42 


1 


ECI (P1.2): External Clock Input to the PCA 




4 


5 


43 


I/O 


CEX0 (P1.3): Capture/Compare External I/O for PCA module 




5 


6 


44 


I/O 


CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 




6 


7 


1 


I/O 


CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 




7 


8 


2 


I/O 


CEX3 (PI .6): Capture/Compare External I/O for PCA module 3 




8 


9 


3 


I/O 


CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 


P2.0-P2.7 


21-28 


24-31 


18-25 


I/O 


Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 2 pins that are externally being pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l !L ). Port 2 emits the high-order address byte 
during fetches from external program memory and during accesses to external data memory 
that use 1 6-bit addresses (MOVX @ DPTR). In this application, it uses strong internal 
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit 
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some 
Port 2 pins receive the high order address bits during EPROM programming and verification. 



1996 Aug 16 



3-66 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



87C51FA/87C51FB 



PIN DESCRIPTIONS (Continued) 





PIN NUMBER 






MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAML AND rUNCIION 


P3.0-P3.7 


10-17 


11, 
13-19 


5. 
7-13 


I/O 


Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 3 pins that are externally being pulled low will source current because of the pull-ups. 
(See DC Electrical Characteristics: l| L ). Port 3 also serves the special features of the 80C51 
family, as listed below: 




10 


11 


5 


I 


RxD (P3.0): Serial input port 




11 


13 


7 





TxD (P3.1): Serial output port 




12 


14 


8 


I 


INTO (P3.2): External interrupt 




13 


15 


g 


I 


IRTT (P3.3): External interrupt 
TO (P3.4): Timer external input 




14 


16 


10 


1 




15 


17 


11 


1 


T1 (P3.5): Timer 1 external input 




16 


18 


12 





WR (P3.6): External data memory write strobe 




17 


19 


13 


o 


RD (P3.7): External data memory read strobe 


RST 


9 


10 


4 


1 


Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to Vss permits a power-on reset using only an external 
capacitor to Vcc- 


ALE/PROG 


30 


33 


27 


I/O 


Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the 
address during an access to external memory. In normal operation, ALE is emitted at a 
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. 
Note that one ALE pulse is skipped during each access to external data memory. This pin is 
also the program pulse input (PROG) during EPROM programming. 


P5EN 


29 


32 


26 


o 


Program Store Enable: The read strobe to external program memory^When the 

87C51 FA/FB is executing code from the external program memory, PSEN is activated twice 












each machine cycle, exceptthat two PSEN activations are skipped during each access to 
external data memory. PSEN is not activated during fetches from internal program memory. 












EATVpp 


31 


35 


29 


1 


External Access Enable/Programming Supply Voltage: EA must be externally held low 
to enable the device to fetch code from external program memory locations 0000H to 
1 FFFH. If EA" is held high, the device executes from internal program memory unless the 
program counter contains an address greater than 1 FFFH. This pin also receives the 












12.75V programming supply voltage (V PP ) during EPROM programming. If security bit 1 is 
programmed, EA" will be internally latched on Reset. 


XTAL1 


19 


21 


15 


1 


Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 


XTAL2 


18 


20 


14 


o 


Crystal 2: Output from the inverting oscillator amplifier. 



NOTE: 

To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V cc + 0.5V or V ss - 0.5V, respectively. 



TIMER 2 

This is a 1 6-bit up or down counter, which can be operated as either 
a timer or event counter. It can be operated in one of three different 
modes (autoreload, capture or as the baud rate generator for the 
UART). 

In the autoreload mode the Timer can be set to count up or down by 
setting or clearing the bit DCEN in the T2CON Special Function 
Register. The SFR's RCAP2H and RCAP2L are used to reload the 
Timer upon overflow or a 1 -to-0 transition on the T2EX input (P1 .1 ). 

In the Capture mode Timer 2 can either set TF2 and generate an 
interrupt or capture its value. To capture Timer 2 in response to a 
1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON 
must be set. Timer 2 is then captured in SFR's RCAP2H and 
RCAP2L. 



POWER OFF FLAG 

The Power Off Flag (POF) is set by on-chip circuitry when the Vcc 
level on the 87C51 FA/FB rises from to 5V. The POF bit can be set 
or cleared by software allowing a user to determine if the reset is the 
result of a power-on or a warm start after powerdown. The V cc level 
must remain above 3V for the POF to remain unaffected by the V C c 
level. 



As the baud rate generator, Timer 2 is selected by setting TCLK 
and/or RCLK in T2CON. As the baud rate generator Timer 2 is 
incren 



incremented at '/£ the oscillator frequency. 



1996 Aug 16 



3-67 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 
oscillator. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements 
on the duty cycle of the external clock signal, because the input to 
the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 




A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-on reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. At power-on, the voltage on 
V cc and RST must come up at the same time for a proper start-up. 

Idle Mode 

In the idle mode, the CPU puts itself to sleep while all of the on-chip 
peripherals stay active. The instruction to invoke the idle mode is the 
last instruction executed in the normal operating mode before the 
idle mode is activated. The CPU contents, the on-chip RAM, and all 
of the special function registers remain intact during this mode. The 
idle mode can be terminated either by any enabled interrupt (at 
which time the process is picked up at the interrupt service routine 
and continued), or by a hardware reset which starts the processor in 
the same manner as a power-on reset. 

Power-Down Mode 

To save even more power, a Power Down mode can be invoked by 
software. In this mode, the oscillator is stopped and the instruction 
that invoked Power Down is the last instruction executed. The 
on-chip RAM and Special Function Registers retain their values until 
the Power Down mode is terminated. 

On the 87C51 FA/FB either a hardware reset or external interrupt 
can use an exit from Power Down. Reset redefines all the SFRs but 
does not change the on-chip RAM. An external interrupt allows both 
the SFRs and the on-chip RAM to retain their values. 

To properly terminate Power Down the reset or external interrupt 
should not be executed before Vcc is restored to its normal 
operating level and must be held active long enough for the 
oscillator to restart and stabilize (normally less than 10ms). 

With an external interrupt, INTO and INT1 must be enabled and 
configured as level-sensitive. Holding the pin low restarts the 
oscillator but bringing the pin back high completes the exit. Once the 
interrupt is serviced, the next instruction to be executed after RETI 
will be the one following the instruction that put the device into 
Power Down. 



Design Consideration 

• When the idle mode is terminated by a hardware reset, the device 
normally resumes program execution, from where it left off, up to 
two machine cycles before the internal rest algorithm takes 
control. On-chip hardware inhibits access to internal RAM in this 
event, but access to the port pins is not inhibited. To eliminate the 
possibility of an unexpected write when Idle is terminated by reset, 
the instruction following the one that invokes Idle should not be 
one that writes to a port pin or to external memory. 

ONCE™ Mode 

The ONCE ("On-Circuit Emulation") Mode facilitates testing and 
debugging of systems using the 87C51 FA/FB without the 
87C51 FA/FB having to be removed from the circuit. The ONCE 
Mode is invoked by: 

1 . Pull ALE low while the device is in reset and PS EN is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in ONCE Mode, the Po rt pin s go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the 87C51 FA/FB is 
in this mode, an emulator or test CPU can be used to drive the 
circuit. Normal operation is restored when a normal reset is applied. 

Programmable Clock-Out 

The 87C51 FA/FB has a new feature. A 50% duty cycle clock can be 
programmed to come out on P1 .0. This pin, besides being a regular 
I/O pin, has two alternate functions. It can be programmed (1) to 
input the external clock for Timer/Counter 2 or (2) to output a 50% 
duty cycle clock ranging from 61 Hz to 4MHz at a 16MHz operating 
frequency. 

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in 
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit 
TR2 (T2CON.2) also must be set to start the timer. 

The Clock-Out frequency depends on the oscillator frequency and 
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) 
as shown in this equation: 

Oscillator Frequency 
4 x (65536 - RCAP2H, RCAP2L) 

In the Clock-Out mode, Timer 2 roll-overs will not generate an 
interrupt. This is similar to when it is used as a baud-rate generator. 
It is possible to use Timer 2 as a baud-rate generator and a clock 
generator simultaneously. Note, however, that the baud-rate and the 
Clock-Out frequency will be the same. 



Table 2. External Pin Status During Idle and Power-Down Mode 



MODE 


PROGRAM 
MEMORY 


ALE 


P5ETJ 


PORTO 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Float 


Data 


Data 


Data 



1996 Aug 16 



3-68 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



87C51FA/87C51FB 



Programmable Counter Array (PCA) 

The Programmable Counter Array is a special Timer that has five 
16-bit capture/compare modules associated with it. Each of the 
modules can be programmed to operate in one of four modes: rising 
and/or falling edge capture, software timer, high-speed output, or 
pulse width modulator. Each module has a pin associated with it in 
port 1 . Module is connected to P1 .3(CEX0). module 1 to 
P1 .4(CEX1 ), etc. The basic PCA configuration is shown in Figure 1 . 

The PCA timer is a common time base for all five modules and can 
be programmed to run at: 1/12 the oscillator frequency, 1/4 the 
oscillator frequency, the Timer overflow, or the input on the ECI pin 
(P1 .2). The timer count source is determined from the CPS1 and 
CPSO bits in the CMOD SFR as follows (see Figure 4): 

CPS1 CPSO PCA Timer Count Source 

1/12 oscillator frequency 

1 1/4 oscillator frequency 

1 Timer overflow 

1 1 External Input at ECI pin 

In the CMOD SFR are three additional bits associated with the PCA. 
They are CIDL which allows the PCA to stop during idle mode, 
WDTE which enables or disables the watchdog function on module 
4, and ECF which when set causes an interrupt and the PCA 
overflow flag, CF (in the CCON SFR) to be set when the PCA timer 
overflows. These functions are shown in Figure 2. 

The watchdog timer function is implemented in module 4 as 
implemented in other parts that have a PCA that are available on the 
market. However, if a watchdog timer is required in the target 
application, it is recommended to use the hardware watchdog timer 
that is implemented on the 87C51 FA/FB separately from the PCA 
(see Figure 12). 

The CCON SFR contains the run control bit for the PCA and the 
flags for the PCA timer (CF) and each module (refer to Figure 5). To 
run the PCA the CR bit (CCON. 6) must be set by software. The 
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when 
the PCA counter overflows and an interrupt will be generated if the 
ECF bit in the CMOD register is set, The CF bit can only be cleared 
by software. Bits through 4 of the CCON register are the flags for 
the modules (bit for module 0, bit 1 for module 1 , etc.) and are set 
by hardware when either a match or a capture occurs. These flags 
also can only be cleared by software. The PCA interrupt system 
shown in Figure 3. 



Each module in the PCA has a special function register associated 
with it. These registers are: CCAPMO for module 0, CCAPM1 for 
module 1 , etc. (see Figure 6). The registers contain the bits that 
control the mode in which each module will operate. The ECCF bit 
(CCAPMn.O where n=0, 1 , 2, 3, or 4 depending on the module) 
enables the CCF flag in the CCON SFR to generate an interrupt 
when a match or compare occurs in the associated module. PWM 
(CCAPMn.1 ) enables the pulse width modulation mode. The TOG 
bit (CCAPMn.2) when set causes the CEX output associated with 
the module to toggle when there is a match between the PCA 
counter and the module's capture/compare register. The match bit 
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON 
register to be set when there is a match between the PCA counter 
and the module's capture/compare register. 

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) 
determine the edge that a capture input will be active on. The CAPN 
bit enables the negative edge, and the CAPP bit enables the 
positive edge. If both bits are set both edges will be enabled and a 
capture will occur for either transition. The last bit in the register 
ECOM (CCAPMn.6) when set enables the comparator function. 
Figure 7 shows the CCAPMn settings for the various PCA functions. 

There are two additional registers associated with each of the PCA 
modules. They are CCAPnH and CCAPnL and these are the 
registers that store the 1 6-bit count when a capture occurs or a 
compare should occur. When a module is used in the PWM mode 
these registers are used to control the duty cycle of the output. 

PCA Capture Mode 

To use one of the PCA modules in the capture mode either one or 
both of the CCAPM bits CAPN and CAPP for that module must be 
set. The external CEX input for the module (on port 1 ) is sampled for 
a transition. When a valid transition occurs the PCA hardware loads 
the value of the PCA counter registers (CH and CL) into the 
module's capture registers (CCAPnL and CCAPnH). If the CCFn bit 
for the module in the CCON SFR and the ECCFn bit in the CCAPMn 
SFR are set then an interrupt will be generated. Refer to Figure 8. 

16-bit Software Timer Mode 

The PCA modules can be used as software timers by setting both 
the ECOM and MAT bits in the modules CCAPMn register. The PCA 
timer will be compared to the module's capture registers and when a 
match occurs an interrupt will occur if the CCFn (CCON SFR) and 
the ECCFn (CCAPMn SFR) bits for the module are both set (see 
Figure 9). 



• f~| P1.3/CEX0 




MODULE FUNCTIONS: 
16-BIT CAPTURE 
16-BIT TIMER 

16-BIT HIGH SPEED OUTPUT 
8-BIT PWM 
WATCHDOG TIMER (MODULE 4 ONLY) 



4 I P1 7/CEX4 



Figure 1. Programmable Counter Array (PCA) 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



o-To 



EXTERNAL INPUT i— i 



(P1.2/ECI) 



• - l L....0D.. 

: ; 1 01. 

; ; 10 

; 11.. 



TOPCA 
MODULES 



16-BIT UP COUNTER 



CIDL 


WDTE 








CPS1 


CPSO 


EOF 



CMOD 
(D9H) 



















CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO | 



Figure 2. PCA Timer/Counter 







PCA TIMER/COUNTER 



<r-f« 



3 | ECF | 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



X 



CCON 
(D8H) 



IE.6 




IE.7 


EC 




EA 




TO 

INTERRUPT 



Figure 3. PCA Interrupt System 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



87C51FA/87C51FB 



CMOD Address = OD9H 
Bit Addressable 



Reset Value = OOXXXO0OB 





CIDL 


WDTE 








CPS1 


CPSO 


ECF 


Bit: 


7 


6 


5 


4 


3 


2 


1 






Symbol Function 



CIDL 

WDTE 

CPS1 



ECF 



NOTE: 

* User software 
new bit will be 
" fosc 



Counter Idle control: CIDL = programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs 
it to be gated off during idle. 

Watchdog Timer Enable: WDTE = disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. 
Not implemented, reserved for future use.* 
PCA Count Pulse Select bit 1 . 

PCA Count Pulse Select bit 0. 

CPS1 CPSO Selected PCA Input" 

Internal clock, f osc + 12 

1 1 Internal clock, fosc * 4 

1 2 Timer overflow 

1 1 3 External clock at ECI/P1 .2 pin (max. rate = fosc * 8) 

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = disables 
that function of CF. 

should not write Is to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the 
0. and its active value will be 1 . The value read from a reserved bit is indeterminate. 



Figure 4. CMOD: PCA Counter Mode Register 



bol 



CCON Address = OD8H 
Bit Addressable 



Reset Value = 00X0 0000B 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCF0 



Bit: 7 
Function 



CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is 

set. CF may be set by either hardware or software but can only be cleared by software. 

CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA 

counter off. 

Not implemented, reserved for future use*. 
CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
CCF0 PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 

NOTE: 

" User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the 
new bit will be 0. and its active value will be 1 The value read from a reserved bit is indeterminate. 



Figure 5. CCON: PCA Counter Control Register 



1996 Aug 16 



3-71 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



CCAPMn Address 



CCAPMO 
CCAPM1 
CCAPM2 
CCAPM3 
CCAPM4 

Not Bit Addressable 



ODAH 
ODBH 
ODCH 
ODDH 
ODEH 



Reset Value = X000 OOOOB 







ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




Bit: 


7 


6 


5 


4 


3 


2 


1 







Symbol Function 

















ECOMn 
CAPPn 
CAPNn 
MATn 

TOGn 

PWMn 
ECCFn 

NOTE: 

*User software 
bit will be 0, 



Not implemented, reserved for future use*. 
Enable Comparator. ECOMn = 1 enables the comparator function. 
Capture Positive, CAPPn = 1 enables positive edge capture. 
Capture Negative, CAPNn = 1 enables negative edge capture. 

Match. When MATn = 1 , a match of the PCA counter with this module's compare/capture register causes the CCFn bit 
in CCON to be set, flagging an interrupt. 

Toggle. When TOGn = 1 , a match of the PCA counter with this module's compare/capture register causes the CEXn 
pin to toggle. 

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. 
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. 

. 



should not write Is to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the n 
its active value will be 1 . The value read from a reserved bit is indeterminate. 



Figure 6. CCAPMn: PCA Modules Compare/Capture Registers 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 


MODULE FUNCTION 


X 























No operation 


X 


X 


1 














X 


1 6-bit capture by a positive-edge trigger on CEXn 


X 


X 





1 











X 


1 6-bit capture by a negative trigger on CEXn 


X 


X 


1 


1 











X 


1 6-bit capture by a transition on CEXn 


X 


1 








1 








X 


1 6-bit Software Timer 


X 


1 








1 


1 





X 


16-bit High Speed Output 


X 


1 














1 





8-bit PWM 


X 


1 








1 


X 





X 


Watchdog Timer 



Figure 7. PCA Module Modes (CCAPMn Register) 



High Speed Output Mode 

In this mode the CEX output (on port 1 ) associated with the PCA 
module will toggle each time a match occurs between the PCA 
counter and the module's capture registers. To activate this mode 
the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must 
be set (see Figure 10). 

Pulse Width Modulator Mode 

All of the PCA modules can be used as PWM outputs. Figure 11 
shows the PWM function. The frequency of the output depends on 
the source for the PCA timer. All of the modules will have the same 
frequency of output because they all share the PCA timer. The duty 
cycle of each module is independently variable using the module's 
capture register CCAPLn. When the value of the PCA CL SFR is 
less than the value in the module's CCAPLn SFR the output will be 
low, when it is equal to or greater than the output will be high. When 
CL overflows from FF to 00, CCAPLn is reloaded with the value in 
CCAPHn then allows updating the PWM without glitches. The PWM 
and ECOM bits in the module's CCAPMn register must be set to 
enable the PWM mode. 



Enhanced UART 

The UART operates in all of the usual modes that are described in 
the first section of this book for the 80C51 . In addition the UART can 
perform framing error detect by looking for missing stop bits, and 
automatic address recognition. The 87C51 FA/FB UART also fully 
supports multiprocessor communication as does the standard 
80C51 UART. 

When used for framing error detect the UART looks for missing stop 
bits in the communication. A missing bit will set the FE bit in the 
SCON register. The FE bit shares the SCON. 7 bit with SM0 and the 
function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 
13). If SMOD0 is set then SCON.7 functions as FE. SCON.7 
functions as SMO when SMOD0 is cleared. When used as FE 
SCON.7 can only be cleared by software. Refer to Figure 14. 

Automatic Address Recognition 

Automatic Address Recognition is a feature which allows the UART 
to recognize certain addresses in the serial bit stream by using 
hardware to make the comparisons. This feature saves a great deal 



1996 Aug 16 



3-72 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



of software overhead by eliminating the need for the software to 
examine every serial address which passes by the serial port. This 
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART 
modes, mode 2 and mode 3, the Receive Interrupt flag (Rl) will be 
automatically set when the received byte contains either the "Given" 
address or the "Broadcast" address. The 9 bit mode requires that 
the 9th information bit is a 1 to indicate that the received information 
is an address and not data. Automatic address recognition is shown 
in Figure 15. 

The 8 bit mode is called Mode 1 . In this mode the Rl flag will be set 
if SM2 is enabled and the information received has a valid stop bit 
following the 8 address bits and the information is either a Given or 
Broadcast address. 

Mode is the Shift Register mode and SM2 is ignored. 

Using the Automatic Address Recognition feature allows a master to 
selectively communicate with one or more slaves by invoking the 
Given slave address or addresses. All of the slaves may be 
contacted by using the Broadcast address. Two special Function 
Registers are used to define the slave's address, SADDR, and the 
address mask, SADEN. SADEN is used to define which bits in the 
SADDR are to b used and which bits are "don't care". The SADEN 
mask can be logically ANDed with the SADDR to create the "IGiven" 
address which the master will use for addressing each of the slaves. 
Use of the Given address allows multiple slaves to be recognized 
while excluding others. The following examples will help to show the 
versatility of this scheme: 

Slave 



ve 1 



SADDR = 


1100 0000 


SADEN = 


1111 


1101 


Given = 


1100 


00X0 


SADDR = 


1100 


0000 


SADEN = 


1111 


mo 


Given = 


1100 


ooox 



In the above example SADDR is the same and the SADEN data is 
used to differentiate between the two slaves. Slave requires a in 
bit and it ignores bit 1 . Slave 1 requires a in bit 1 and bit is 
ignored. A unique address for Slave would be 1100 0010 since 
slave 1 requires a in bit 1 . A unique address for slave 1 would be 
1100 0001 since a 1 in bit will exclude slave 0. Both slaves can be 
selected at the same time by an address which has bit = (for 
slave 0) and bit 1 = (for slave 1 ). Thus, both could be addressed 
with 1100 0000. 

In a more complex system the following could be used to select 
slaves 1 and 2 while excluding slave 0: 



Slave 


SADDR ■ 


1100 0000 




SADEN = 


1111 1001 




Given 


1100 oxxo 


Slave 1 


SADDR = 


1110 0000 




SADEN = 


1111 1010 




Given = 


1110 oxox 


Slave 2 


SADDR = 


1110 0000 




SADEN = 


1111 1100 




Given 


1110 ooxx 



In the above example the differentiation among the 3 slaves is in the 
lower 3 address bits. Slave requires that bit = and it can be 
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = and 
it can be uniquely addressed by 1 1 1 and 01 01 . Slave 2 requires 
that bit 2 = and its unique address is 1110 0011 . To select Slaves 
and 1 and exclude Slave 2 use address 1110 0100, since it is 
necessary to make bit 2 = 1 to exclude slave 2. 

The Broadcast Address for each slave is created by taking the 
logical OR of SADDR and SADEN. Zeros in this result are teated as 
don't-cares. In most cases, interpreting the don't-cares as ones, the 
broadcast address will be FF hexadecimal. 

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR 
address 0B9H) are loaded with 0s. This produces a given address 
of all "don't cares" as well as a Broadcast address of all "don't 
cares". This effectively disables the Automatic Addressing mode and 
allows the microcontroller to use standard 80C51 type UART drivers 
which do not make use of this feature. 

Reduced EMI Mode 

The AO bit (AUXR.0) in the AUXR register when set disables the 
ALE output. 

87C51FA/FB Reduced EMI Mode 

AUXR (0X8E) 



- I - I - 



AO: Turns off ALE output. 
Interrupt Enable (IE) Register 



EA 


IE.7 


enable all interrupts 


EC 


IE.6 


enable PCA interrupt 


ET2 


IE.5 


enable Timer 2 interrupt 


ES 


IE.4 


enable Serial I/O interrupt 


ET1 


IE.3 


enable Timer 1 interrupt 


EX1 


IE.2 


enable External interrupt 1 


ET0 


IE.1 


enable Timer interrupt 


EX0 


IE.0 


enable External interrupt 


Interrupt Priority (IP) Register 




IP.7 


reserved 


PPC 


IP.6 


PCA interrupt priority 


PT2 


IP.5 


Timer 2 interrupt priority 


PS 


IP.4 


Serial I/O interrupt priority 


PT1 


IP.3 


Timer 1 interrupt priority 


PX1 


IP.2 


External interrupt 1 priority 


PT0 


IP.1 


Timer interrupt priority 


PXO 


IP.O 


External interrupt priority 



Priority 


Source 


Flag 


Vector 


1 


INTO 


IE0 


03H highest priority 


2 


Timer 


TF0 


0BH 


3 


INT1 


IE1 


13H 


4 


Timer 1 


TF1 


1BH 


5 


PCA 


CF.CCFn 


33H 


6 


Serial I/O 


Rl.TI 


23H 


7 


Timer 2 


TF2/EXF2 


2BH lowest priority 



1996 Aug 16 



3-73 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



CF 


CR 




CCF4 


CCF3 


CCF2 















CCON 
(D8H) 



1 



► PCA INTERRUPT 



CTO CCFn) 



PCA TIMER/COUNTER 



5 



CCAPnH CCAPnL 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOQn 


PWMn 


ECCFn 
























Figure 8. PCA Capture Mode 





cc *™ n : 1-9.!° 4 



WRITE TO 
CCAPnH RESET 



WRITE TO 
CCAPnL 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



CCON 
(D8H) 



CCAPnH 


CCAPnL 




: 



(TO CCFn) 



16-BIT COMPARATOR 



PCA INTERRUPT 













CH 


CL 



PCA TIMER/COUNTER 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 



CCAPMn, n= to 4 
(DAH - DEH) 













Figure 9. PCA Compare Mode 



1996 Aug 16 



3-74 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



87C51FA/87C51FB 



WHITE TO 
CCAPnH RESET 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



CCON 
(D8H) 



WRITE TO 
COAPnL 



;V nTnr 



(TO CCFn) 



16-BIT COMPARATOR 

7% 7T 



<A *■ PCA INTERRUPT 



1 [5C] CJcEXn 



PCA TIMER/COUNTER 



1 - 


ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




t 










1 








CCAPMn. n: 0- 4 
(DAH - DEH) 



Figure 10. PCA High Speed Output Mode 



□ 



1 



8-BIT 
COMPARATOR 

~ r> — 



CL >• CCAPnL 



PCA TIMER/COUNTER 



1 1 »Q CEXn 

. : 







ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 


CCAPMn. n: 0..4 
{DAH - DEH) 






























Figure 11. PCA PWM Mode 



1996 Aug 16 



3-75 



Philips Semiconductors 



Product specification 



CMOS single-c 



87C51FA/87C51FB 





CIDL 


WDTE 








CPS1 


CPSO 


ECF 



WRITE TO 
CCAP4H 



WRITE TO 
CCAP4L 




CMOD 
(D9H) 



9. n 



1 6— BIT COMPARATOR 













CH 


CL 



RESET 



PCA TIMER/COUNTER 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




T 








1 


X 





X 



CCAPM4 
(DEH) 



Watchdog Timer 



SMO 
SM1 



SM2 



REN 
TB8 
RB8 

Tl 

Rl 

NOTE: 

•SMODO is 
"* f OSC 



SCON Address = 
Bit Addressable 



98H 



Reset Value = 0000 0000B 





SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


Bit: 


7 

(SMODO = 


6 

0/1 J* 


5 


4 


3 


2 


1 





Symbol Function 

















Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid 
frames but should be cleared by software. The SMODO bit must be set to enable access to the FE bit. 

Serial Port Mode Bit 0, (SMODO must = to access bit SMO) 

Serial Port Mode Bit 1 



SMO 


SM1 


Mode 


Description 


Baud Rate" 











shift register 


fosc/12 





1 


1 


8-bit UART 


variable 


1 





2 


9-bit UART 


fosc/64 or fosc/32 


1 


1 


3 


9-bit UART 


variable 



Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the 
received 9th data bit (RB8) is 1 , indicating an address, and the received byte is a Given or Broadcast Address. 
In Mode 1 , if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a 
Given or Broadcast Address. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In modes 2 and 3, the 9th data bit that was received. In Mode 1 , if SM2 = 0, RB8 is the stop bit that was received. 
In Mode 0, RB8 is not used. 

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the 
other modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in 
the other modes, in any serial reception ( 



locaied at PCON6. 
frequency 



Figure 13. SCON: Serial Port Control Register 



1996 Aug 16 



3-76 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 




START 



ONLY IN STOP 
MODE 2. 3 BIT 



SET FE BIT IF STOP BIT IS (FRAMING ERROR) 
SMO TO UART MODE CONTROL 



SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 




SMOD1 


SMODO 


OSF 


POF 


LVF 


GFO 


GF1 


IDL 



SCON 
(98H) 



PCON 
(87H) 



: SCON.7 = SMO 

1 : SCON.7 < FE 



Figure 14. UART Framing Error Detection 



C D2 D3 


5v °* 


/X 05 


/\ 06 , 


>C 07 y\. c 


8 \ 


























SMO 


SM1 


SM2 


REN 


TB8 


Rl 


38 


Tl 


Rl 



RECEIVED ADDRESS DO TO D7 
PROGRAMMED ADDRESS 



IN UART MODE 2 OR MODE 3 AND SM2 = 1 : 

INTERRUPT IF REN=1, RB8=I AND "RECEIVED ADDRESS" =. "PROGRAMMED ADDRESS" 
- -N OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES 

N ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. 



SCON 
(98H) 



Figure 15. UART Multiprocessor Communication, Automatic Address Recognition 



1996 Aug 16 



3-77 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



ABSOLUTE MAXIMUM RATINGS 1 2 3 



PARAMETER 


RATING 


UNIT 


Operating temperature under bias 


to +70 or -40 to +85 


°C 




Storage temperature range 


-65 to +150 


°c 


Voltage on EATVpp pin to Vss 


to +13.0 


V 


Voltage on any other pin to Vss 


-0.5 to +6.5 


V 


Maximum Iol per I/O pin 


15 


mA 


Power dissipation 

(based on package heat transfer limitations, not device power consumption) 


1.5 


W 



NOTES: 

1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vss unless otherwise 
noted. 



Electrical Deviations from Commercial Specifications for Extended Temperature Range 

DC and AC parameters not included here are the same as in the commercial temperature range table. 

DC ELECTRICAL CHARACTERISTICS 

T amb = -40°C to +85°C, V CC = 5V ±10%, V SS - 0V 







TEST 


LIMITS 




SYMBOL 


PARAMETER 


CONDITIONS 


MIN 






VlL 


Input low voltage, except EA" 




-0.5 


0.2V CC -0.15 


V 


V'lLI 


Input low voltage to EA 







0.2V OC -0.35 


V 


V,H 


Input high voltage, except XTAL1 , RST 




0.2V CC +1 


Vcc+0.5 


V 


V|H1 


Input high voltage to XTAL1 , RST 




0.7V CC +0.1 


V cc +0.5 


V 


l|L 


Logical input current, ports 1 , 2, 3 


V| N = 0.45V 




-75 


MA 


Itl 


Logical 1 -to-0 transition current, ports 1,2,3 


V| N = 2.0V 




-750 















II 



1996 Aug 16 



3-78 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



DC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to +85"C, V C c = 5V ±10%, V S s = 0V 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 


V|L 


Input low voltage, except ES 7 




-0.5 




0.2V CC -01 


V 


V|L1 


Input low voltage to EA' 









0.2V CC -0.3 


V 


VlH 


Input high voltage, except XTAL1 , RST 7 




0.2V cc +0.9 




Vcc+0.5 


V 


V|H1 


Input high voltage, XTAL1 , RST 7 




0.7V C c 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 3 9 


l OL = 1.6mA 2 






0.45 


V 


Voli 


Output low voltage, port 0, ALE, PSEN 9 


l 0L = 3.2mA z 






0.45 


V 


Voh 


Output high voltage, ports 1 , 2, 3, ALE, PSEN 3 


l 0H = -30|iA 


V CC - 0.7 






V 


V0H1 


Output high voltage (port in external bus mode), 
ALE 10 , PSEN 3 


Ioh = -3.2mA 


V cc - 0.7 






V 


IlL 


Logical input current, ports 1 , 2, 3 7 


V| N = 0.45V 






-50 


HA 


Itl 


Logical 1 -to-0 transition current, ports 1 , 2, 3 7 


See note 4 






-650 


HA 


lu 




Input leakage current, port 


0.45 V, N < 
V C c " 0.3 






±10 


HA 


Ice 


Power supply current: 
Active mode @ 16MHz 5 
Idle mode @ 16MHz 
Power-down mode 
Tamb = to +70°C 
Tamb=^0to+85°C 


See note 6 




15 

3 

10 


32 
5 

50 
75 


mA 
mA 

uA 
uA 


Rrst 


Internal reset pull-down resistor 




50 




225 


kfi 


Cio 


Pin capacitance 11 (except ES) 








15 


PF 



1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the Vols of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1 -to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 1 0OpF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Iol can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs ex ceed th e test conditions. 

3. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the 0.9V C c specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 

5- Iccmax at other frequencies is given by: Active mode: Iccmax = 1.50 x FREQ + 8; Idle mode: Iccmax = 0.14 x FREQ+2.31, 
where FREQ is the external oscillator frequency in MHz. Iccmax is 9 iven in m A. See Figure 23. 

6. See Figures 24 through 27 for Ice test conditions. 

7. These values apply only to T am b = 0°C to+70°C. For T amb = -40°C to +85°C, see table on previous page. 

8. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

9. Under steady state (non-transient) conditions, Iol must be externally limited as follows: 

Maximum Iol per port pin: 15mA ("NOTE: This is 85°C specification.) 

Maximum Iol per 8-bit port: 26mA 

Maximum total Iol for all outputs: 71mA 
If Iol exceeds the test condition, V 0L may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

1 0. ALE is tested to V m , except when ALE is off then V h is the voltage specification. 

1 1 . Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 1 5pF (except ES, it is 25pF). 



1996 Aug 16 



3-79 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40"C to +85°C, V C c = 5V ±1 0%, Vss = 0V 1 ' 2 ' 3 



SYMBOL 


FIGURE 


— 

PARAMETER 


16MHz CLOCK 


VARIABLE CLOCK 


1 IhllT 
UNI 1 


MIN 


MAX 


MIN 


MAX 


1/toLOL 


16 


Oscillator frequency -4,-5 






3.5 


16 


MHz 


-A, -B 






3.5 


24 


MHz 


'lhll 


16 


ALE pulse width 


85 




2tcLCL-40 




ns 


UvLL 


16 


Address valid to ALE low 


22 




tcLCL-40 




ns 


tLLAX 


16 


Address hold after ALE low 


32 




tcLCL-30 




ns 


'lliv 


16 


ALE low to valid instruction in 




150 




4tci_CL-1°0 


ns 


tLLPL 


16 


ALE low to PSEN low 


32 




tCLCL-30 




ns 


tpLPH 


16 


PSEN pulse width 


142 




3tcLCL"^5 




ns 


tpLIV 4 


16 


PSEN low to valid instruction in 




82 




3tcLCL-105 


ns 


tpxix 


16 


Input instruction hold after PSEN 












ns 


tpxiz 


16 


Input instruction float after PSEN 




37 




tCLCL-25 


ns 


tAVIV 


16 


Address to valid instruction in 




207 




5t C LCL-105 


ns 


tpLAZ 


16 


PSEN low to address float 




10 




10 


ns 


Data Memory 


tRLRH 


17, 18 


RD pulse width 


275 




6tci_CL-100 




ns 


*WLWH 


17, 18 


WR pulse width 


275 




6tcLCL-100 




ns 


tRLDV 


17, 18 


RD low to valid data in 




147 




5tcLCL"155 


ns 


tRHDX 


17, 18 


Data hold after RD 












ns 


tRHDZ 


17, 18 


Data float after RD 




65 




2tci_CL-60 


ns 


t|_LDV 


17, 18 


ALE low to valid data in 




350 




8tcLCL-150 


ns 


Wdv 


17, 18 


Address to valid data in 




397 




9tci_CL-165 


ns 


( LLWL 


17, 18 


ALE low to RD or WR low 


137 


237 


3tci_CL"50 


3tciXL+50 


ns 


'avwl 


17, 18 


Address valid to WR low or RD low 


122 




4tcLCL-130 




ns 


tQVWX 


17, 18 


Data valid to WR transition 


13 




tcLCL-50 




ns 


twHQX 


17, 18 


Data hold after WR 


13 




tCLCL-50 




ns 


fQVWH 


18 


Data valid to WR high 


287 




7ICLCL-150 




ns 


tRLAZ 


17, 18 


RD low to address float 












ns 


tyVHLH 


17, 18 


RD or WR high to ALE high 


23 


103 


tcLCL-^0 


tcLCL+40 


ns 


External Clock 


*CHCX 


20 


High time 


20 




20 




ns 


tCLCX 


20 


Low time 


20 




20 




ns 


( CLCH 


20 


Rise time 




20 




20 


ns 


tcHCL 


20 


Fall time 




20 




20 


ns 


Shift Register 


txLXL 


19 


Serial port clock cycle time 


750 




12tcLCL 




ns 


tQVXH 


19 


Output data setup to clock rising edge 


492 




10tci_CL-133 




ns 


txHQX 


19 


Output data hold after clock rising edge 


8 




2tcLCL-117 




ns 


txHDX 


19 


Input data hold after clock rising edge 












ns 


'XHDV 


19 


Clock rising edge to input data valid 




492 




10tcLCL-133 


ns 



NOTES: 

1 . Parameters are valid over operating temperature range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 87C51 FA/FB to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. See Application Note AN457. 



1996 Aug 16 



3-80 



Philips Semiconductors Product specification 


CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to +85°C, V c c = 5V +10%, Vss = 2 ' 3 









24MHz CLOCK 


VARIABLE CLOCK 4 




SYMBOL 


FIGURE 


PARAMETER 


MIN 


MAX 


MIN 


MAX 


UNIT 


1/tCLCL 


16 


Speed versions : A, B (24MHz) 


3.5 


24 


3.5 


24 


MHz 


•lhll 


16 


ALE pulse width 


43 




2tcLCL-^0 




ns 


•avll 


16 


Address valid to ALE low 


17 




tcLCL-25 




ns 


t|_LAX 


16 


Address hold after ALE low 


17 




tcLCL-25 




ns 


*LLIV 


16 


ALE low to valid instruction in 




102 




4tc LC L-65 


ns 


*LLPL 


16 


ALE low to P5EN low 


17 




tc|_CL-25 




ns 


tpLPH 


16 


PSEN pulse width 


80 




3tcLCL^t5 




ns 


tpLIV 


16 


PSEN low to valid instruction in 




65 




3tcLCL"~60 


ns 


tpxix 


16 


Input instruction hold after PSEN 












ns 




tpxiz 


16 


Input instruction float after PSEN 




17 




tCLCL-25 


ns 


tAVIV 


16 


Address to valid instruction in 




128 




5tcLCL"80 


ns 


tpLAZ 


16 


PSEN low to address float 




10 




10 


ns 


Data Memory 


*RLRH 


17, 18 


RD pulse width 


150 




6tcLCL-100 




ns 


tWLWH 


17, 18 


WR pulse width 


150 




6tciXL-100 




ns 


*RLDV 


17, 18 


RD low to valid data in 




118 




5tcLCL"90 


ns 


tRHDX 


17, 18 


Data hold after RD 














tfiHDZ 


17, 18 


Data float after RD 




55 




2t C LCL-28 




tLLDV 


17, 18 


ALE low to valid data in 




183 




8tcLCL-150 


ns 


tAVDV 


17, 18 


Address to valid data in 




210 




9tcLCL"165 


ns 










Illwl 


17, 18 


ALE low to RD or WR low 


75 


175 


3t C LCL-50 


3tcLCL+50 


ns 


•avwl 


17, 18 


Address valid to WR low or RD low 


92 




4tcLCL-?5 




ns 


•qvwx 


17, 18 


Data valid to WR transition 


12 




tcLCL-30 




ns 


twHQX 


17, 18 


Data hold after WR 


17 




tcLCL-25 




ns 


•qvwh 


18 


Data valid to WR high 


162 




7to LC L-130 




ns 


Irlaz 


17, 18 


RD low to address float 












ns 


twHLH 


17, 18 


RDorWRhightoALE high 


17 


67 


tcLCL-25 


tCLCL+25 


ns 


External Clock 


tCHCX 


20 


High time 


17 




17 


'CLCL-'CLCX 


ns 


toLCX 


20 


Low time 


17 




17 


•cLCL-tcHCX 


ns 


tCLCH 


20 


Rise time 




5 




5 


ns 


tcHCL 


20 


Fall time 




5 




5 


ns 


Shift Register 


txLXL 


19 


Serial port clock cycle time 


505 




12tcLCL 




ns 


*QVXH 


19 


Output data setup to clock rising edge 


283 




10t CLCL -133 




ns 


'XHQX 


19 


Output data hold after clock rising edge 


3 




2tcLCL-80 




ns 


*XHDX 


19 


Input data hold after clock rising edge 












ns 


txHDV 


19 


Clock rising edge to input data valid 




283 




10tc L CL-133 


ns 



NOTES: 

1 . Parameters are valid over operating temperature range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = lOOpF, load capacitance for all other outputs = 80pF. 

3. interfacing the 87C51 FA/FB to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. Variable clock is specified for oscillator frequencies greater than 16MHzto 33MHz. For frequencies equal or less than 16MHz, see 16MHz 
"AC Electrial Characteristics", page 3-80. 



1996 Aug 16 



3-81 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 

5 (= time). The other characters, depending on their positions, 

indicate the name of a signal or the logical status of that signal. The 

designations are: 

A - Address 

C- Clock 

D - Input data 

H - Logic level high 

I - Instruction (program memory contents) 
L - Logic level low, or ALE 



P-P5ER 
Q - Output data 
R - RD signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: tAVLL = Tme for address valid to ALE low. 
tu_ PL = Time for ALE low to P5ETJ low. 



— 



Ilhll 

tAVLL 



PORT 2 



>: 



y v_ 







tLLPL 



tpLPH 



*LUV — ' 
tpLIV. 



tLLAX 



tpLAZ 



tAVIV 



tpxrx" 



- tpxiz- 



X 



Figure 16. External Program Memory Read Cycle 



tAVLL 



X 



y 



« - twHLH 



tLLDV 



tLLWL 



tLLAX 



\ / A0-A7 \ 

? > FROMRIORDPL r ' 



tRLA^ 



" t A VWL 



tRLRH 



tRLDV 



t-AVDV 



tRHDX ' 



< DATA IN 




A0-A7 FROM PCL 



P2.0-P2.7 OR A8-A15 FROM DPF 



A0-A15 FROM PCH 



Figure 17. External Data Memory Read Cycle 



1996 Aug 16 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



tAVLL 



PORT 2 



zx 







Illwl 



tLLAX 



A0-A7 
FROM Rl OR DPL 



X 



tQVWX 



•WHLH 



^ / 

X / 



/ 



- <AVWL 



tQVWH 



'WHQX 



XX 



A0-A7 FROM PCL 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 18. External Data Memory Write Cycle 





| | 1 | 2 | 3 | 4 | 5 | 6 | 7 | B | 

L_r^_r^_n_r" L_n_r~L_n_r 

I ~*\ K" 'XHQX I 
tQVXH Y H I 

^I^3CT>C3Z>CZZ>CZZ>CZ3eZ>CZ7 7 

I r 'xhdx 

•xhdv r* — *] | 



INSTRUCTION 
ALE 



OUTPUT DATA . 

' T ' 

WRITE TO SBUF 

INPUT DATA . 



f 

SETTI 



t 

SET Rl 



Figure 19. Shift Register Mode Timing 



Vcc-05 



0.7V CC 
0.45V S 0.2V0C-0 - 

tcHCL " 



ft jf 

tCLCX~* 



•-•cHCX"* 
tcLCH 



*CLCL 



Figure 20. External Clock Drive 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



vcc-o s 



0.45V 



0-2VCC+0.9 
0.2VCC-01 



X 



NOTE: 

AC inputs during testing are driven at V cc -0.5 for a logic '1' and 0.45V for a logic '0'. 
Timing measurements are made at V !H min for a logic T and V jL max for a logic 'O'. 



Figure 21 . AC Testing Input/Output 



v LOAD+° 



v LOAD~ 



VLOAD-0 1V 



).1V f 
■ 1V N. 



TIMING 
REFERENCE 
POINTS 



>V O H-0.1V 
Vol-^IV 



NOTE: 
Fori 



timing purposes, a port is no longer floating wnen a lOOmV change from load voltage occurs, 
begins to float when a lOOmV change from the loaded VohATol level occurs. Iom^cx. 2 ±20mA 



Figure 22. Float Waveform 



ICC mA 




MAX ACTIVE MODE 
l CCMAX='-50 XFREQ.t 8 



TYP ACTIVE MODE 
0.9 X FREQ. + 2.5 



MAX IDLE MODE 
TYP IDLE MODE 



8MHz 12MHz 16MHz 20MHz 

FREQ AT XTAL1 



Figure 23. l C c vs. FREQ 
Valid only within frequency specifications of the device under test 



SU00046 



1996 Aug 16 



3-84 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



Vcc 



(NQ- 
CLOCK SIGNAL - 



Vcc 
PO 



RST 

XTAL2 
XTAL1 



Ice 



Vcc 



(NO- 
CLOCK SIGNAL - 



I 





Vcc 


RST 


PO 






XTAL2 




XTAL1 




Vss 





1 



Figure 24. Ice Test Condition, Active Mode 
All other pins are disconnected 



Figure 25. Ice Test Condition, Idle Mode 
All other pins are disconnected 



VcC-05 
0.45V 



- 0.7VCC 
0.2VCC-0-1 



-tcLor* 



*-tCHCX-* 
tCLCH 







i Signal Waveform for l C c Tests in Active and idle Modes 
•clch = tcHCL = 5ns 



Vcc 





Vcc 


RST 






PO 




EA 


XTAL2 




XTAL1 




VSS 





lec 

I 



Vcc 







Figure 27. l C c Test Condition, Power Down Mode 
All other pins are disconnected. V c c = 2V to 5.5V 



1996 Aug 16 



3-85 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



87C51FA/87C51FB 



EPROM CHARACTERISTICS 

The 87C51FA/FB is programmed by using a modified Quick-Pulse 
Programming™ algorithm. It differs from older methods in the value 
used for V PP (programming supply voltage) and in the width and 
number of the ALE/PROG pulses. 

The 87C51 FA/FB contains two signature bytes that can be read and 
used by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87C51 FA/FB manufactured 
by Philips. 

Table 3 shows the logic levels for reading the signature byte, and for 
programming the program memory, the encryption table, and the 
security bits. The circuit configuration and waveforms for quick-pulse 
programming are shown in Figures 28 and 29. Figure 30 shows the 
circuit configuration for normal program memory verification. 

Quick-Pulse Programming 

The setup for microcontroller quick-pulse programming is shown in 
Figure 28. Note that the 87C51 FA/FB is running with a 3.5MHz to 
12MHz oscillator. The reason the oscillator needs to be running is 
that the device is executing internal address and program data 
transfers. 

The address of the EPROM location to be programmed is applied to 
ports 1 and 2, as shown in Figure 28. The code byte to be 
programmed into that location is applied to port 0. RST, PSEN and 
pins of ports 2 and 3 specified in Table 3 are held at the 'Program 
Code Data' levels indicated in Table 3. The ALE/PROG is pulsed 
low 15 to 25 times as shown in Figure 29. 

To program the encryption table, repeat the 15 to 25 pulse 
programming sequence for addresses through 1 FH, using the 
'Pgm Encryption Table' levels. Do not forget that after the enci 
table is programmed, verification cycles will produce only 
data. 

To program the security bits, repeat the 1 5 to 25 pulse programming 
sequence using the 'Pgm Security Bit' levels. After one security bit is 
programmed, further programming of the code memory and 
encryption table is disabled. However, the other security bit can still 
be programmed. 

Note that the EATVpp pin must not be allowed to go above the 
maximum specified Vpp level for any amount of time. Even a narrow 
glitch above that voltage can cause permanent damage to the 
device. The V PP source should be well regulated a 
and overshoot. 



Program Verification 

If security bit 2 has not been programmed, the on-chip program 
memory can be read out for program verification. The address of the 
program memory locations to be read is applied to ports 1 and 2 as 
shown in Figure 30. The other pins are held at the 'Verify Code Data' 
levels indicated in Table 3. The contents of the address location will 
be emitted on port 0. External pull-ups are required on port for this 
operation. 

If the encryption table has been programmed, the data presented at 
port will be the exclusive NOR of the program byte with one of the 
encryption bytes. The user will have to know the encryption table 
contents in order to correctly decode the verification data. The 
encryption table itself cannot be read out. 



Reading the Signature Bytes 

The signature bytes are read by the same procedure as a 
verification of locations 030H and 031 H, except that P3.6 and P3.7 
need to be pulled to a logic low. The values are: 
(030H) = 15H indicates manufactured by Philips 
(031 H) = B1H indicates 87C51 FA 
B2H indicates 87C51FB 

Program/Verify Algorithms 

Any algorithm in agreement with the conditions listed in Table 3, and 
which satisfies the timing specifications, is suitable. 

Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is exposed to 
light with wavelengths shorter than approximately 4,000 angstroms. 
Since sunlight and fluorescent lighting have wavelengths in this 
range, exposure to these light sources over an extended time (about 
1 week in sunlight, or 3 years in room level fluorescent lighting) 
could cause inadvertent erasure. For this and secondary effects, 
it is recommended that an opaque label be placed over the 
window. For elevated temperature or environments where solvents 
are being used, apply Kapton tape Fluorglas part number 2345-5, or 
equivalent. 

The recommended erasure procedure is exposure to ultraviolet light 
(at 2537 angstroms) to an integrated dose of at least 1 5W-s/cm 2 . 
Exposing the EPROM to an ultraviolet lamp of 1 2,000uW/cm 2 rating 
for 20 to 39 minutes, at a distance of about 1 inch, should be 
sufficient. 

Erasure leaves the array in an all 1s state. 



Table 3. EPROM Programming Modes 



MODE 


RST 


PSEN 


ALE/PROG 


EATVpp 


P2.7 


P2.6 


P3.7 


P3.6 


Read signature 







1 


1 














Program code data 







0* 


Vpp 


1 





1 


1 


Verify code data 







1 


1 








1 


1 


Pgm encryption table 







o- 


Vpp 


1 





1 





Pgm security bit 1 







0* 


Vpp 


1 


1 


1 


1 


Pgm security bit 2 







0* 


Vpp 


1 


1 









NOTES: 

1 . '0' = Valid low for that pin, '1 ' = valid high for that pin. 

2. Vpp = 12.75V ±0.25V. 

3. V<x = 5V±1 0% during programming and verification. 

• ALE/PROG receives 1 5 to 25 programming pulses while V PP is held at 1 2.75V. Each programming pulse is low for 50us to 1 00(is and high 
for a minimum of 10us. 



"Trademark phrase of Intel Corporation. 



1996 Aug 16 



3-86 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit 




87C51FA/87C51FB 





3.510 12MHz [=} J— 
I X 



P1 

RST 
P3.6 
P3.7 
XTAL2 



vcc 

PO 

EAWpp 
ALE/PHOG 
87C51 FA/FB F5EFJ 
P27 
P2.6 



P2.0-P2.4 



+1 2.75V 

15 TO 25 50J1S TO 100ns PULSES TO GROUND 



\ 



Figure 28. Programming Configuration 



. 



15 TO 25 PULSES 



ALE/PROG: 



"LrLTLTLTL, "TrLTLTLTLr 



10ns MIN 



sons -100ms 



n 



Figure 29. PROG Waveform 



pi 

RST 
P3.6 
P3.7 
XTAL2 

XTAL1 

vss 



vcc 

P0 

EA/Vpp 
ALE/PHOG" 
87C51FA/FB PSEN 
P2.7 
P2.6 
P2.0-P2.4 



•-C 



Figure 30. Program Verification 



1996 Aug 16 



3-87 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 87C51 FA/87C51 FB 



EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS 

T amb = 21 °C to +27°C, V cc = 5V±10%. V ss = OV (See Figure 31) 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


V PP 


Programming supply voltage 


12.5 


13.0 


V 


l PP 


Programming supply current 




50 


mA 


1/t CLCL 


Oscillator frequency 


4 


6 


MHz 


tAVGL 


Address setup to PROG low 


4 8tcLCL 






*GHAX 


Address hold after PROG 


48tc LCL 






tDVGL 


Data setup to PROG low 


48tcLCL 






tGHDX 


Data hold after PROG 


48tci_CL 






tEHSH 


P2.7 (ENABLE) high to V PP 


48tcLCL 






tSHGL 


V PP setup to PROG low 


10 




(IS 


Ighsl 


V PP hold after PROG 


10 




us 


tGLGH 


PROS width 


50 


100 


us 


UVQV 


Address to data valid 




4 8tCLCL 




tELQZ 


ENABLE low to data valid 




48tc LCL 




'ehqz 


Data float after ENABLE 





48t CL CL 




tGHGL 


PRUG" high to PROG low 


10 




us 



P1.0-P1.7 
P2.0-P2 .4 



< 



tDVGL 
tAVGL 



PROGRAMMING* 



ADDRESS 



> 



DATA IN S >. 



tGLGH 
tSHGL 



EXWpp 



« t E HSH -* 



< 



VERIFICATION 



> 



tGHDX 
tGHAX 



tGHGL 



tGHSL 



tELQV 



tAVQV 



> 



tEHQZ 



s 



NOTE: 

• FOR PROGRAMMING VERIFICATION SEE FIGURE 28. 
FOR VERIFICATION CONDITIONS SEE FIGURE 30. 



Figure 31. EPROM Programming and Verification 



1996 Aug 16 



3-88 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



DESCRIPTION 

The 87C51 FC Single-Chip 8-Bit Microcontroller Is manufactured in 
an advanced CMOS process and Is a derivative of the 80C51 
microcontroller family. The 8XC51 FC has the same instruction set 
as the 80C51. 

This device provides architectural enhancements that make it 
applicable in a variety of applications for general control systems. 
The 87C51 FC contains 32k x 8 EPROM memory, a volatile 256 x 8 
read/write data memory, four 8-bit I/O ports, three 1 6-bit timer/event 
counters, a Programmable Counter Array (PCA), a multi-source, 
four-priority-level, nested interrupt structure, an enhanced UART 
and on-chip oscillator and timing circuits. For systems that require 
extra capability, the 8XC51FC can be expanded using standard "in- 
compatible memories and logic. 

Its added features make it an even more powerful microcontroller for 
applications that require pulse width modulation, high-speed I/O and 
up/down counting capabilities such as motor control. It also has a 
more versatile serial channel that facilitates multiprocessor 
communications. 

See 83C51 FA/83C51 FB/83C51 FC/80C51 FA datasheet for ROM 
device specification. 

FEATURES 

• 80C51 central processing unit 

• 32k x 8 EPROM expandable externally to 64k bytes (87C5f FC) 

- Improved Quick Pulse programming algorithm 

- Three level program security system 

- 64 byte encryption array 

• 256 x 8 RAM, expandable externally to 64k bytes 

• Three 16-bit timer/counters 

- T2 is an up/down counter 

• Programmable Counter Array (PCA) 

- High speed output 

- Capture/compare 

- Pulse Width Modulator 

- Watchdog Timer 

• Four 8-bit I/O ports 

• Full-duplex enhanced UART 

- Framing error detection 

- Automatic address recognition 

• Power control modes 

- Idle mode 

- Power-down mode 

• Once (On Circuit Emulation) Mode 

• Five package styles 

• OTP package available 

• Programmable clock out 

• 7 interrupt sources 

• 4 level priority 



PIN CONFIGURATIONS 



T2/P1.o[T 
T2EX/P1.1[T 
ECI/P1.2|T 
CEX0/P1.3[T 
CEX1/P1.4|T 
CEX2/P1.5|T 
CEX3/P1.6[T 
CEX4/P1.7|T 

rst[T 

RxD/P3.o[lO 
TxD/P3.lQT 
INTB/P3.2[l2 
1NTT/P3.3Q3 
T0/P3.4[l4 
T1/P3.5[l5 
WRVP3.6[l6 
RD7P3.7[r7 
XTAL2[l8 
XTAL1 [l9 
Vss[20 



DUAL 
IN-LINE 
PACKAGE 



40] 



1 



13 



»] 



Vco 

POO/ADO 

P0.1/AD1 

P0.2/AD2 

P0.3/AD3 

P0.4/AD4 

P0.5/AD5 

P0.6/AD6 

P0.7/AD7 

EAWpp 

ALE/PROG" 

PSEFJ 

P2.7/A15 

P2.6/A14 

P2.5/A13 

P2.4/A12 

P2.3/A11 

P2.2/A10 

P2.1/A9 

P2.0/AB 



1996 Aug 12 



3-89 



Philips Semiconductors Preliminary specification 


CMOS single-chip 8-bit microcontroller 87C51 FC 




ORDERING INFORMATION 



EPROM 1 


TEMPERATURE RANGE C AND PACKAGE 


FREQUENCY 


DRAWING 
NUMBER 


S87C51FC-^N40 


OTP 


to +70, 40-Pin Plastic Dual In-line Package 


3.5 to 16MHz 


SOT 129-1 


S87C51FC-4F40 


uv 


to +70, 40-Pin Ceramic Dual In-line Package w/Window 


3.5to16MHz 


0590B 


S87C51FC^tA44 


OTP 


to +70, 44-Pin Plastic Leaded Chip Carrier 


3.5 to 16MHz 


SOT187-2 


S87C51FC-*K44 


UV 


to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 


3.5 to 16MHz 


1472A 


S87C51FC-4B44 


OTP 


to +70, 44-Pin Plastic Quad Flat Pack 


3.5 to 16MHz 


SOT307-2 


S87C51FC-5N40 


OTP 


-40 to +85, 40-Pin Plastic Dual In-line Package 


3.5 to 16MHz 


SOT129-1 


S87C51FC-5F40 


UV 


-40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 


3.5 to 16MHz 


0590B 


S87C51FC-5A44 


OTP 


-40 to +85, 44-Pin Plastic Leaded Chip Carrier 


3.5 to 16MHz 


SOT187-2 


S87C51FC-5B44 


OTP 


-40 to +85, 44-Pin Plastic Quad Flat Pack 


3.5 to 16MHz 


SOT307-2 



NOTE: 

1. OTP = One Time Programmable EPROM. UV = Erasable EPROM. 



1996 Aug 12 



3-90 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



BLOCK DIAGRAM 



— 



- 

P0.0-P0.7 

«! 



yccj 
vssi 

n 



PORTO 
DRIVERS 

7T 



t 



RAM ADDR 
REGISTER 



IT TT 



JOT 



PORT 2 
LATCH 



I 



rn 3 



B 






REGISTER 




ACC 



STACK 
POINTER 



P5ER»-|— 
ALE/PRO O" I • 
EAWpp— 1-" 
RST- 



TIMING 
AND 
CONTROL 



E o 



|_XTAL1 __ 

HDI— 
HhjHH 



<> <> 


<> 


TMP2 




TMP1 



31 



PORT 1 
LATCH 



31 




SFRs 
TIMERS 

P.C.A 



77 



31 



PORT 3 
LATCH 



I 



PC 
INCRE- 
MENTER 



PROGRAM 
COUNTER 



-Hlf -Wf 



1996 Aug 12 



Philips Semiconductors Preliminary specification 
_ ■ ■ — — 1 

CMOS single-chip 8-bit microcontroller 87C51 FC 



Table 1 . 8XC51 FC Special Function Reg isters 



SYMBOL 


DESCRIPTION 


DIRECT 


BIT ADDRESS. SYMBOL. OR ALTERNATIVE PORT FUNCTION 


RESET 


ADDRESS 


MSB 














LSB 


VALUE 


ACC* 


Accumulator 


EOH 


E7 


CD 


E5 


E4 


E3 


E2 




EO 


00H 


AUXR# 


Auxiliary 


8EH 




_ 






- 




_ 


An 


xxxxxxxOB 


B" 


B register 


FOH 


F7 


re 

ro 


ro 




F3 


F2 


F1 


Fn 
ru 


00H 


CCAPOH* 


Module Capture High 


FAH 


















xxxxxxxxB 


OCAPInff 


Module 1 Capture High 


cnui 
rbn 


















AAAAAAAAU 


CCAP2H# 


Module 2 Capture High 


FCH 


















xxxxxxxxB 


CCAP3H# 


Module 3 Capture High 


FDH 
















xxxxxxxxB 


CCAP4H# 


Module 4 Capture High 


FEH 
















xxxxxxxxB 


CCAP0L# 


Module Capture Low 


EAH 
















xxxxxxxxB 


CCAP1L# 


Module 1 Capture Low 


EBH 
















xxxxxxxxB 


OCAPPI # 


Mnriulp 2 Caoture Low 


ECH 


















xxxxxxxxB 


OL-MroLff 


rviuuuie o ^apiure luw 


EDH 


















xxxxxxxxB 

AAAAAAAAU 




Mnrli iIp A Canti irp I nw 


EEH 


















xxxxxxxxB 


CCAPM0# 


Module Mode 


DAH 




ECOM 


CAPP 


CAPN 


MAT 


TOG 


PWM 


ECCF 


xOOOOOOOB 


CGAPMIff 


Module l Mode 


DBH 




ECOM 


CAPP 


CAPN 


MAT 

mm i 




PWM 


ti/or 


vnnnnnnnR 

XUUUUUUUD 


CCAPM2# 


Module 2 Mode 


DCH 




ECOM 


CAPP 


CAPN 


MAT 
MAI 


I Uu 


PWM 


ECCF 


xOOOOOOOB 


CCAPM3# 


Module 3 Mode 


DDH 




ECOM 


CAPP 


CAPN 


MAT 
MM I 


I UU 


PWM 


ECCF 


XOOOOOOOB 


CCAPM4# 


Module 4 Mode 


DEH 


— 


ECOM 


CAPP 


CAPN 


MAT 
MM I 


I uu 


PWM 


ECCF 


XOOOOOOOB 
































DF 


DE 


DD 


DC 


DB 


DA 


D9 


D8 




CCON*# 


PCA Counter Control 


D8H 


Oh 


CR 


_ 


CCF4 


CCF3 


CCF2 


CCF1 


CCFO 


OOxOOOOOB 


CH# 


PPA Ccu intpr Hinh 


F9H 


















00H 


CL# 


PCA Counter Low 


E9H 


















00H 


CMOD# 


PCA Counter Mode 


D9H 


CIDL 


WDTE 


- 

1 


- 

I 




CPS1 


CPSO 


ECF 


OOxxxOOOB 


DPTR: 


Data Pointer (2 bytes) 






















DPH 


Data Pointer High 


83H 


















00H 


DPL 


Data Pointer Low 


82H 


















00H 








AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 




IE* 


Interrupt Enable 


A8H 


FA 

EA 


Fr 
EC 


ET2 


ES 


ET1 


EX1 


ETO 


EXO 


00H 














BC 


BB 


BA 


B9 


B8 




IP* 


Interrupt Priority 


B8H 




PPC 


PT2 


PS 


PT1 


PX1 


PTO 


PXO 


xOOOOOOOB 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




IPH# 


Interrupt Priority High 


B7H 




PPCH 


PT2H 


PSH 


PT1H 


PX1H 


PTOH 


PXOH 


xOOOOOOOB 








87 


86 


85 


84 


83 


82 


81 


80 




PO* 


PortO 


80H 


AD7 


AD6 


AD5 


AD4 


AD3 


AD2 


AD1 | ADO 


FFH 








97 


96 


95 


94 


93 


92 


91 


90 




PI* 


Portl 


90H 


CEX4 


CEX3 


CEX2 


CEX1 


CEXO 


EC, 


T2EX 


T2 


FFH 








A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 




P2* 


Port 2 


AOH 


AD15 


AD14 


AD13 


AD12 


AD11 


AD10 


AD9 


ADS 


FFH 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




P3* 


Port 3 


BOH 


RTJ 


WR 


T1 


TO 


TNTT 


TNTO 


TxD 


RxD 


FFH 












PCON# 


Power Control 


87H 


SM0D1 


SMODO 




POF 2 


GF1 


GFO 


PD 


IDL 


OOxxOOOOB 













* SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 



1996 Aug 12 



3-92 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



Table 1. 8XC51FC Special Function Registers (Continued) 



SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 
MSB LSB 


RESET 
VALUE 








D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 




PSW* 


Program Status Word 


DOH 


CY 


AC 


—| — — — 

I F0 


RS1 


RSO 


ov 


" 


p 


OOH 


RACAP2H# 
RACAP2L# 


Timer 2 Capture High 
Timer 2 Capture Low 


CBH 
CAH 


















OOH 
OOH 


SADDFW 
SADEN# 


Slave Address 
Slave Address Mask 


A9H 
B9H 


















OOH 
OOH 


SBUF 


Serial Data Buffer 


99H 


















xxxxxxxxB 








9F 


9E 


9D 


9C 


9B 


9A 


99 


98 




SCON* 


Serial Control 


98H 


SMO/FE 


SM1 


| SM2 


REN 


TBS 


RB8 


Tl 


R, 


OOH 


SP 


Stack Pointer 


81H 


















07H 








8F 


8E 


8D 


8C 


8B 


8A 


89 


88 




TCON* 


Timer Control 


88H 


TF1 


TR1 


| TFO 


TRO 


IE1 


IT1 


IE0 


ITO 


OOH 








CF 


CE 


CD 


CC 


CB 


CA 


C9 


C8 




T2CON- 


Timer 2 Control 


C8H 


TF2 


EXF2 


RCLK 


TCLK 


EXEN2 


TR2 


C/T2 


CP/RT2 


OOH 


T2MOD# 


Timer 2 Mode Control 


C9H 














T20E3 


DCEN 


xxxxxxOOB 


THO 

TH1 

TH2# 

TLO 

TL1 

TL2# 


Timer High 
Timer High 1 
Timer High 2 
Timer Low 
Timer Low 1 
Timer Low 2 


8CH 
8DH 
CDH 
8AH 
8BH 
CCH 


















OOH 
OOH 
OOH 
OOH 
OOH 
OOH 


















TMOD 


Timer Mode 


89H 


GATE 


C/T 


| M1 


MO 


GATE 


C/T 


M1 


MO 


OOH 



" SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 

1 . Reset value depends on reset source. 

2. Bit will not be affected by Reset. 

3. T20E— see Programmable Clock-Out. 




1996 Aug 12 



3-93 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 



CERAMIC AND PLASTIC LEADED CHIP CARRIER 
PIN FUNCTIONS 



PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 




□ 39 



□ 29 



Function 

NC- 

P1.0/T2 

P1.1/T2EX 

P1.2/ECI 

P1.3/CEX0 

P1.4/CEX1 

P1.5/CEX2 

P1.6/CEX3 

P1.7/CEX4 

RST 

P3.0/P.XD 
NC- 

P3.1/TxD 



" DO NOT I 




u 




u 


IB 




28 


Pin 


Function 


Pin 


16 


P3.4/T0 


31 


17 


P3.5/T1 


32 


16 




33 


19 


P3.7/RTJ 


34 


20 


XTAL2 


35 


21 


XTAL1 


36 


22 
I 


Vss 

NC- 
P2.0/A8 


37 
38 
39 


25 


P2.1/A9 


40 


26 


P2.2/A10 


41 


27 


P2.3/A11 


42 


26 


P2.4/A12 


43 


29 


P2.6/A13 


44 


30 


P2.6/A14 





P2.7/A 15 

FSEN 

ALE/PROG 

NC 

ES/Vpp 

P0.7/AD7 

P0.6/AD6 

P0.5/AD5 

P0.4/AD4 

P0.3/AD3 

P0.2/AD2 

P0.1/AD1 

P0.0/AD0 



O 







y 


1 










12 


22 






Pin 


Function 


Pin 


Function 


Pin 




1 


P1.5/CEX2 


16 


Vss 


31 


P0.6MD6 


2 


P1.6/CEX3 


17 


NC* 


32 


P0.5/AD5 


3 


P1.7/CEX4 


18 


P2.0/A8 


33 


P0.4/AD4 


4 


RST 


19 


P2.1/A9 


34 


P0.3/AD3 


S 


P3.0/RXD 


20 


P2.2/A10 


35 


P0.2/AD2 


6 


NC" 


21 


P2.3/A11 


36 


P0.1/AD1 


7 


P3.1/TXD 


22 


P2.4/A12 


37 


PO.O/ADO 


8 


P3.2/Tfrr0 


23 


P2.5/A13 


38 


Vcc 


S 


P3.3/TNTT 


24 


P2.6/A14 


39 


NC* 


10 


P3.4/T0 


25 


P2.7/A15 


40 


P1.0/T2 


11 


P3.5/T1 


26 


PSEN 


41 


P1.1/T2EX 


12 


P3.6/WH 


27 
28 


ALE/PRTS5 


42 


P1.2/ECI 


13 


P3.7/RD 


NC- 


43 


P1.3/CEX0 


14 


XTAL2 


29 


EAWpp 


44 


P1.4/CEX1 


15 


XTAL1 


30 


P0.7/AD7 











PIN DESCRIPTIONS 



- 





PIN NUMBER 




I 1 


MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAME AND FUNCTION 


Vss 


20 


22 


16 


I 


Ground: 0V reference. 


Vcc 


40 


44 


38 


I 


Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 


PO.0-0.7 


39-32 


43-36 


37-30 


I/O 


Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to 
them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data memory. In 
this application, it uses strong internal pull-ups when emitting 1s. Port also outputs the 
code bytes during program verification and receives code bytes during EPROM 
programming. External pull-ups are required during program verification. 


P1.0-P1.7 


1-8 

1 
2 
3 
4 
5 
6 
7 
8 


2-9 

2 
3 
4 
5 
6 
7 
8 
9 


40-44, 
1-3 

40 
41 
42 
43 
44 
1 
2 
3 


I/O 

I 
I 
I 

I/O 
I/O 
I/O 
I/O 
I/O 


Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 1 pins that are externally pulled low will source current because of the internal pull-ups. 
(See DC Electrical Characteristics: I|l). Port 1 also receives the low-order address byte 
during program memory verification. Alternate functions include: 

T2 (P1 .0): Timer/Counter 2 external count input. (See Programmable Clock-Out.) 

T2EX (P1 .1 ): Timer/Counter 2 Reload/Capture/Direction Control 

ECI (P1 .2): External Clock Input to the PCA 

CEX0 (P1.3): Capture/Compare External I/O for PCA module 

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 


P2.0-P2.7 


21-28 


24-31 


18-25 


I/O 


Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 2 pins that are externally being pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l| L ). Port 2 emits the high-order address byte 
during fetches from external program memory and during accesses to external data memory 
that use 16-bit addresses (MOVX ODPTR). In this application, it uses strong internal 
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit 
addresses (MOV @ Ri), port 2 emits the contents of the P2 special function register. Some 
Port 2 pins receive the high order address bits during EPROM programming and verification. 



1996 Aug 12 



Q QA 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



PIN DESCRIPTIONS (Continued) 



MNEMONIC 



PIN NUMBER 



DIP LCC QFP 



TYPE 



NAME AND FUNCTION 



P3.0-P3.7 



RST 



ALE/PRU5 



P5ER 



EA/Vp 



XTAL1 



XTAL2 



10-17 



10 
11 
12 
13 
14 
15 
16 
17 
9 



30 



29 



31 



19 



18 



11, 
13-19 



11 
13 
14 
15 
16 
17 
18 
19 
10 



33 



32 



35 



21 



20 



5, 
7-13 



5 
7 
8 
9 
10 
11 
12 
13 
4 



27 



26 



I/O 



I 

o 
I 
I 
I 
I 

o 
o 
I 



I/O 



15 



14 



Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 3 pins that are externally being pulled low will source current because of the pull-ups. 
(See DC Electrical Characteristics: l||_). Port 3 also serves the special features of the 80C51 
family, as listed below: 

RxD (P3.0): Serial input port 

TxD (P3.1): Serial output port 

INTO (P3.2): External interrupt 

1WTT (P3.3): External interrupt 

TO (P3.4): Timer external input 

T1 (P3.5): Timer 1 external input 

WR (P3.6): External data memory write strobe 

RU (P3.7): External data memory read strobe 

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to V S s permits a power-on reset using only an external 
capacitor to V C c. 

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the 
address during an access to external memory. In normal operation, ALE is emitted at a 
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. 
Note that one ALE pulse is sk ipped d uring each access to external data memory. This pin is 
also the program pulse input (PROG) during EPROM programming. ALE can be disabled by 
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. 

Program Store Enable: The read strobe to external program memory. When the 8XC51 FC 
is executing code from the extemalprogram memory, PSEN is activated twice each 
machine cycle, except thattw o PSEN activations are skipped during each access to 
external data memory. PSEN is not activated during fetches from internal program memory. 

External Access Enable/Programming Supply Voltage: EA must be externally held low 
to enable the device to fetch code from external program memory locations 0000H and 
7FFFH. If EA is held high, the device executes from internal program memory unless the 
program counter contains an address greater than 7FFFH. This pin also receives the 
12.75V programming supply voltage (V PP ) during EPROM programming. If security bit 1 is 
programmed, EA will be internally latched on Reset. 

Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 

Crystal 2: Output from the inverting oscillator amplitier. 



NOTE: 

To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than Vcc + 0.5V or Vss - 0.5V, respectively. 



TIMER 2 

This is a 16-bit up or down counter, which can be operated as either 
a timer or event counter. It can be operated in one of three different 
modes (autoreload, capture or as the baud rate generator for the 
UART). 

In the autoreload mode the Timer can be set to count up or down by 
setting or clearing the bit DCEN in the T2CON Special Function 
Register. The SFR's RCAP2H and RCAP2L are used to reload the 
Timer upon overflow or a 1-to-0 transition on the T2EX input (P1 .1). 

In the Capture mode Timer 2 can either set TF2 and generate an 
interrupt or capture its value. To capture Timer 2 in response to a 
1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON 



As the baud rate generator, Timer 2 is selected by setting TCLK 
and/or RCLK in T2CON. As the baud rate generator Timer 2 is 
incremented at V 2 the oscillator frequency. 



POWER OFF FLAG 

The Power Off Flag (POF) is set by on-chip circuitry when the V cc 
level on the 8XC51 FC rises from to 5V. The POF bit can be set or 
cleared by software allowing a user to determine if the reset is the 
result of a power-on or a warm start after powerdown. The V cc level 
must remain above 3V for the POF to remain unaffected by the V cc 



must be set. Timer 2 is then captured in SFR's RCAP2H and 
RCAP2L. 



1996 Aug 12 



3-95 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 

oscillator. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements 
on the duty cycle of the external clock signal, because the input to 
the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 

Reset 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-on reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. At power-on, the voltage on 
V cc and RST must come up at the same time for a proper start-up. 
Ports 1 , 2, and 3 will asynchronously be driven to their reset 
condition when a voltage above V| H i is applied to RESET. 

Idle Mode 

In the idle mode, the CPU puts itself to sleep while all of the on-chip 
peripherals stay active. The instruction to invoke the idle mode is the 
last instruction executed in the normal operating mode before the 
idle mode is activated. The CPU contents, the on-chip RAM, and all 
of the special function registers remain intact during this mode. The 
idle mode can be terminated either by any enabled interrupt (at 
which time the process is picked up at the interrupt service routine 
and continued), or by a hardware reset which starts the processor in 
the same manner as a power-on reset. 

Power-Down Mode 

To save even more power, a Power Down mode can be invoked by 
software. In this mode, the oscillator is stopped and the instruction 
that invoked Power Down is the last instruction executed. The 
on-chip RAM and Special Function Registers retain their values until 
the Power Down mode is terminated. 

On the 8XC5t FC either a hardware reset or external interrupt can 
use an exit from Power Down. Reset redefines all the SFRs but 
does not change the on-chip RAM. An external interrupt allows both 
the SFRs and the on-chip RAM to retain their values. 

To properly terminate Power Down the reset or external interrupt 
should not be executed before V cc is restored to its normal 
operating level and must be held active long enough for the 
oscillator to restart and stabilize (normally less than 10ms). 

With an external interrupt, INTO and INT1 must be enabled and 
configured as level-sensitive. Holding the pin low restarts the 
oscillator but bringing the pin back high completes the exit. Once the 
interrupt is serviced, the next instruction to be executed after RETI 
will be the one following the instruction that put the device into 
Power Down. 



Design Consideration 

• When the idle mode is terminated by a hardware reset, the device 
normally resumes program execution, from where it left off, up to 
two machine cycles before the internal rest algorithm takes 
control. On-chip hardware inhibits access to internal RAM in this 
event, but access to the port pins is not inhibited. To eliminate the 
possibility of an unexpected write when Idle is terminated by reset, 
the instruction following the one that invokes Idle should not be 
one that writes to a port pin or to external memory. 

• The windowed parts must be covered with an opaque label to 
assure proper chip operation. 

ONCE™ Mode 

The ONCE ("On-Circuit Emulation") Mode facilitates testing and 
debugging of systems using the 8XC51 FC without the 8XC51 FC 
having to be removed from the circuit. The ONCE Mode is invoked 
by: 

1 . Pull ALE low while the device is in reset and F5ETJ is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in ONCE Mode, the Port pins go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the 8XC51 FC is in 
this mode, an emulator or test CPU can be used to drive the circuit. 
Normal operation is restored when a normal reset is applied. 

Programmable Clock-Out 

The 8XC51 FC has a new feature. A 50% duty cycle clock can be 
programmed to come out on P1 .0. This pin, besides being a regular 
I/O pin, has two alternate functions. It can be programmed (1) to 
input the external clock for Timer/Counter 2 or (2) to output a 50% 
duty cycle clock ranging from 61 Hz to 4MHz at a 1 6MHz operating 
frequency. 

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in 
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit 
TR2 (T2CON.2) also must be set to start the timer. 

The Clock-Out frequency depends on the oscillator frequency and 
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) 
as shown in this equation: 

OscillatorFrequency 
4 x (65536 - RCAP2H, RCAP2L) 

In the Clock-Out mode Timer 2 roll-overs will not generate an 
interrupt. This is similar to when it is used as a baud-rate generator. 
It is possible to use Timer 2 as a baud-rate generator and a clock 
generator simultaneously. Note, however, that the baud-rate and the 
Clock-Out frequency will be the same. 



Table 2. External Pin Status During Idle and Power-Down Mode 



MODE 


PROGRAM 
MEMORY 


ALE 


PSEN 


PORT 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 




Float 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Float 


Data 


Data 


Data 



1996 Aug 12 



3-96 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



CPS1 


CPSO 











1 


1 





1 


1 



Programmable Counter Array (PCA) 

The Programmable Counter Array is a special Timer that has five 
1 6-bit capture/compare modules associated with it. Each of the 
modules can be programmed to operate in one of four modes: rising 
and/or falling edge capture, software timer, high-speed output, or 
pulse width modulator. Each module has a pin associated with it in 
port 1 . Module is connected to P1 3(CEX0), module 1 to 
P1 .4(CEX1 ), etc. The basic PCA configuration is shown in Figure 1 . 

The PCA timer is a common time base for all five modules and can 
be programmed to run at: 1/12 the oscillator frequency, 1/4 the 
oscillator frequency, the Timer overflow, or the input on the ECI pin 
(P1 .2). The timer count source is determined from the CPS1 and 
CPSO bits in the CMOD SFR as follows (see Figure 4): 

PCA Timer Count Source 

1/12 oscillator frequency 
1/4 oscillator frequency 
Timer overflow 
External Input at ECI pin 

In the CMOD SFR are three additional bits associated with the PCA. 
They are CIDL which allows the PCA to stop during idle mode, 
WDTE which enables or disables the watchdog function on module 
4, and ECF which when set causes an interrupt and the PCA 
overflow flag CF (in the CCON SFR) to be set when the PCA timer 
overflows. These functions are shown in Figure 2. 

The watchdog timer function is implemented in module 4 (see Figure 
14). 

The CCON SFR contains the run control bit for the PCA and the 
flags for the PCA timer (CF) and each module (refer to Figure 5). To 
run the PCA the CR bit (CCON.6) must be set by software. The 
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when 
the PCA counter overflows and an interrupt will be generated if the 
ECF bit in the CMOD register is set, The CF bit can only be cleared 
by software. Bits through 4 of the CCON register are the flags for 
the modules (bit for module 0, bit 1 for module 1 , etc.) and are set 
by hardware when either a match or a capture occurs. These flags 
also can only be cleared by software. The PCA interrupt system 
shown in Figure 3. 

Each module in the PCA has a special function register associated 
with it. These registers are: CCAPMO for module 0, CCAPM1 for 
module 1 , etc. (see Figure 6). The registers contain the bits that 
control the mode that each module will operate in. The ECCF bit 
(CCAPMn.O where n=0, 1 , 2, 3, or 4 depending on the module) 
enables the CCF flag in the CCON SFR to generate an interrupt 



when a match or compare occurs in the associated module. PWM 
(CCAPMn.1) enables the pulse width modulation mode. The TOG 
bit (CCAPMn.2) when set causes the CEX output associated with 
the module to toggle when there is a match between the PCA 
counter and the module's capture/compare register. The match bit 
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON 
register to be set when there is a match between the PCA counter 
and the module's capture/compare register. 

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) 
determine the edge that a capture input will be active on. The CAPN 
bit enables the negative edge, and the CAPP bit enables the 
positive edge. If both bits are set both edges will be enabled and a 
capture will occur for either transition. The last bit in the register 
ECOM (CCAPMn.6) when set enables the comparator function. 
Figure 7 shows the CCAPMn settings for the various PCA functions. 

There are two additional registers associated with each of the PCA 
modules. They are CCAPnH and CCAPnL and these are the 
registers that store the 1 6-bit count when a capture occurs or a 
compare should occur. When a module is used in the PWM mode 
these registers are used to control the duty cycle of the output. 

PCA Capture Mode 

To use one of the PCA modules in the capture mode either one or 
both of the CCAPM bits CAPN and CAPP for that module must be 
set. The external CEX input for the module (on port 1 ) is sampled for 
a transition. When a valid transition occurs the PCA hardware loads 
the value of the PCA counter registers (CH and CL) into the 
module's capture registers (CCAPnL and CCAPnH). If the CCFn bit 
for the module in the CCON SFR and the ECCFn bit in the CCAPMn 
SFR are set then an interrupt will be generated. Refer to Figure 10. 

16-bit Software Timer Mode 

The PCA modules can be used as software timers by setting both 
the ECOM and MAT bits in the modules CCAPMn register. The PCA 
timer will be compared to the module's capture registers and when a 
match occurs an interrupt will occur if the CCFn (CCON SFR) and 
the ECCFn (CCAPMn SFR) bits for the module are both set (see 
Figure 11). 

High Speed Output Mode 

In this mode the CEX output (on port 1) associated with the PCA 
module will toggle each time a match occurs between the PCA 
counter and the module's capture registers. To activate this mode 
the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must 
be set (see Figure 12). 



| 16 BITS 



PCA TIMER/COUNTER 



MODULE 



TIME BASE FOR PCA MODULES 

MODULE FUNCTIONS: 
16-BIT CAPTURE 
16-BIT TIMER 

16-BIT HIGH SPEED OUTPUT 
S-BIT PWM 

WATCHDOG TIMER (MODULE 4 ONLY) 



P1.3/CEX0 



P1.4/CEX1 
*f~| P1.5/CEX2 



P1.6/CEX3 



-►O P1.7/CEX4 



Figure 1. Programmable Counter Array (PCA) 



1996 Aug 12 



3-97 



Preliminary specification 



Philips Semiconductors 



CMOS single-chip 8-bit microcontroller 87C51 FC 




TIMER 
OVERFLOW 



J 

: 

I — T\ 



EXTERNAL INPUT |-|_ 
(P1.2/ECI) |_T 



<r<o 



ofo. 



- i 00 .. 




; i 0.1. .. 


DECODE 







TO PCA 
MODULES 



16-BIT UP COUNTER 



CIDL 


WDTE 








CPS1 


cpso 


ECF 


1 


i 


CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



CMOD 
(D9H) 



CCON 
(D8H) 



SU00033 



Figure 2. PCA Timer/Counter 



PCA TIMER/COUNTER 



CF 

' z ' 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



T 



CCON 
(D8H) 





IE.6 




IE.7 






EC 




EA 








TO 






INTERRUPT 






PRIORITY 










DECODER 










► 









: | ecf I 



SU00034 



Figure 3. PCA Interrupt System 



1996 Aug 12 



3-98 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



CMOD Address = OD9H 



Reset Value = OOXX X000B 



Bit Addressable 



CIDL 


WDTE 








CPS1 


CPSO 


ECF 


7 


6 


5 


4 


3 


2 


1 






Bit: 



Symbol 



Function 



CIDL 
WDTE 

CPS1 
CPSO 



ECF 



Counter Idle control: CIDL = programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs 
it to be gated off during idle. 

Watchdog Timer Enable: WDTE = disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. 
Not implemented, reserved for future use." 
PCA Count Pulse Select bit 1 . 

PCA Input** 

Internal clock, f sc + 1 2 
Internal clock, fosc + 4 
Timer overflow 

External clock at ECI/P1 .2 pin (max. rate = fosc * 8) 

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = disables 
that function of CF. 




NOTE: 

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke 

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 
" 'OSC = oscillator frequency 



new features. In that case, the reset or inactive value of Ihe 



Figure 4. CMOD: PCA Counter Mode Register 



CCON Address = OD8H 



Bit Addressable 



Reset Value = 00X0 0000B 





CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCF0 


Bit: 


7 


6 


5 


4 


3 


2 


1 





Symbol Function 

















CF 
CR 



CCF4 
CCF3 
CCF2 
CCF1 
CCF0 



PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is 
set. CF may be set by either hardware or software but can only be cleared by software. 

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA 
counter off. 

Not implemented, reserved for future use". 

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 
PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. 



NOTE: 

• Use 

new bit will be 0. 



should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case. 
0. and its active value will be 1 . The value read from a reserved bit is indeterminate. 



the reset or inactive value of the 



Figure 5. CCON: PCA Counter Control Register 



1996 Aug 12 



3-99 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



CCAPMn Address 



ECOMn 
CAPPn 
CAPNn 
MATn 

TOGn 



CCAPMO 
CCAPM1 
CCAPM2 
CCAPM3 
CCAPM4 

Not Bit Addressable 



ODAH 
ODBH 
ODCH 
ODDH 
ODEH 



Reset Value = X000 0000B 









ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 


Symbol 


Bit: 
Func 


7 

tion 


6 5 4 


3 


2 


1 






Not implemented, reserved for future use*. 
Enable Comparator. ECOMn = 1 enables the comparator function. 
Capture Positive, CAPPn = 1 enables positive edge capture. 
Capture Negative, CAPNn = 1 enables negative edge capture. 
Match. When MATn = 1 , a match of the PCA counter with this module's c 
in CCON to be set, flagging an interrupt. 
Toggle. When TOGn = 1 , a match of the PCA counter with this module's compare/capture register causes the CEXn 
pin to toggle. 

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. 
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. 



r causes the CCFn bit 



ECCFn 



'User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that c 
bit will be 0. and its active value will be 1 . The value read from a reserved bit is indeterminate. 



r. the reset or inactive value of the new 
SU00037 



Figure 6. CCAPMn: PCA Modules Compare/Capture Registers 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 


MODULE FUNCTION 


X 























No operation 


X 


X 


1 














X 


1 6-bit capture by a positive-edge trigger on CEXn 


X 


X 





1 











X 


1 6-bit capture by a negative trigger on CEXn 


X 


X 


1 


1 











X 


1 6-bit capture by a transition on CEXn 


X 


1 








1 








X 


1 6-bit Software Timer 


X 


1 








1 


1 





X 


16-bit High Speed Output 


X 


1 














1 





8-bit PWM 


X 


1 








1 


X 





X 


Watchdog Timer 



Pulse Width Modulator Mode 

All of the PCA modules can be used as PWM outputs. Figure 13 
shows the PWM function. The frequency of the output depends on 
the source for the PCA timer. All of the modules will have the same 
frequency of output because they all share the PCA timer. The duty 
cycle of each module is independently variable using the module's 
capture register CCAPLn. When the value of the PCA CL SFR is 
less than the value in the module's CCAPLn SFR the output will be 
low, when it is equal to or greater than the output will be high. When 
CL overflows from FF to 00, CCAPLn is reloaded with the value in 
CCAPHn. the allows updating the PWM without glitches. The PWM 
and ECOM bits in the module's CCAPMn register must be set to 
enable the PWM mode. 



Figure 7. PCA Module Modes (CCAPMn Register) 



1996 Aug 12 



3-100 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



Enhanced UART 

The UART operates in all of the usual modes that are described in 
the first section of this book for the 80C51 . In addition the UART can 
perform framing error detect by looking for missing stop bits, and 
automatic address recognition. The 8XC51 FC UART also fully 
supports multiprocessor communication as does the standard 
80C51 UART. 

When used for framing error detect the UART looks for missing stop 
bits in the communication. A missing bit will set the FE bit in the 
SCON register. The FE bit shares the SCON.7 bit with SMO and the 
function of SCON.7 is determined by PCON.6 (SMODO) (see Figure 
15). if SMODO is set then SCON.7 functions as FE. SCON.7 
functions as SMO when SMODO is cleared. When used as FE 
SCON.7 can only be cleared by software. Refer to Figure 16. 

Automatic Address Recognition 

Automatic Address Recognition is a feature which allows the UART 
to recognize certain addresses in the serial bit stream by using 
hardware to make the comparisons. This feature saves a great deal 
of software overhead by eliminating the need for the software to 
examine every serial address which passes by the serial port. This 
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART 
modes, mode 2 and mode 3, the Receive Interrupt flag (Rl) will be 
automatically set when the received byte contains either the "Given" 
address or the "Broadcast" address. The 9 bit mode requires that 
the 9th information bit is a 1 to indicate that the received information 
is an address and not data. Automatic address recognition is shown 
in Figure 1 7. 

The 8 bit mode is called Mode 1 . In this mode the Rl flag will be set 
if SM2 is enabled and the information received has a valid stop bit 
following the 8 address bits and the information is either a Given or 
Broadcast address. 

Mode is the Shift Register mode and SM2 is ignored. 

Using the Automatic Address Recognition feature allows a master to 
selectively communicate with one or more slaves by invoking the 
Given slave address or addresses. All of the slaves may be 
contacted by using the Broadcast address. Two special Function 
Registers are used to define the slave's address, SADDR, and the 
address mask, SADEN. SADEN is used to define which bits in the 
SADDR are to b used and which bits are "don't care". The SADEN 
mask can be logically ANDed with the SADDR to create the "IGiven" 
address which the master will use for addressing each of the slaves. 
Use of the Given address allows multiple slaves to be recognized 
while excluding others. The following examples will help to show the 
versatility of this scheme: 

Slave SADDR = 1100 0000 

SADEN S 1111 1101 

Given = 1100 00X0 



In a more complex system the following could be used to select 
slaves 1 and 2 while excluding slave 0: 



Slave 


SADDR 


1100 0000 




SADEN 


1111 1001 




Given 


1100 oxxo 


Slave 1 


SADDR 


1110 0000 




SADEN 


1111 1010 




Given 


1110 oxox 


Slave 2 


SADDR 


1110 0000 




SADEN 


1111 1100 




Given 


1110 ooxx 



Slave 1 



SADDR 
SADEN 
Given 



1100 0000 
1111 1110 
1100 000X 



In the above example SADDR is the same and the SADEN data is 
used to differentiate between the two slaves. Slave requires a in 
bit and it ignores bit 1 . Slave 1 requires a in bit 1 and bit is 
ignored. A unique address for Slave would be 1100 0010 since 
slave 1 requires a in bit 1 . A unique address for slave 1 would be 
1100 0001 since a 1 in bit will exclude slave 0. Both slaves can be 
selected at the same time by an address which has bit = (for 
slave 0) and bit 1 = (for slave 1). Thus, both could be addressed 
with 1100 0000. 



In the above example the differentiation among the 3 slaves is in the 
lower 3 address bits. Slave requires that bit = and it can be 
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = and 
it can be uniquely addressed by 1110 and 0101. Slave 2 requires 
that bit 2 = and its unique address is 1 1 1 001 1 . To select Slaves 
and 1 and exclude Slave 2 use address 1110 0100, since it is 
necessary t make bit 2 = 1 to exclude slave 2. 

The Broadcast Address for each slave is created by taking the 
logical OR of SADDR and SADEN. Zeros in this result are teated as 
don't-cares. In most cases, interpreting the don't-cares as ones, the 
broadcast address will be FF hexadecimal. 

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR 
address 0B9H) are loaded with 0s. This produces a given address 
of all "don't cares" as well as a Broadcast address of all "don't 
cares", this effectively disables the Automatic Addressing mode and 
allows the microcontroller to use standard 80C51 type UART drivers 
which do not make use of this feature. 

Reduced EMI Mode 

The AO bit (AUXR.O) in the AUXR register when set disables the 
ALE output. 

8XC51FC Reduced EMI Mode 

AUXR (8EH) 

7 6 5 4 3 2 1 

I - I - I - I - I - I - I - I " I 

AO: Turns off ALE output. 

Interrupt Priority Structure 

The 8XC51 FC has a 7-source four-level interrupt structure. There 
are 3 SFRs associated with the interrupts on the 8XC51 FC. They 
are the IE and IP. (See Figures 8 and 9.) In addition, there is the IPH 
(Interrupt Priority High) register that makes the four-level interrupt 
structure possible. The IPH is located at SFR address B7H. The 
structure of the IPH register and a description of its bits is shown 
below: 

IPH (Interrupt Priority High) (B7H) 

r 6 5 4 3 2 1 

| - | PPCH | PT2H | PSH | PT1H | PX1H | PTOH | PXOH | 

IPH.O PXOH External interrupt priority high 

IPH.1 PTOH Timer interrupt priority high 

IPH .2 PX1H External interrupt 1 priority high 

IPH.3 PT1H Timer 1 interrupt priority high 

IPH.4 PSH Serial Port interrupt high 

IPH.5 PT2H Timer 2 interrupt priority high 

IPH.6 PPCH PCA interrupt priority high 

IPH.7 — Not implemented 



1996 Aug 12 



3-101 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



The function of the IPH SFR is simple and when combined with the 
IP SFR determines the priority of each interrupt. The priority of each 
interrupt is determined as shown in the following table: 



PRIORITY BITS 


INTERRUPT PRIORITY LEVEL 


IPH.x 


IP.x 








Level (lowest priority) 





1 


Level 1 


1 





Level 2 


t 


f 


Level 3 (highest priority) 



The priority scheme for servicing the interrupts is the same as that 
for the 80C51 , except there are four interrupt levels on the 8XC51 FC 
rather than two as on the 80C51 . An interrupt will be serviced as 
long as an interrupt of equal or higher priority is not already being 
serviced. If an interrupt of equal or higher level priority is being 
serviced, the new interrupt will wait until it is finished before being 
serviced. If a lower priority level interrupt is being serviced, it will be 
stopped and the new interrupt serviced. When the new interrupt is 
finished, the lower priority level interrupt that was stopped will be 
completed. 



IE (0A8H) 



7 


6 


5 


4 


3 


2 


1 





EA 


EC 


ET2 


ES 


ET1 


EX1 


ETO 


EXO 



BIT 

IE.7 

IE.6 
IE.5 
IE.4 
IE.3 
IE.2 
IE.1 
IE.0 



SYMBOL 

EA 

EC 

ET2 

ES 

ET1 

EX1 

ETO 

EXO 



nable Bit = 1 enables the 
nable Bit = disables it. 



FUNCTION 

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1 , ei 
enabled or disabled by setting or clearing its enable bit. 
PCA interrupt enable bit. 
Timer 2 interrupt enable bit. 
Serial Port interrupt enable bit. 
Timer 1 interrupt enable bit. 
External interrupt 1 enable bit. 
Timer interrupt enable bit. 
External interrupt enable bit. 



- 



can be individually 



Figure 8. IE Registers 



7 


6 


5 


4 


3 


2 


1 









PPC 


PT2 


PS 


PT1 


PX1 


PTO 


PXO 







IP (0B8H) 


BIT 


SYMI 


IP.7 
IP.6 


PPC 


IP.5 


PT2 


IP.4 


PS 


IP.3 


PT1 


IP.2 


PX1 


IP.1 


PTO 


IPO 


PXO 



Priority Bit = 1 assigns high priority 
Priority Bit = assigns low priority 

IL FUNCTION 

Not implemented, reserved for future use. 

PCA interrupt priority bit. 

Timer 2 interrupt priority bit. 

Serial Port interrupt priority bit. 

Timer 1 interrupt priority bit. 

External interrupt 1 priority bit. 

Timer interrupt priority bit. 

External interrupt priority bit. 



I 



IP Registers 



■ 

■ 



1996 Aug 12 



3-102 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



Table 3. Interrupt Table 



SOURCE 


POLLING PRIORITY 


REQUEST BITS 


HARDWARE CLEAR? 


VECTOR ADDRESS 


XO 


1 


IE0 


N(L) 1 Y(T)2 


03H 


TO 


2 


TPO 


Y 


OB 


X1 


3 


IE1 


N(L) Y(T) 


13 


T1 


4 


TF1 


Y 


1B 


SP 


5 


R1.TI 


N 


23 


T2 


6 


TF2, EXF2 


N 


2B 


PCA 


7 


CF, CCFn 
n = 0-4 


N 


33 



NOTES: 

1 . L = Level activated 

2. T = Transition activated 



CF 


CR 




CCF4 


CCF3 


CCF2 


CCF1 


CCFO 



CCON 
(D8H) 



PCA INTERRUPT 



(TO CCFn) 



PCA TIMER/COUNTER 



7- 



CAPPn CAPNn 



r rrFn CCAPMn. n= 10 4 
(DAH-DEH) 



Figure 10. PCA Capture Mode 



WRITE TO 
CCAPnH RESET 




16-BIT COMPARATOR 













CH 


CL 



PCA TIMER/COUNTER 



CCF4 CCF3 CCF2 CCF1 CCFO 



CCON 
(D8H) 



(TO CCFn) 

i 



PCA INTERRUPT 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




t 



















CCAPMn, n=0to4 
(DAH-DEH) 



Figure 11. PCA Compare Mode 



1996 Aug 12 



3-103 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



i 



WRITE TO 
CCAPnH RESET 



- 



— CCF4 



CCON 
(D8H) 



WRITE TO 
CCAPnL 







•v 



CCAPnH 


CCAPnL 










15-BIT COMPARATOR 










I. 


CH 


CL 



(TO CCFn) 



t WfA *" PCA INTERRUPT 



DC — »□ CEXn 



PCA TIMER/COUNTER 









ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




t 










1 








CCAPMn, n: .4 
(DAH-DEH) 



Figure 12. PCA High Speed Output Mode 



□ 



8-BIT 
COMPARATOR 



7T 



PCA TIMER/COUNTER 



i »Q CEXn 





ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 
























CCAPMn, n: .4 
(DAH - DEH) 







Figure 13. PCA PWM Mode 



1996 Aug 12 



3-104 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



WRITE TO 

CCAP4H Htbt ' 



WRITE TO 
CCAP4L 



CIDL 


WDTE 








CPS1 


CPSO 


ECF 



9 ^r^r 



16-BIT COMPARATOR 



7T 



PCA TIMER/COUNTER 



CMOD 
(D9H) 



-I 



1 










CH 


CL 







ECOMn 


CAPPn 


CAPNn 


MATn 


TOGn 


PWMn 


ECCFn 




T 








1 


X 





X 



CCAPM4 
(DEH) 



Figure 1 4. PCA Watchdog Timer 



SM1 



SM2 



REN 
TB8 
RB8 

Tl 

Rl 



NOTE: 

■SMODO is 

"lose = 



SCON Address = 98H 
Bit Addressable 



Reset Value = 0000 0000B 





SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


Bit: 


7 


6 


5 


4 


3 


2 


1 






(SMODO = 0/1)* 
Symbol Function 



Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid 
frames but should be cleared by software. The SMODO bit must be set to enable access to the FE bit. 



Serial Port Mode Bit 0, (SMODO must = to access bit SM0) 



SM0 SM1 Ft 


lode 


Description 


Baud Rate" 








shift register 


f0Sc/12 


1 


1 


8-bit UART 


variable 


1 


2 


9-bit UART 


fosc/64 or fosc/32 


1 1 


3 


9-bit UART 


variable 



Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the 
received 9th data bit (RB8) is 1 , indicating an address, and the received byte is a Given or Broadcast Address. 
In Mode 1 , if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a 
Given or Broadcast Address. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In modes 2 and 3, the 9th data bit that was received. In Mode 1 , if SM2 = 0, RB8 is the stop bit that was received. 
In Mode 0, RB8 is not used. 

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the 
other modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in 
the other modes, in any serial reception (except see SM2). Must be cleared by software. 



located al PCON6. 
frequency 



SU00043 



Figure 15. SCON: Serial Port Control Register 



1996 Aug 12 



3-105 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



START 
BIT 



: SCON.7 = SMO 
1 : SCON.7 = FE 



ONLY IN STOP 
MODE 2, 3 BIT 



SET FE BIT IF STOP BIT IS (FRAMING ERROR) 
SMO TO UART MODE CONTROL 



SMO/FE 


SM1 


SM2 


REN 


TBS 


RB6 


Tl 


Rl 




SMOD1 


SMODO 


OSF 


POF 


LVF 


GFO 


GF1 


IDL 



SCON 
(98H) 



PCON 
(B7H) 



Figure 16. UART Framing Error Detection 



1 1 
1 o 




SMO 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 



RECEIVED ADDRESS DO TO D7 
PROGRAMMED ADDRESS 



COMPARATOR 



IN UART MODE 2 OR MODE 3 AND SM2 = 1: 

INTERRUPT IF REN=1 . RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" 

- WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES 

- WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. 



Figure 17. UART Multiprocessor Communication, Automatic Address Recognition 
ABSOLUTE MAXIMUM RATINGS 1 ' 2 - 3 



SCON 
(98H) 



PARAMETER 


RATING 


UNIT 


Operating temperature under bias 


to +70 or -40 to +85 


°C 


Storage temperature range 


-65 to +150 


°c 


Voltage on ES/Vpp pin to Vss 


to +13.0 


V 


Voltage on any other pin to Vss 


-0.5 to +6.5 


V 


Maximum Iol per I/O pin 


15 


mA 


Power dissipation (based on package heat transfer limitations, not 
device power consumption) 


1.5 


W 



NOTES: 

1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V ss unless otherwise 
noted. 



1996 Aug 12 



3-106 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 



87C51FC 



DC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to +85°C, V C c = 5V +1 0%, V S s = 0V 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 


V|L 


Input low voltage, except EA" 




-0.5 




0.2V C c-0-1 


V 












V|L1 


Input low voltage to EA 









0.2Vcc-0.3 


V 


V IH 


Input high voltage, except XTAL1 , RST 




0.2V OC +0.9 




Vcc+0.5 


V 


V|H1 


Input high voltage, XTAL1 , RST 




0.7V CC 




Vcc+0.5 


V 


Vol 


— ; 

Output low voltage, ports 1 , 2, 3 s 


Iol = 1 .6mA2 






0.45 


V 


v 0L1 


Output low voltage, port 0, ALE, PSEN 8 


Iol = 3.2mA2 






0.45 


V 


VoH 


Output high voltage, ports 1 , 2, 3 3 


Ioh = -30(iA 


V cc - 0.7 






V 


VoH1 


Output high voltage (port in external bus mode), 
ALE 9 , PEER 3 


I h = -3.2mA 


Vcc-0.7 






V 


IK 


Logical input current, ports 1, 2, 3 


V| N = 0.45V 






-50 


HA 


Itl 


Logical 1-to-0 transition current, ports 1 , 2, 3 6 


See note 4 






-650 


MA 


III 


Input leakage current, port 


0.45 V| N < 
V C c - 0-3 






+10 


ma 












Ice 


Power supply current: 
Active mode @ 1 6MHz 
Idle mode 3 16MHz 
Power-down mode 


See note 5 




15 
3 
10 


32 
10 
100 


mA 
mA 
MA 


Rrst 


Internal reset pull-down resistor 




40 




225 


kft 


C|0 


Pin capacitance 10 (except EA) 








15 


PF 



NOTES: 

1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the V i_s of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 1 0OpF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Iol can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs ex ceed th e test conditions. 

3. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V !N is approximately 2V. 

5. See Figures 25 through 28 for l C c test conditions. 

6. This value applies to T amb = 0°C to +7 0°C Fo r T amb = -40°C to +85°C, Itl = -750nA. 

7. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

8. Under steady state (non-transient) conditions, Iol must be externally limited as follows: 

Maximum Iol per port pin: 1 5mA ('NOTE: This is 85°C specification.) 

Maximum Iol per 8-bit port: 26mA 

Maximum total Iol for all outputs: 71 mA 
If l L exceeds the test condition, V 0L may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

VLE is off then V h is the voltage specification. 

not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF 



9. ALE is tested to V m, 

10. Pin capacitance is char; 
(except ES is 25pF). 



1996 Aug 12 



3-107 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



AC ELECTRICAL CHARACTERISTICS 

Tamb = "°C to +70°C or -^0°C to +85°C, V cc = 5V ±1 0%, V SS = 0V 1 ■ 2 ' 3 



SYMBOL 


FIGURE 


PARAMETER 


16MHz CLOCK 


VARIABLE CLOCK 




UNIT 


MIN 


MAX 


MIN 


MAX 


1 /tcLCL 


18 


Oscillator frequency -4 -5 






3.5 


16 


MHz 




18 


ALE pulse width 


85 




ZtcLCL-^O 




ns 


'avll 


18 


Address valid to ALE low 


22 




tCLCL-^0 




ns 


*LLAX 


18 


Address hold after ALE low 


32 




(clcl-30 




ns 


'lliv 


18 


ALE low to valid instruction in 




150 




4tcLCL-10° 


ns 


'llpl 


18 


ALE low to PSER low 


32 




tcLCL-30 




ns 


tpLPH 


18 


PSEN pulse width 


142 




3tcLCL-45 




ns 


tpLIV 4 


18 


PSEN low to valid instruction in 




82 




3tcLCL"1°5 


ns 


tpxix 


18 


Input instruction hold after PSEN 












ns 


tpxiz 


18 


Input instruction float after PSEN 




37 




tCLCL-ZS 


ns 


( AVIV 


18 


Address to valid instruction in 




207 




5tcLCL-105 


ns 


tpLAZ 


18 


PSEN low to address float 




10 




10 


ns 


Data Memory 


tRLRH 


19. 20 


RD pulse width 


275 




6tci_CL-100 




ns 


'WLWH 


19, 20 


WR pulse width 


275 




6tCLCL~100 




ns 


tRLDV 


19, 20 


RD low to valid data in 




147 




5tcLCL-165 


ns 


tRHDX 


19, 20 


Data hold after RD 












ns 


tRHDZ 


19, 20 


Data float after RD 




65 




2tci_CL-60 


ns 


•lldv 


19, 20 


ALE low to valid data in 




350 




8tcLCL-150 


ns 


'avdv 


19, 20 


Address to valid data in 




397 




9tcLCL-165 


ns 


Illwl 


19,20 


ALE low to RD or WR low 


137 


237 


3tci_CL-50 


3tCLCL+50 


ns 


WwL 


19, 20 


Address valid to WR low or RD low 


175 




4tcLCL-130 




ns 


tQVWX 


19, 20 


Data valid to WR transition 


42 




tCLCL-50 




ns 


'WHQX 


19, 20 


Data hold after WR 


42 




tCLCL-50 




ns 


tQVWH 


20 


Data valid to WR high 


287 




7t C LCL-150 




ns 


'rlaz 


19,20 


RD low to address float 












ns 


*WHLH 


19, 20 


RD or WR high to ALE high 


40 


87 


tOLOL-^0 


tcLCL+40 


ns 


External Clock 


'CHCX 


22 


High time 


12 




20 




ns 


•CLCX 


22 


Low time 


12 




20 




ns 


tCLCH 


22 


Rise time 




20 




20 


ns 


tCHCL 


22 


Fall time 




20 




20 


ns 


Shift Register 


<XLXL 


21 




1 




12t CLCL 




us 


tQVXH 


21 


Output data setup to clock rising edge 


492 




10tcLCL-133 




ns 


'XHQX 


21 


Output data hold after clock rising edge 


8 




2tc ucu -117 




ns 


'XHDX 


21 


Input data hold after clock rising edge 












ns 


'XHDV 


21 


Clock rising edge to input data valid 




492 




10tcLCL-133 


ns 



NOTES: 

1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 8XC51 FC to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 



drivers. 

4. See application note AN457. 



1996 Aug 12 



3-108 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 



87C51 FC 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 

't' (= time). The other characters, depending on their positions, 

indicate the name of a signal or the logical status of that signal. The 

designations are: 

A - Address 

C - Clock 

D - Input data 

H - Logic level high 

I - Instruction (program memory contents) 
L - Logic level low, or ALE 



P - PSER 
Q - Output data 
R - RTJ signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: Iavll = Time for address valid to ALE low. 
ti_LPL =Time for ALE low to PSER low. 



f LHLL 
•avll 



PORT 2 



y v 



tLLPL 



'PLPH 



Illiv — 1 

tpLIV. 



*LLAX 



/ 



tpLAZ 



<AVIV 



tpxix " 



- tpxiz- 



X 



X 



Figure 18. External Program Memory Read Cycle 



PSER 



tAVLL 



r 



*LLDV 



*LLAX 



\ / A0-A7 \ 

? \ FROM Rl OR DPL / ' 



« tRLA2 > 



*AVWL 



*RLRH 



tRLDV 



*AVDV 



y 



*RHDX " 



<: 



'WHLH -*• 



N / 



N / 



*RHDZ. 



A0-A7 FROM PCL 



X. 



P2.0-P2.7 OR A8-A15 FROM DPF 



AO-A15 FROM PCH 



Figure 19. External Data Memory Read Cycle 



1996 Aug 12 



3-109 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 



87C51FC 



*AVLL 



X 



y 







tLLWL 



tLLAX 



\ ' 7^ >> 

) \ FROM Rl OR DPL X, 



\ 



twLWH 



tQVWX 



X / 

X / 



UvWL 



Iqvwh 



tWHQX 



XX 



ACV-A7 FROM PCL 



^ INSTR IN 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 20. External Data Memory Write Cycle 



STRUCTION 
ALE 



| | , | , | 3 | 4 | , | 6 | 7 | S | 

(*" txLXL ~H 

"i_r~L_r 



OUTPUT DATA . 



~ f 

WRITE TO SBUF 



L_T~1_ 

"•"I I* - 'XHQX 
tQVXH Y *\ | 



INPUT DATA 
CLEAR Rl 



, L J n r txHDX 



X 



t 

SETTI 



>@0€>0^0€>0<BO€>0€>0<^< 



t 

SET Rl 



Figure 21. Shift Register Mode Timing 



1996 Aug 12 



3-110 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 



87C51FC 








Figure 22. External Clock Drive 



X0.2VCC+0.9 ^v/ 
02VCC-<" /\_ 



NOTE: 
ACinpi 

■ 



3 driven at V cc -0.5 for a logic '1 ' and 0.45V lor a logic '0'. 
'-- J eatV| H min!oralogicTandV| L maxforalc ' 



Figure 23. AC Testing Input/Output 



vload+o- 



v LOAD - 



vload-o- 



TIMING 
REFERENCE 
POINTS 



>: 



Vqm-0.1V 



NOTE: 

For timing purposes, a port is no longer tloating when a lOOmV change from load voltage occurs, 
and begins to float when a 100mV change from the loaded V h/Vol level occurs. lotV'oL £ ±20mA. 



Figure 24. Float Waveform 



1996 Aug 12 



3-111 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



Vcc 



vcc 



(NQ- 



CLOCK SIGNAL H XTAL1 

Vss 



I* 



Vcc 



ice 



(NO- 



CLOCK SIGNAL - 



I 





Vcc 


RST 






PO 




EA" 


XTAL2 




XTAL1 




Vss 





Figure 25. I cc Test Condition, 
All other pins are disconn 



Figure 26. I cc Test Condition, Idle Mode 
All other pins are disconnected 



0.45V -r 



0.2V CC -0.1 
*CHCL 



-tcLCX-" 
tCLCL 



*CHCX-> 
"tCLCH 



Figure 27. Clock Signal Waveform for l cc Tests in Active and Idle 
•clch = tcHCL = 5ns 



(NC>- 





Vcc 


RST 






PO 




EA" 


XTAL2 




XTAL1 




VSS 





Vcc 



Vcc 



Figure 28. I cc Test Condition, Power Down Mode 
All other pins are disconnected. V cc = 2V to 5.5V 



1996 Aug 12 



3-112 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



EPROM CHARACTERISTICS 

The 87C51FC is programmed by using a modified Improved 
Quick-Pulse Programming™ algorithm. It differs from older methods 
in the value used for Vpp (programming supply voltage) and in the 
width and number of the ALE/PROG pulses. 

The 87C51 FC contains two signature bytes that can be read and 
used by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87C51 FC manufactured by 
Philips. 

Table 4 shows the logic levels for reading the signature byte, and for 
programming the program memory, the encryption table, and the 
security bits. The circuit configuration and waveforms for quick-pulse 
programming are shown in Figures 29 and 30. Figure 31 shows the 
circuit configuration for normal program memory verification. 

Quick-Pulse Programming 

The setup for microcontroller quick-pulse programming is shown in 
Figure 29. Note that the 87C51 FC is running with a 4 to 6MHz 
oscillator. The reason the oscillator needs to be running is that the 
device is executing internal address and program data transfers. 

The address of the EPROM location to be programmed is applied to 
ports 1 and 2, as shown in Figure 29. The code byte to be 
programmed into that location is applied to port 0. RST, PSEN and 
pins of ports 2 and 3 specified in Table 4 are held at the 'Program 
Code Data' levels indicated in Table 4. The ALE/PROG is pulsed 
low 5 times as shown in Figure 30. 

To program the encryption table, repeat the 25 pulse programming 
sequence for addresses through 1 FH, using the 'Pgm Encryption 
Table' levels. Do not forget that after the encryption table is 
programmed, verification cycles will produce only encrypted data. 

To program the security bits, repeat the 25 pulse programming 
sequence using the 'Pgm Security Bit' levels. After one security bit is 
programmed, further programming of the code memory and 
encryption table is disabled. However, the other security bit can still 
be programmed. 

Note that the EATVpp pin must not be allowed to go above the 
maximum specified Vpp level for any amount of time. Even a narrow 
glitch above that voltage can cause permanent damage to the 
device. The V PP source should be well regulated and free of glitches 
and overshoot. 

Program Verification 

If security bits 2 and 3 have not been programmed, the on-chip 
program memory can be read out for program verification. The 
address of the program memory locations to be read is applied to 
ports 1 and 2 as shown in Figure 31 . The other pins are held at the 
'Verify Code Data' levels indicated in Table 4. The contents of the 
address location will be emitted on port 0. External pull-ups are 
required on port for this operation. 



If the 64 byte encryption table has been programmed, the data 
presented at port will be the exclusive NOR of the program byte 
with one of the encryption bytes. The user will have to know the 
encryption table contents in order to correctly decode the verification 
data. The encryption table itself cannot be read out. 

Reading the Signature Bytes 

The signature bytes are read by the same procedure as a normal 
verification of locations 030H and 031 H, except that P3.6 and P3.7 
need to be pulled to a logic low. The values are: 
(030H) = 1 5H indicates manufactured by Philips 
(031 H) = B3H indicates 87C51 FC 
(060H)= FCH 

Program/Verify Algorithms 

Any algorithm in agreement with the conditions listed in Table 4, and 
which satisfies the timing specifications, is suitable. 

Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is exposed to 
light with wavelengths shorter than approximately 4,000 angstroms. 
Since sunlight and fluorescent lighting have wavelengths in this 
range, exposure to these light sources over an extended time (about 
1 week in sunlight, or 3 years in room level fluorescent lighting) 
could cause inadvertent erasure. For this and secondary effects, 
it is recommended that an opaque label be placed over the 
window. For elevated temperature or environments where solvents 
are being used, apply Kapton tape Fluorglas part number 2345-5, or 
equivalent. 

The recommended erasure procedure is exposure to ultraviolet light 
(at 2537 angstroms) to an integrated dose of at least 1 5W-s/cm 2 . 
Exposing the EPROM to an ultraviolet lamp of 1 2,0O0uW/cm 2 rating 
for 20 to 39 minutes, at a distance of about 1 inch, should be 
sufficient. 

Erasure leaves the array in an all 1 s state. 

Security Bits 

With none of the security bits programmed the code in the program 
memory can be verified. If the encryption table is programmed, the 
code will be encrypted when verified. When only security bit 1 (see 
Table 5) is programmed, MOVC instructions executed from external 
program memory are disabled from fetching code bytes from the 
internal memory, EA is latched on Reset and all further programming 
of the EPROM is disabled. When security bits 1 and 2 are 
programmed, in addition to the above, verify mode is disabled. 
When all three security bits are programmed, all of the conditions 
above apply and all external program memory execution is disabled. 

Encryption Array 

64 bytes of encryption array are initially unprogrammed (all 1s). 



™Trademark phrase of Intel Corporation. 
1996 Aug 12 



3-113 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 



Table 4. EPROM Programming Modes 



MODE 


RST 


P5ETJ 


ALE/PROG 


EAWpp 


P2.7 


P2.6 


P3.7 


P3.6 


P3.3 


Read signature 


1 





1 


! 

















Program code data 







o- 


V PP 


1 





1 


1 


1 


Verify code data 







1 


1 








1 


1 





Pgm encryption table 


1 





0* 


V PP 


1 





1 





1 


Pgm security bit 1 


i 





0* 


V PP 


1 


1 


1 


1 


1 


Pgm security bit 2 


1 





0* 


Vpp 


1 


1 








1 


Pgm security bit 3 


1 

1 1 





0' 

' 


Vpp 






1 





1 


1 



1 . '0' = Valid low for that pin, '1 ' = valid high for that pin. 

2. Vpp = 12.75V ±0.25V. 

3. Vcc = 5V±1 0% during programming and verification. 

• ALE/PROG receives 5 programming pulses (only for user array; 25 pulses for encryption or security bits) while V PP is held at 12.75V. Each 
programming pulse is low for 100ns (±10jis) and high for a minimum of 10|is. 



Table 5. Program Security Bits 



PROGRAM LOCK BITS 1 ' 2 


PROTECTION DESCRIPTION 




SB1 


SB2 


SB3 


1 


U 


U 


U 


No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if 
programmed.) 


2 


P 


u 


U 


MOVC instructions executed from external program memory are disabled from fetching code bytes 
from internal memory, ES is sampled and latched on Reset, and further programming of the EPROM 
is disabled. 


3 


P 


P 


u 


Same as 2, also verify is disabled. 


4 


P 


P 


p 


Same as 3, external execution is disabled. Internal data RAM is not accessible. 



NOTES: 

1 . P - programmed. U - unprogrammed. 

2. Any other combination of the security bits is not defined. 



1996 Aug 12 



3-114 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontroller 87C51 FC 







-v 




RST 
P3.6 
P3.7 



XTAL1 

vss 



vcc 

PO 

EAWpp 
ALE/PROG" 
87C51FC P5EN 
P2.7 
P2.6 
P2.0-P2.5 
P3.4 



A- 
V 



PGM DATA 
+12.75V 

5 100ns PULSES TO GROUND 



1 



A8-A13 
A14 







Figure 29. Programming Configuration 







,r 

^UTJ-LTLTL ~~ LTLTLTLTLr 



10)is MIN 



n 



_TL 



Figure 30. PROG Waveform 



pi 

RST 
P3.6 
P3.7 
P3.3 



VCC 
PO 

EAWpp 
ALE/PRTJG" 
B7C51FC FSEW 
P2.7 
P2.6 
P2.0-P2.5 
P3.4 



V 



Si 



PGM DATA 

1 
1 


ENABLE 



A8-A13 
A14 



SU000S0 



Figure 31, Program Verification 



1996 Aug 12 



3-115 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit 



EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS 

Tamb = 21 ° c t0 +27°C, V cc = 5V±10%, V ss = OV (See Figure 32) 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


Vpp 


Pronramminn *5iinnl\/ vnltanp 
r luyi ai i m [ mi ly supply vuuauc 


12 5 


13.0 


V 


1 

Ipp 


Programming supply current 




ou 


mA 


1Ac(_CL 


0*?rill?itor frpni ipnrv 

woi^iiio.iwi iici^ueiiijy 


4 


g 


MHz 


*AVGL 




4tJI CLCL 






*GHAX 


MQoress noiu aner rrftju 


AO* 






•ovgl 


Data setup to PROG low 


48t CLCL 






tQHDX 


Data hold after PROG 


48tcLCL 






tEHSH 


P2.7 (ENABLE) high to V PP 


48ICLCL 






*SHGL 


Vpp setup to PROG low 


10 




US 


tGHSL 


Vpp hold after PROG 


10 




us 


*GLGH 


PROG width 


90 


110 


jis 


Wqv 


Address to data valid 




48tcLCL 




*ELQZ 


ENABLE low to data valid 




48tc LCL 




tEHQZ 


Data float after ENABLE 





48tcLCL 




'ghgl 


high to PROG low 


10 




US 



NOTE: 

1 Not tested. 



P1.0-P1.7 
P2.0-P2.5 
P3.4 
(A0-A14) 



PORT 
P0.0-P0.7 
(D0-D7) 



EAWpp 



P3.3 
P2.7 



< 



<DVGL 
*AVGL 



PROGRAMMING* 



:> — <; 



< 



*GLGH 
'SHGL 



* *EHSH * 



> 



VERIFICATION* 



> 



*GHDX 
tGHAX 



*GHGL 



*GHSL 



'elqv 



•avqv 



> 



tEHQZ 



NOTES: 

* FOR PROGRAMMING VERIFICATION SEE FIGURE 29. 

FOR VERIFICATION CONDITIONS SEE FIGURE 31. 
" SEE TABLE 4. 

Figure 32. EPROM Programming and Verification 



1996 Aug 12 



3-116 



Philips Semiconductors 



Product specification 



lip 8-bit microcontrollers 80CL31/80CL51 



FEATURES 

• Full static 80C51 CPU 

• 8-bit CPU, ROM, RAM, 1/0 in a single 40-lead DIL / mini-pack 

• 4K x 8 ROM, expandable externally to 64K bytes 

• 128 bytes RAM, expandable externally to 64K bytes 

• Four 8-bit ports, 321/0 lines 

• Two 1 6-bit timer / event counters 



• External memory expandable up to 128K, external ROM up to 
64Kand/or RAMupto64K 

• On-chip oscillator suitable for RC, LC, quartz crystal or ceramic 
resonator 

• Thirteen source, thirteen vector interrupt structure with two priority 
levels 

• Full duplex serial port (UART) 

• Enhanced architecture with: 

- non-page oriented instructions 

- direct addressing 

- four eight byte RAM register banks 

- stack depth up to 128 bytes 

- multiply, divide, subtract and compare instructions 

• Power-Down and IDLE instructions 



• Wake-up via external interrupts at Port 1 

• Single supply voltage of 1 .8V to 6.0V (5.0V +1 0% for P80C51 ) 

• Frequency range of to 16MHz (3.5MHz to 16MHz for 

• Very low current consumption 

• Operating temperature range: -40 to +85°C 

DESCRIPTION 

The 80CL51 is manufactured in an advanced CMOS technology. 
The instruction set of the 80CL51 is based on that of the 8051 . The 
80CL51 is a general purpose microcontroller especially suited for 
battery-powered applications. The device has low power 
consumption and a wide range of supply voltage. For emulation 
purposes, the 85CL000 (Piggy-back version) with 256 bytes of RAM 
is recommended. The 80CL51 has two software selectable modes 
of reduced activity for further power reduction: Idle and Power-down. 
The 80CL51 also functions as an arithmetic processor having 
facilities for both binary and BCD arithmetic plus bit-handling 
capabilities. The instruction set consists of over 100 instructions: 49 
one-byte, 46 two-byte, and 16 three-byte. 

The P80CL31 is the ROMIess version of the P80CL51 . P80C51 is a 
5V version of the low voltage P80CL51 . 

The P80CL31 is the ROMIess version of the P80CL51 . P80C51 is a 
5V version of the low voltage P80CL51 . 



PIN CONFIGURATIONS 



INTS/P1.0 
IHT5/P1.1 
IWT4/P1.2 
TTCT57P1.3 
INT6/P1.4 
1NT7/P1.5 
IRTS7P1.6 
INT97P1.7 
RST 

P.XO/OATA/P3.0 
TXD/CLOCK/P3. 1 
IHT5/P3.2 
lfJTT7P3.3 
TOP3.4 
T1/P3.5 
WR7P3.6 
RD7P3.7 
XTAL2 
XTAL1 

vss 



PLASTIC 
DUAL 
IN-UNE 

AND 
SMALL 
OUTLINE 
PACKAGES 



§v DD 

3§ P0.O/AD0 
51] P0.1/AD1 
37] P0.2/AD2 
3j| P0.3/AD3 
35j P0.4/AD4 
34] P0.5/AD5 
5| P0.6/AD6 
32| P0.7/AD7 
3_l] ES 
30j ALE 
29] P5T-R 
2sJ P2.7/A15 
2j P2.6/A14 
ilj P2.5/A13 
25] P2.4/A12 
24] P2.3/A11 
23] P2.2/A10 
22] P2.1/A9 
2l] P2.0/A8 



OOOO 



5 5 8 s o 

till' 



S 3 > Si » 
0000 




P2.7/A15 
P2.6/A14 
P2.5/A13 



January 1 995 



3-117 



Philips Semiconductors 





Product specification 
— 



80CL31/80CL51 



ORDERING INFORMATION 



PHILIPS PART ORDER 
NUMBER PART MARKING 


PHILIPS NORTH AMERICA 1 
PART ORDER NUMBER 


TEMPERATURE RANGE °C 
AND PACKAGE 


DRAWING 
NUMBER 


ROMIess 


ROM 


ROMIess 


ROM 


P80CL31 HFP 


P80CL51HFP 


P80CL31 HFP N 


P80CL51HFP N 


-40 to +85; 

40-lead Plastic Dual In-line Package (1 .8V to 6V) 


SOT129-1 


P80CL31HFT 


P80CL51HFT 


P80CL31 HFT D 


P80CL51HFTD 


-40 to +85; 

40-lead Plastic Small Outline Package (1 .8V to 6V) 


SOT158-1 


P80CL31HFH 


P80CL51HFH 


P80CL31HFH B 


P80CL51HFH B 


-40 to +85; 

44-lead Plastic Quad Flat Package (1.8V to 6V) 


SOT307-2 




P80C51HFP 




P80C51HFPN 


-40 to +85; 

40-lead Plastic Dual In-line Package (5.0V ±10%) 


SOT129-1 




P80C51HFT 




P80C51HFTD 


-40 to +85; 

40-lead Plastic Small Outline Package (5.0V ±10%) 


SOT158-1 




P80C51HFH 




P80C51HFHB 


-^0 to +85; 

44-lead Plastic Quad Flat Package (5.0V ±10%) 


SOT307-2 



NOTE: 

1 . Parts ordered by the Philips North America part number will be marked with the Philips part marking. 



January 1 995 



3-118 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



PIN DESCRIPTIONS 



PIN 


UboluNAI IUN 


FUNCTION 






QFP 


DIP 






AO 


■j 


P1.0/INT2 


Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written 


41 


2 


P1.1/1NT3 


to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 1 


42 


3 


P1.2/INT4 


m ,tm it Ki ,tf*sr nan e!nlr/am irnn A I Q 1 i | InaHe Ac inni ite Dnrt 1 nine that ara ovtornalh/ ni illaH 1 fl\A/ 
OUipUT DUlier can SinK/SOUrce 1 Lo 1 1 L- lUaUa. Ha llipulb, run 1 UIII& Ulal ale cxiyi 1 Idlly puilfcJU LWVV 


HO 


4 


P1.3/INT5 


will source current (l|[_ in the characteristics) due to the internal pullups. Port 1 aiso serves the 




alternative functions INT2 to INT9. 


44 
1 


5 
6 


P1.4/INT6 
P1.5/INT7 


2 


7 


P1.6/INT8 




3 


8 


P1 .7/1NT9 




4 


9 


RST 


Reset: A high level on this pin for two machine cycles while the oscillator is running resets the 
device. 


5-13 


10-17 




Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can 
sink/source 4 LS TTL inputs. Port 3 pins that have 1 s written to them are pulled HIGH by the 
internal pull ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally 
pulled LOW will source current (l| L in the characteristics) due to the internal pull ups. 


5 


10 


P3.0/RXD/data 


RXD/data: Serial port receiver data input (asynchronous)or data input/output (synchronous) 


7 


11 


P3.1/TXD/clock 


TXD/clock: Serial port transmitter data output (asynchronous) or clock output (synchronous) 


8 


12 


P3.2/1NT0 


INTO: External interrupt 0. 


9 


13 


P3.3/INT1 


INT1 : External interrupt 1 . 


10 


14 


P3.4/T0 


TO: Timer external input. 


11 


15 


P3.5/T1 


T1 : Timer 1 external input. 


12 


16 


P3.6/WR 


WR: External data memory write strobe. 


13 


17 


P3.7/RT3 


RTJ: External data memory read strobe. 


14 


18 


XTAL2 


Crystal output: Output of the inverting amplifier of the oscillator. Left open when external clock is 
used. 

Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally gen- 
erated clock source. 


15 


19 


XTAL1 


Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally 
generated clock source. 


16 


20 


Vss 


Ground: Circuit ground potential. 


18-25 


21-28 


P2.0-P2.7 


Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that have 1 s written 
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 2 
output buffer can sink/source 4 LS TTL loads. 

Port 2 emits the high-order address byte during accesses to external memory that use 1 6-bit ad- 

eiraecac /R^f^WV iff) nD I Ul\ In thio annlinatinn it icoc the ctrnnn internal niilhmc uihon omittinn to 

uresses ^iviuva wur i nj. in inis application n uses ine birony imeinai punup& wiien eniiuing i s>. 
During accesses to external memory that use 8-bit addresses (MOVX @ Ri) , Port 2 emits the con- 
tents of the P2 Special Function Register. 


26 


29 


PSEN 


Program store enable output: Read strobe to external program memory. When executing code 
out of external program memory, PSEN is activated twice each machine cycle. However, during 
each access to external data memory two PSEN activations are skipped. 


27 


30 


ALE 


Address Latch Enable: Output pulse for latching the low byte of the address during access to 
external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, and may be 
used for external timing or clocking purposes. 


29 


31 


ES 


External Access: When EA is held High the CPU executes out of internal program memory (un- 
less the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of 
external memory regardless of the value of the program counter. 


30-37 


32-39 


P0.0-P00.7 


Port 0: Port is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8 
LS TTL loads. Port pins that have 1s written to them float, and in that state will function as high 
impedance inputs. Port is also the multiplexed low order address and data bus during access to 
external memory. In this application it uses strong internal pull-ups when emitting logic 1s. 


38 


40 


Vdd 


Power supply. 



January 1995 



3-119 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



BLOCK DIAGRAM 



FREQUENNCY REFERENCE 
XTAL2 XTAL1 



OSCILLATOR 
AND TIMING 



PROGRAM 
MEMORY 
(4K BY 8 ROM) 



7T 



DATA MEMORY 
(128 BY 8 RAM) 



77 



TWO 16-BIT TIMER/ 
EVENT COUNTERS 



80CL51 



7T 



iz. 



64K BYTE BUS 
EXPANSION 
CONTROL 



INTERNAL 
INTERRUPTS 



±2 



PROGRAMMABLE 

I/O 



V 7 

, CONTROL 

EXTERNAL ENTERRUPTS 

1 . Pins shared with parallels ports pins. 



PROGRAMMABLE 
SERIAL PORT, 
FULL DUPLEX UART, 
SYNCHRONOUS 
SHIFT 



y y, V 

PARALLEL PORTS 



(1) 



1 



vdd 

VSS RST 



XTAL1 |~*~ 

□ 
XTAlJT^ 



ALTERNATIVE 
FUNCTIONS 

RxD/data-<— >■ 

TxD/clock-< 

IWT5 »> 

WTT ► 

TO ► 

T1 — »• 

WB< 

RTJ< 



ES ■ 
P5ETC • 
ALE < 



iii 



ADDRESS AND 
DATA BUS 



ADDRESS BUS 



January 1995 



3-120 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit i 



80CL31/80CL51 



1.0 FUNCTIONAL DESCRIPTION 
General 

The 80CL51 is a stand-alone high-performance CMOS 
microcontroller designed for use in real-time applications such as 
instrumentation, industrial control, intelligent computer peripherals 
and consumer products. 

The device provides hardware features, architectural enhancements 
and new instructions to function as a controller for applications 
requiring up to 64K bytes of program memory and/or up to 64K 
bytes of data storage. 

The 80CL51 contains a non-volatile 4K byte x 8 read-only program 
memory; a static 128 byte x 8 read/write data memory; 32 1/0 lines; 
two 1 6-bit timer/event counters; a thirteen- source two priority-level, 
nested interrupt structure and on-chip oscillator and timing circuit. 

The device has two software selectable modes of reduced activity 
for power reduction: IDLE and Power-down. The Idle mode freezes 
the CPU while allowing the RAM, timers, serial I/O and interrupt 
system to continue functioning. The Power-down mode saves the 
RAM contents but freezes the oscillator causing all other chip 
functions to be inoperative. 

The P80C51 is a 5V version of the low voltage microcontroller 
P80CL51 . Hereafter the generic term P80CL51 will be used for the 
functional description of both types. The special features of the 
P80C51 are handled in chapter 1.9. 

CPU timing 

A machine cycle consists of a sequence of 6 states. Each state time 
lasts for two oscillator periods, thus a machine cycle takes 12 
oscillator periods or ^\^s if the oscillator frequency is 12MHz. 

1.1 Memory organization 

The 80CL51 has a 4K Program Memory (ROM) plus 128 bytes of 
Data Memory (RAM) on board. The device has separate address 
spaces for Program and Data Memory (see Memory Map). Using 
Ports P0 and P2, the 80CL51 can address up to 64K bytes of 
external memory. The CPU generates both read and write signals 
(RD and WR) for external Data Memory accesses, and the read 
strobe (PSEN) for external Program Memory. 

MEMORY MAP 



1.1.1 Program Memory 

The 80CL51 contains 4K bytes of internal ROM. After reset the CPU 
begins execution at location OO0OH. The lower 4K bytes of Program 
Memory can be implemented in either on- chip ROM or external 
Memory. If the EA pin is strapped to V DD , then program memory 
fetches from addresses 000H through OFFFH are directed to the 
internal ROM. Fetches from addresses 1000H through FFFFH are 
directed to external ROM. Program counter values greater than 
OFFFH are automatically addressed to external memory regardless 
of the state of the EA pin. 

1 .1 .2 Data Memory 

The 80CL51 contains 128 bytes of internal RAM and 25 Special 
Function Registers (SFR). The Memory Map below shows the 
internal Data Memory space divided into the Lower 128, the Upper 
128, and the SFR space. 

The lower 128 bytes of the internal RAM are organized as mapped 
in Figure 1 . The lowest 32 bytes are grouped into 4 banks of 8 
registers. Program instructions refer to these registers R0 through 
R7. Two bits in the Program Status Word select which register bank 
is in use. The next 1 6 bytes above the register banks form a block of 
bit-addressable memory space. The 1 28 bits in this area can be 
directly addressed by the single-bit manipulation instructions. The 
remaining registers (30H to 7FH) are directly and indirectly byte 
addressable. 

1.1.3 Special Function Registers 

The upper 128 bytes are the address locations of the SFRs. Figure 
2 shows the Special Function Register (SFR) space. SFRs include 
the port latches, timers, peripheral control, serial I/O registers, etc. 
These registers can only be accessed by direct addressing. There 
are 128 addressable locations in the SFR address space (SFRs with 
addresses divisible by eight). 

1.1.4 Addressing 

The 80CL51 has five methods for addressing source operands: 

- Register 

- Direct 



Immediate 

Base-Register-plus Index-Register-indirect 



64K 








EXTERNAL 








dOQfi 





















INTERNAL 




INTERNAL 




(ES=1) 




(ES.O) 



OVERLAPPED 
SPACE 




PROGRAM MEMORY 



INTERNAL DATA MEMORY 



January 1995 



3-121 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



R7 
I 


1 FH 


I 

BO 


18H 


R7 
I 


17H 


I 

RO 


10H 


R7 


OFH 


1 

RO 


OSH 


R7 
1 


07H 


RO 










BIT-AODRESSABLESPACE 
(BIT ADDRESSES 0-7FI 



4 BANKS OF 8 REGISTERS 
(RO-R) 



Figure 1. The Lower 128 Bytes of Internal RAM 



The first three methods can be used for addressing destination 
operands. Most instructions have a "destination/source" filed that 
specifies data type, addressing methods and operands involved. For 
operations other than MOVs, the destination operand is also a 

source operand. 

Access to memory addressing is as follows: 

- Registers in one of the four register banks through register, 
direct or indirect. 

- Internal RAM (128 bytes) through direct or register-indirect. 

- Special Function Register through Direct. 

- External data memory through Register-Indirect 

- Program memory look-up tables through Base-Register-Plus 
Index-Register-Indirect. 

1.2 I/O Facilities 

1.2.1 Ports 

The 80CL51 has 32 I/O lines treated as 32 individually addressable 
bits or as four parallel 8- bit addressable ports. Port 0, 1 , 2 and 3 
perform the following alternate functions: 

Port 0: provides the multiplexed low-order address and data bus 
for expanding the device with standard memories and 
peripherals. 

Port 1 : provides the inputs for the external interrupts INT2/INT9. 

Port 2: provides the high-order address when expanding the 
device with external program or data memory. 

Port 3: pins can be configured individually to provide: 

(1) external interrupt request inputs 

(2) counter input 

(3) control signals to read and write to external 

(4) UART input and output 



To enable a Port 3 pin alternate function, the Port 3 bit latch in its 
SFR must contain a logic 1 . 

Each port consists of a latch (Special Function Registers P0 to P3), 
an output driver and an input buffer. Ports 1 ,2,3 have internal pull 
ups. Figure 3(a) shows that the strong transistor p1 is turned on for 
only 2 oscillator periods after a 0-to-1 transition in the port latch. 
When on, it turns on p3 (a weak pull up) through the inverter. This 
inverter and p3 form a latch which hold the 1. In Port the pull up p1 
is only on when emitting 1s for external memory access. Writing a 1 
to a Port bit latch leaves both output transistors switched off so the 
pin can be used as a high-impedance input. 

1.2.2 Port Options 

The pins of port 1 , port 2, and port 3 may be individually configured 
with one of the following options (see Figure 3): 

Option 1: Standard Port; quasi-bidirectional I/O with pull up. The 
strong booster pull up p1 is turned on for two oscillator 
periods after a 0-to-1 transition in the port latch (see 
Figure 3(a)). 

Option 2: Open drain; quasi-bidirectional I/O with n-channel open 
drain output. Use as an output requires the connection of 
an external pull up resistor (see Figure 3(c)). 

Option 3: Push-Pull; output with drive capability in both polarities. 

Under this option, pins can only be used as outputs. See 
Figure 3(b). 



January 1995 



3-122 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 



80CL31/80CL51 



REGISTER 
MNEMONIC 



BIT ADDRESS 



DIRECT 
BYTE ADDRESS 
(HEX) 



1X1 
IEN1 



SOBUF 
SOCON 



TH1 
THO 
TL1 



TLO 
TMOD 
TCON 
PCON 

DPH 



DPL 
SP 



FD FC FB FA 



EA 



E4 E3 E2 



D4 D3 D2 



C4 C3 C2 



BC 88 BA 



B6 B5 B4 B3 B2 



AE AD AC I AB AA 



A6 A5 A4 A3 A2 



9D 9C 9B 9A 



95 94 93 92 



BF | BE | 3D | SC | 8B | 8A | 69 | BS 







izr 



j±2 



F8H •< 



FOH •<- 



E9H 

E8H •< 



EOH -< 



DOH <- 



COH -< 



B8H 



BOH <- 



A8H 



AOH 



99H 

98H ^ 



90H ■< 



8DH 
8CH 
8BH 
BAH 
89H 

88H <- 

87H 



81H 
BOH 



SFRs CONTAINING DIRECTLY 
ADDRESSABLE BITS 



Figure 2. Special Function Registers 



January 1995 



3-123 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 







(a) 



STRONG PULL UP 
2 OSCILLATOR PERIODS 



FROM 
PORT 
LATCH 

-» 



READ PORT PIN 



INPUT BUFFER 



(b) 



PORT 
LATCH 

a — 



STRONG PULL UP 



FROM 
PORT 
LATCH 

a — < 



INPUT DATA 



READ PORT PIN 



EXT. 
PULL UP 



-°<\ <H 

INPUT BUFFER 



Figure 3. Ports 



The definition of port options for port is slightly different. Two 
cases have to be examined. First, accesses to external memory 
(EA=0 or access above the built -in memory boundary), second, I/O 
accesses. 

External Memory Accesses 

Option 1 : True and 1 are written as address to the external 
memory (strong pull up is used). 

Option 2: An external pull up resistor is needed for external 
accesses. 

Option 3: Not allowed for external memory access as the port can 
only be used as output. 

I/O Accesses 

Option 1: When writing a 1 to the port-latch, the strong pull up p1 
will be on for 2 oscillator periods. No weak pull up exists. 
Without an external pull up, this option can be used as a 
high-impedance input. 



Option 2: Open drain; quasi-bidirectional I/O with n-channel open 
drain output. Use as an output requires the connection of 
an external pull up resistor (see Figure 3(c)). 

Option 3: Push-Pull; output with drive capability in both polarities. 
Under this option, pins can only be used as outputs. 

Individual mask selection of the post-reset state is available on any 
of the above pins. Make your selection by appending "S" or "R" to 
option 1 , 2, or 3 above (e.g. 1 S for a standard I/O to be set after 
RESET or 2R for an open-drain I/O to be reset after RESET). 

1 .3 Timer/event counter 

The 80CL51 contains two 1 6-bit Timer/Counter registers, Timer 
and Timer 1 , which can perform the following functions: 

- Measure time intervals and pulse durations 

- Count events 

- Generate interrupts requests 



January 1995 



3-124 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



Timer and Timer 1 can be independently programmed to operate 

as follows: 

Mode - 8-bit timer or counter with divide-by-32 prescaler 

Model - 16-bit time-interval or event counter 

Mode 2 - 8-bit time interval or event counter with automatic reload 
upon overtlow 

Mode 3 - Timer establishes TLO and THO as two separate 
counters. 

In the "Timer" function, the register is incremented every machine 
cycle. Since a machine cycle consists of 12 oscillator periods, the 
count rate is 1 /1 2 of the oscillator frequency. 

In the "Counter" function, the register is incremented in response to 
a 1-to-0 transition. Since it takes 2 machine cycles (24 oscillator 
periods) to recognize a 1 -to-0 transition, the maximum count rate is 
1/24 of the oscillator frequency. To ensure a given level is sampled, 
it should be held for at least one full machine cycle. 



PCON 


BIT 


POSITION 


FUNCTION 


SMOD 


PCON.7 

PCON.4-PCON.6 


Double baud-rate bit, see description of the UART, chapter 1 .5. 
(reserved) 


GF1 


PCON.3 


General purpose flag bit 


GFO 


PCON.2 


General purpose flag bit 


PD 


PCON.1 


Power-down activation bit 


IDL 


PCON.O 


Idle mode activation bit 



1 .4 Idle and Power-down operation 

Idle mode operation permits the interrupt, serial port and timer 
blocks to continue functioning while the clock to the CPU is halted. 
The following functions remain active during Idle mode: 

- Timer 0, Timer 1 

- UART 

- External interrupt 

The Power-down operation freezes the oscillator. The Power-down 
mode can only be activated by setting the PD bit in the PCON 
register. 

1.4.1 Power control register 

Power-down and Idle modes are activated by software via the 
Special Function Register PCON. Its hardware address is 87H. 
PCON is byte addressable only. 



OSCILLATOR 



CLOCK 
GENERATOR 



INPUTS 
SERIAL PORTS 
TIMER BLOCKS 






Figure 4. Idle and Power-down Hardware 



January 1 995 



3-125 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit mi 



80CL31/80CL51 



1 .4.2 Power-down mode 

The instruction setting PCON.1 is the last executed prior to going 
into the Power-down mode. In Power-down mode the oscillator is 
stopped. The contents of the on-chip RAM and SFRs are preserved. 
The port pins output the values held by their respective SFRs. ALE 
and PSEN are held LOW. 

In the Power-down mode V DD may be reduced to minimize power 
consumption. However, the supply voltage must not be reduced until 
Power-down mode is active, and must be restored before the 
hardware reset is applied and frees the oscillator. Reset must be 
held active until the oscillator has restarted and stabilized. 



The wake-up operation after power-down in this controller has two 
basic approaches: 

1 .4.2.1 Wake-up using INT2 to INT9 

If INT2 to INT9 are enabled, the 80CL51 can be awakened from 
power-down mode with the external interrupts. To ensure that the 
oscillator is stable before the controller restarts, the internal clock 
will remain inactive for 1 536 oscillator periods. This is controlled by 
an on-chip delay counter. 

1.4.2.2 Wake-up using RESET 

To wake-up the 80CL51 the RESET pin has to be kept HIGH for a 
minimum of 24 oscillator periods. The on-chip delay counter is 
inactive. The user has to ensure that the oscillator is stable before 
any operation is attempted. Figure 5 illustrates the two possibilities 
for wake-up. 

1.4.3 Idle mode 

The instruction that sets PCON.O is the last instruction executed 
before going into Idle mode. Once in the Idle mode, the internal 



clock is gated away from the CPU, but not from the Interrupt, Timer 
and Serial port functions. The CPU status is preserved along with 
the Stack Pointer, Program Counter, Program Status Word and 
Accumulator. The RAM and all other registers maintain their data 
during Idle mode. The port pins retain the logical states they held at 
Idle mode activation. ALE and PSEN hold at the logic HIGH level. 

There are two methods used to terminate the Idle mode. Activation 
of any enabled interrupt will cause PCON to be cleared by 
hardware, terminating Idle mode. The interrupt is serviced, and 
following the instruction RETI, the next instruction to be executed 
will be the one following the instruction that put the device in the Idle 
mode. 

Flag bits GFO and GF1 may be used to determine whether the 
interrupt was received during normal execution or Idle mode. For 
example, the instruction that writes to PCON.O can also set or clear 
one or both flag bits. When Idle mode is terminated by an interrupt, 
the service routine can examine the status of the flag bits. 

The second method of terminating the Idle mode is with an external 
hardware reset. Since the oscillator is still running, the hardware 
reset is required to be active for only two machine cycles to 
complete the reset operation. 

Reset redefines all SFRs, but does not affect the on-chip RAM. 

The status of the external pins during Idle and Power-down mode is 
shown in Table 1 . If the Power-down mode is activated while 
accessing external memory, port data held in the Special Function 
Register P2 is restored to Port 2. If the data is a logic 1 , the port pin 
is held HIGH during the Power-down mode by the strong pull up 
transistor p1 (see Figure 3(a)). 



Table 1 . Status of the External Pins During Idle and Power-down Mode 



MODE 


MEMORY 


ALE 


PSEN 


PORT 


PORT 1 


PORT 2 


PORT 3 


Idle 


internal 


1 


1 


Port Data 


Port Data 


Port Data 


Port Data 


Idle 


external 


1 


1 


Floating 


Port Data 


Address 


Port Data 


Power-down 


internal 








Port Data 


Port Data 


Port Data 


Port Data 


Power-down 


external 








Floating 


Port Data 


Port Data 


Port Data 



POWER-DOWN 



c 



J L 



RESET-PIN T 



DELAY COUNTER 
1 536 PERIODS 



Figure 5. Wake-up Operation 



January 1995 



3-126 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



1.5 Standard serial interface SIO: UART 

This serial port is full duplex, meaning it can transmit and receive 
simultaneously. It is also receive-buffered, meaning it can 
commence reception of a second byte before a previously received 
byte has been read from the register. (However, if the first byte still 
hasn't been read by the time reception of the second byte is 
complete, one of the bytes will be lost). The serial port receive and 
transmit registers are both accessed at Special Function Register 
SOBUF. Writing to SOBUF loads the transmit register, and reading 
SOBUF loads the transmit register, and reading SOBUF accesses a 
physically separate receive register. 

The serial port can operate in 4 modes: 

Mode 0: Serial data enters and exits through RxD. TxD outputs the 
shift clock. 8 bits are transmitted/ received (LSB first). The 
baud is fixed at 1/12 the oscillator frequency. 

Mode 1 : 10 bits are transmitted (through TxD) or received (through 
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit 
(1). On receive, the stop bit goes into RB8 in Special 
Function Register SCON. The baud rate is variable. 

Mode 2: 11 bits are transmitted (through TxD) or received (through 
RxD): start bit (0), 8 data bits (LSB first), a programmable 
9th data bit, and a stop bit (1). On Transmit, the 9th data 
bit (TB8 in SCON) can be assigned the value of or 1 . 
Or, for example, the parity bit (P, in the PSW) could be 
moved into TBS. On receive, the 9th data bit goes into 
RB8 in Special Function Register SCON, while the stop 
bit is ignored. The baud rate is programmable to either 
1/32 or 1/64 the oscillator frequency. 

Mode 3: 11 bits are transmitted (through TxD) or received (through 
RxD): a start bit (0), 8 data bits (LSB first), a 
programmable 9th data bit and a stop bit (1). In fact, 
Mode 3 is the same as Mode 2 in all respects except 
baud rate. The baud rate in Mode 3 is variable. 

In all four modes, transmission is initiated by any instruction that 
uses SOBUF as a destination register. Reception is initiated in Mode 
by the condition Rl = and REN = 1 . Reception is initiated in the 
other modes by the incoming start bit if REN = 1 . 

1.5.1 Multiprocessor communications 

Modes 2 and 3 have a special provision for multiprocessor 
communications. In these modes, 9 data bits are received. The 9th 
one goes into RB8. Then comes a stop bit. The port can be 
programmed such that when the stop bit is received, the serial port 
interrupt will be activated only if RB8 = 1 . This feature is enabled by 
setting bit SM2 in SCON. A way to use this feature in multiprocessor 
systems is as follows: 

When the master processor wants to transmit a block of data to one 
of several slaves, it first sends out an address byte which identifies 
the target slave. An address byte differs from a data byte in that the 
9th bit is 1 in an address byte and in a data byte. With SM2 = 1 , no 
slave will be interrupted by a data byte. An address byte, however, 
will interrupt all slaves, so that each slave can examine the received 
byte and see if it is being addressed. The addressed slave will clear 
its SM2 bit and prepare to receive the data bytes that will be coming. 
The slaves that weren't being addressed leave their SM2s set and 
go on about their business, ignoring the coming data bytes. 

SM2 has no effect in Mode 0, and in Mode 1 can be used to check 
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1 , the 
receive interrupt will not be activated unless a valid stop bit is 
received. 



1.5.2 Serial port control register 

The serial port control and status register is the Special Function 
Register S0CON, shown in Figure 6. The register contains not only 
the mode selection bits, but also the 9th data bit for transmit and 
receive (TB8 and RB8), and the serial port interrupt bits (T1 and 
R1). See next page. 

Baud Rates 

The baud rate in Mode is fixed: Mode Baud Rate = Oscillator 
Frequency /1 2. The baud rate in Mode 2 depends on the value of bit 
SMOD in Special Function Register PCON. If SMOD = (which is 
the value on reset), the baud rate is 1/64 the oscillator frequency. If 
SMOD = 1 , the baud rate is 1/32 the oscillator frequency. 

Mode 2 Baud Rate = (2 SMOD /64)(Oscillator Frequency) 

The baud rates in Modes 1 and 3 are determined by the Timer 1 
overflow rate. 

Using Timer 1 to generate baud rates 

When Timer 1 is used as the baud rate generator, the baud rates in 
Modes 1 and 3 are determined by the Timer 1 overflow rate and the 
value of SMOD as follows: 
(2 SMOD /32)(Timer 1 Overflow Rate) 

The Timer 1 interrupt should be disabled in this application. The 
Timer itself can be configured for either "timer" or "counter" 
operation, and in any of its 3 running modes. In the most typical 
applications, it is configured for "timer operation, in the auto-reload 
mode (high nibble of TMOD = 001 0B). In that case the baud rate is 
given by the formula: 

Mode 1 , 3 Baud Rate = 

((2 SMOD /32) (Oscillator Frequency)) / (12 (256 - (TH 1 )) 

One can achieve very low baud rates with Timer 1 by leaving the 
Timer 1 interrupt enabled, and configuring this Timer to run as a 
1 6-bit timer (high nibble of TMOD = 0001 B), and using the Timer 1 
interrupt to do a 1 6-bit software reload. Table 2 lists various 
commonly used baud rates and how they can be obtained from 
Timer 1. 

More about Mode 

Figure 7 shows a simplified functional diagram of the serial port in 
Mode 0, and associated timing. Transmission is initiated by any 
instruction that uses SOBUF as a destination register. The "write to 
S0BUP signal at S6P2 also loads a 1 into the 9th position of the 
transmit shift register and tells the TX Control block to commence a 
transmission. The internal timing is such that the one full machine 
cycle will elapse between "write to S0BUP, and activation of SEND. 

SEND enables the output of the shift register to the alternate output 
function line of P3.0 and also enables SHIFT CLOCK to the 
alternate output function line of P3.1 . SHIFT CLOCK is low during 
S3, S4, and S5 of every machine cycle, and high during S6, S1 and 
S2. At S6P2 of every machine cycle in which SEND is active, the 
contents of the transmit shift are shifted to the right one position. 

As data bits shift out to the right, zeros come in from the left. When 
the MSB of the data byte is at the output position of the shift register, 
then the 1 that was initially loaded into the 9th position is just to the 
left of the MSB, and all positions to the left of that contain zeros. 
This condition flags the TX Control block to do one last shift and 
then deactivate SEND and set T1 . Both of these actions occur at 
S1 Pi of the 1 0th machine cycle after "write to S0BUP. 

Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 
of the next machine cycle, the RX Control unit writes the bits 
11111110 to the receive shift register, and in the next clock phase 
activates RECEIVE. 



January 1 995 



3-127 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



SM2 

REN 
TB8 
RB8 

Tl 

Rl 



S M 


SM1 


SM2 


REN 


TB8 


HB6 


T1 


R1 



Where SMO, SM1 specify the serial port mode, as follows: 
SMO SM1 Mode Description Baud Rate 



shift register 

8- bit UART 

9- bit UART 



fosc/12 
variable 
fosc/64 
or 

fosc/32 



1 3 9-bit variable UART 



1 



Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1 then Rl will not 
be activated if the received 9th data bit (RB8) is 0. In Mode 1 , if SM2=1 then R1 will not be activated if a valid stopbit 
was not received. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1 , it SM2=0, RB8 is the stop bit that was received. In 
Mode 0, RB8 is not used. 

Is transmit interrupt flag. Set by hardware at the end of the 8th time in Mode 0, or at the beginning of the stop bit in the 
other modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in 
the other modes, in any serial reception except (see SM2). Must be cleared by software. 



Figure 6. Serial Port control (SCON) Register 







Table 2. Timer 1 Generated Commonly Used Baud Rates 



TIMER 1 


BAUD RATE 


fosc 


SMOD 


C/T 


MODE 


RELOAD VALUE 


Mode Max: 1.33 Mb/s 


16 MHz 


X 


X 


X 


X 


Mode 2 Max: 500 Kb/s 


16 MHz 


1 


X 


X 




X 


Modes 1,3: 83.3 Kb/s 


16 MHz 


1 





2 


FFH 


19.2 Kb/s 


11.059 MHz 


1 





2 


FDH 


9.6 Kb/s 


11.059 MHz 








2 


FDH 


4.8 Kb/s 


11.059 MHz 








2 


FAH ' 


2.4 Kb/s 


11.059 MHz 








2 


F4H 


1.2 Kb/s 


11.059 MHz 








2 


E8H 


137.5 Kb/s 


11.986 MHz 








2 


1DH 


110 


6 MHz 








2 


72H 


110 


12 MHz 








1 


FEEBH 



January 1995 



3-128 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



RECEIVE enables SHIFT CLOCK to the alternate output function 
line of P3.1. SHIFT Clock makes transitions at S3P1 and S6P1 of 
every machine cycle, at S6P2 of every machine cycle in which 
RECEIVE is active, the contents of the receive shift register are 
shifted to the left one position. The value that comes in from the right 
is the value that was sampled at the P3.0 pin at S5P2 of the same 
machine cycle. 

As data bits come in from the right, 1 s shift out to the left. When the 
that was initially loaded into the right-most position arrives at the 
left-most position in the shift register, it flags the RX Control block to 
do one last shift and load SOBUF. At S1 P1 of the 1 0th machine cycle 
after the write to SCON that cleared Rl, RECEIVE is cleared as Rl is 
set. 

More about Mode 1 

Ten bits are transmitted (through TxD), or received (through RxD): a 
start bit (0), 8 data bits (LSB first), and a stop bit (1 ). On receive, 
the stop bit goes into RB8 in SCON. In the 8051 the baud rate is 
determined by the Timer 1 overflow rate. 

Figure 8 shows a simplified functional diagram of the serial port in 
Mode 1 , and associated timings for transmit/receive. 

Transmission is initiated by any instruction that uses SOBUF as a 
destination register. The "write to SOBUF' signal also loads a 1 into 
the 9th bit position of the transmit shift register and flags the TX 
Control unit that a transmission is requested. Transmission actually 
commences at S1 P1 of the machine cycle following the next rollover 
in the divide-by-1 6 counter. (Thus, the bit times are synchronized to 
the divide-by-1 6 counter, not to the "write to SOBUP signal). 

The transmission begins with activation of SEND which sends the 
start bit to pin TxD. One bit time later, DATA is activated, enabling 
the transmission of the output bit of the transmit shift register to TxD. 
The first shift pulse occurs one bit time after that. 

As data bits shift out to the right, zeros are clocked in from the left. 
When the MSB of the data byte is at the output position of the shift 
register, then the 1 that was initially loaded into the 9th position is 
just to the left of the MSB, and all positions to the left of that contain 
zeros. This condition flags the TX Control unit to do one last shift 
and then deactivate SEND and set Tl. This occurs at the 1 0th 
divide-by-1 6 rollover after "write to SOBUP. Reception is initiated by 
a detected 1 -to-0 transition at RxD. For this purpose RxD is 
sampled at a rate of 1 6 times whatever baud rate has been 
established. When a transition is detected, the divide-by-1 6 counter 
is immediately reset, and 1 FFH is written into the input shift register. 
Resetting the divide-by-1 6 counter aligns its rollovers with the 
boundaries of the incoming bit times. The 1 6 states of the counter 
divide each bit time into 1 6th. At the 7th, 8th, and 9th counter states 
of each bit time, the bit detector samples the value of RxD. The 
value accepted is the value that was seen in at least 2 of the 3 
samples. This is done for noise rejection. If the value accepted 
during the first bit time is not 0, the receive circuits are reset and the 
unit goes back to looking for another 1 -to-0 transition. This is to 
provide rejection of false start bits. If the start bit proves valid, it is 
shifted into the input shift register, and reception of the rest of the 
frame will proceed. 

As data bits come in from the right, 1 s shift out to the left. When the 
start bit arrives at the left-most position in the shift register, (which in 
mode 1 is a 9-bit register), it flags the RX Control block to do one 
last shift, loads SOBUF and RB8, and set Rl. The signal to load 
SOBUF and RB8, and to set Rl, will generated if, and only if, the 



following conditions are met at the time the final shift pulse is 

generated. 

1 R1 = 0, and 

2. Either SM2 = 0, or the received stop bit = 1 

If either of these two conditions is not met, the received frame is 
irretrievably lost. If both conditions are met, the stop bit goes into 
RB8, the 8 data bits go into SOBUF, and Rl is activated. At this time, 
whether the above conditions are met or not, the unit goes back to 
looking for a 1 -to-0 transition in RxD. 

More about modes 2 and 3 

Eleven bits are transmitted (through TxD), or received (through 
RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data 
bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be 
assigned the value of or 1 . On receive, the 9th data bit goes into 
RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 
the oscillator frequency in Mode 2. Mode 3 may have a variable 
baud rate generated from Timer 1 . 

Figures 9 and 10 show a functional diagram of the serial port in 
Modes 2 and 3. The receive portion is exactly the same as in Mode 
1 . The transmit portion differs from Mode 1 only in the 9th bit of the 
transmit shift register. 

Transmission is initiated by any instruction that uses SOBUF as a 
destination register. The "write to SOBUF" signal also loads TB8 into 
the 9th bit position of the transmit shift register and flags the TX 
Control unit that a transmission is requested. Transmission 
commences at S1 P1 of the machine cycle following the next rollover 
in the divide-by-1 6 counter (thus, the bit times are synchronized to 
the divide-by-1 6 counter, not to the "write to SOBUP signal). The 
transmission begins with activation of SEND, which puts the start bit 
at TxD. One bit time later, DATA is activated, which enables the 
output bit of the transmit shift register to TxD. One bit time later, 
DATA is activated, which enables the output bit of the transmit shift 
register to TxD. The first shift pulse occurs one bit time after that. 
The first shift clocks a 1 (the stop bit) into the 9th bit position of the 
shift register. Thereafter, only zeros are clocked in. Thus, as data 
bits shift out to the right, zeros are clocked in from the left. Then TB8 
is at the output position of the shift register, then the stop bit is just to 
the left of TB8, and all positions to the left of that contains zeros. 
This condition flags the TX Control unit to do one last shift and then 
deactivate SEND and set Tl. This occurs at the 11th divide-by-16 
rollover after "write to SOBUF". 

Reception is initiated by a detected 1 -to-0 transition at RxD. For this 
purpose RxD is sampled at a rate of 1 6 times whatever baud rate 
has been established. When a transition is detected, the 
divide-by-1 6 counter is immediately reset, and 1 FFFH is written to 
the input shift register. 

At the 7th, 8th and 9th counter states of each bit time, the bit 
detector samples the value of RxD. The value accepted is the value 
that was seen in at least 2 of the 3 samples. If the value accepted 
during the first bit time is not 0, the receive circuits are reset and the 
unit goes back to looking for another 1 -to-0 transition. If the start bit 
proves valid, it is shifted into the input shift register, and reception of 
the rest of the frame will proceed. As data bits come in from the 
right. 1s shift out to the left. When the start bit arrives at the left-most 
position in the shift register (which in Modes 2 and 3 is a 9-bit 
register), it flags the RX Control block to do one last shift, load 
SOBUF and RB8, and set Rl. 



January 1 995 



3-129 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



EX 




D Q 
CL 



Zero Detector 




Serial 
Port 
Interrupt 







Start 




Shift 




TX Control 




TX Clock 


T1 


Send 




RX Clock 


R1 


Receive 




RX Control 


Shift - 


Start 


11111 


1 1 



_ 



Input Shift Register 



t Shift 



SBUF 



80CL51 Internal Bus 



RxD 
P3.0AII 



Shift 




Clock 





TxD 
P3.1 Alt 

Output 



RxD 
. P3.0AH 
Input 
Function 



S4 . . S1 S6|S1 . 

ALE _ 

Write to SBUF 



S1 .... S6 S1 .... S6 S1 .... S6 S1 .... S6 S1 .... S6 S1 . 



S1 . . . . S6 S1 . . . . S6 S1 



S6P2 



_n n_ 



_n n_ 



RxD (Data Out) 



\ DO X D1 X D2 X D3 X D4 X D5 X « X 07 7 



TxD (Shift Clock) 

TJ 



|- | Write to SCON (Clear Rl) 



TxD (Shift Clock) 




Figure 7. Serial Port Mode 



January 1 995 



3-130 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



60CL51 Internal Bus 



1 — SMOD = 1 ! "' u 



4 



CL 




Zero Detector 



-ED- 



Start 


Shift Data 




TX Control 


TX Clock 


T1 Sena 



+ 16 | 

nil 



RX Clock Bl 


Load 
SBUF 


RX Control 

Start 


sunt 



TTT 



Input Shift Register 
(9 Bits) 

— U 







SBUF 





80CL51 Internal Bus 





j n o n n n n l 







Figure 8. Serial Port Mode 1 



January 1 995 



3-131 



PhiliDS SpmirwiHi „.t~ro 



Phase 2 Clock 
<1« lose) 



fSMOD > 



= 

(SMOD Is 
PCON.7) 



TB8 

4 



80CL51 Internal Bus 



[XI 




Zero Detector 



I 



Stop Bit Shift 
Start Gen. 

TX Control 



<3= 




Sample 



fl 



RX Clock R1 


Load 
SBUF 


RX Control 


Shift 


Start 




1FFH 



ETE 



Load 
SBUF 



Input Shift Register 
(9 Bits) 

i~Shlft 



I 



80CL51 Internal Bus 



TX 










Clock f| 


l fl fl 


n n n 


1 


i n n n 


|| Write to SBUF 














Send 








Data 










Shift 




d n n i 


n i 


i n 



TxD 
Tl 



Stop Bit Gen. 



I 



1 



RX 
Clock 



J a 





RxD 


| Bit 


A^X 


■» X 


D2 X 


D, X 




D5 


X 


D6 






( RB8 / Stop Bit 


Bit Detector 
Sample Times 


m 


■ 


M 


Ml 


Ml 


1 


Ml 




1 




1 




Shift 


(i 


n 


11 


n 


n 


n 


fl 




n 




n 


11 D 



Figure 9. Serial Port Mode 2 



January 1 995 



3-132 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



— 



Timer 1 
Overflow 



80CL51 Internal E 



Serial 
Port 
Interrupt 




Sample 



HX Clock FN 


Load 
SBUF 


RX Control 


Shift 


Stan 





TTT 



v: 



Input Shift Register 
(9 Bite) 



Load 
SBUF 




Tihln 



J L 



J 



80CL51 Internal Bus 



J L 



1= 



5en3 



J L 



Jl D H IL 



T 

r 
a 

> " 
/ 8 

m 

I 
t 



TxD 

n 



Stop Bit Gen. 
RX 



Clock 



ji Hi a 



II L 





RxD 


1 Bit / DO ) 




< ~ X 


D5 


X - X 




; rb» t 


f Stop Bit 


Sair^le'rirnes 


Ml M 


m m m 


Ml 


Ml 


1 


1 


m 


■ 


Shift 


n n 


n n o 


1 


1) 


n 


1) 


n 


n 


Fa 














1 








Figure 10. Ser 


al Port M 


ode 3 











January 1995 



3-133 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



The signal to load SOBUF and RB8, and to set Rl, will be generated 
if, and only if, the following conditions are met at the time the final 
shift pulse is generated. 

1, Rl = 0, and 

2. Either SM2 = or the received 9th data bit = 1 

If either of these conditions is not met, the received frame is 
irretrievably lost, and Rl is not set. If both conditions are met, the 
received 9th data bit goes into RB8, and the first 8 data bits 90 into 
SOBUF. One bit time later, whether the above conditions were met or 
not, the unit goes back to looking for a 1 -to-0 transition at the RxD 
input. 

1 .6 Interrupt System 

External events and the real-time-driven on-chip peripherals require 
service by the CPU asynchronous to do execution of any particular 
section of code. To tie the asynchronous activities of these functions 
to normal program execution, a multiple-source, two-priority-level, 
nested interrupt system is provided. The 80CL51 acknowledges 
interrupt requests from thirteen sources as follows: 

- INTO and INT1 

- Timer and Timer 1 



- UART serial I/O 

- INT2tolNT9(Port1) 

Each interrupt vectors to a separate location in program memory for 
its service routine. Each source can be individually enabled or 
disabled by corresponding bits in the Interrupt Enable Registers (IE, 
IEO). The priority level is selected via the Interrupt Priority register 
(IPO, IP1). All enabled sources can be globally disabled or enabled. 

1 .6.1 External Interrupts INT2/INT9 

Port 1 lines serve an alternative purpose as eight additional 
interrupts INT2 to INT9. When enabled, each of these lines may 
"wake-up" the device from Power-down mode. Using the 1X1 
register, each pin may be initialized to either active HIGH or LOW. 
IRQ1 is the interrupt request flag register. Each flag, if the interrupt 
is enabled, will be set on an interrupt request but must be cleared by 
software, i.e. via the interrupt software or when the interrupt is 
disabled. 

The Port 1 interrupts are level sensitive. A Port 1 interrupt will be 
recognized when a level (HIGH or LOW depending on Interrupt 
Polarity Register 1X1 ) on P1 x is held active for at least one machine 
cycle. The Interrupt Request is not served until the next machine 
cycle. 



INTERRUPT 
SOURCES 



IENO/1 IPO/1 
REGISTERS 




GLOBAL ENABLE 



Figure 11. Interrupt System 



January 1995 



3-134 



Philips Semiconductors 



Product specification 




PI .5 1 

P1.3 



-Oc±: 




— o 

— o 
— o 



— o 



Figure 12. External Interrupt Configuration 



Interrupt enable register IEN0, IEN1 
IEN0 (A8H) 



Interrupt priority register IPO, IP1 
IPO (B8H) 



| ESI | ESQ | ET1 | EX1 | ETO | EXO | | PS1 | PSO | PT1 | PX1 "~| 



Bit Symbol Function 

IEN0.7 EA General enable/disable control 

= no interrupt is enabled 

1 = any individually enabled interrupt will be accepted 
Unused 
Unused 

IEN0.4 ESO Enable UART SIO interrupt 
IEN0.3 ET1 Enable timer T1 interrupt 
Enable external interrupt 
Enable Timer TO interrupt 
Enable external interrupt 



IEN0.6 - 
IEN0.5 ES1 



IEN0.2 EX1 
IEN0.1 ETO 
IEN0.0 EXO 



IEN1 (E8H) 



| EX7 | EX6 | EX5 | EX4 ~| 



Bit Symbol Function 

IEN1.7 EX9 Enable external interrupt 9 

IEN1.6 EX 8 Enable external interrupt 8 

IEN1.5 EX7 Enable external interrupt 7 

IEN1.4 EX6 Enable external interrupt 6 

IEN1.3 EX5 Enable external interrupt 5 

IEN1.2 EX4 Enable external interrupt 4 

IEN1.1 EX3 Enable external interrupt 3 

IEN1 .0 EX2 Enable external interrupt 2 

where = interrupt disabled 
1 = interrupt enabled 



Bit Symbol Function 

IP0.7 - Unused 

IP0.6 - Unused 

IP0.5 PS1 Unused 

IP0.4 PSO UART SIO interrupt 

IPO. 3 PT1 Timer 1 interrupt priority level 

IP0.2 PX1 External interrupt 1 priority level 

IP0.1 PTO Timer interrupt priority level 

IPO.O PXO External interrupt priority level 

IP1 (B8H) 

| PX9 | PX8 | PX7 | PX6 | PX5 | PX4 | PX3 | PX2 | 

Bit Symbol Function 

IP1.7 PX9 External interrupt 9 priority level 
IP1.6 PX8 External interrupt 8 priority level 
IP1.5 PX7 External interrupt 7 priority level 
IP1.4 PX6 External interrupt 6 priority level 
IP1 .3 PX5 External interrupt 5 priority level 
IP1 .2 PX4 External interrupt 4 priority level 
IP1.1 PX3 External interrupt 3 priority level 
IP1 .0 PX2 External interrupt 2 priority level 
Interrupt priority is as follows: 

= low priority 

1 a high priority 



January 1995 



3-135 



Interrupt polarity register 1X1 
1X1 (E9H) 



| IL4 | IL3 | IL2 | 



Bit Symbol Function 

1X1 .7 IL9 External interrupt 9 polarity level 

1X1 .6 IL8 External interrupt 8 polarity level 

1X1 .5 IL7 External interrupt 7 polarity level 

1X1.4 IL6 External interrupt 6 polarity level 

1X1.3 IL5 External interrupt 5 polarity level 

1X1.2 IL4 External interrupt 4 polarity level 

1X1.1 IL3 External interrupt 3 polarity level 

1X1.0 IL2 External interrupt 2 polarity level 



Interrupt request flag register IRQ1 
IRQ1 (COH) 



IQ9 



I ' Q2 I 



Bit Symbol 

IRQ1.7 IQ9 External 

IRQ1.6 IQ8 External 

IRQ1.5 IQ7 External 

IRQ1.4 IQ6 External 

IRQ1.3 IQ5 External 

IRQ1.2 IQ4 External 

IRQ1.1 IQ3 External 

IRQ1.0 IQ2 External 



Function 

interrupt 9 request flag 
interrupt 8 request flag 
interrupt 7 request flag 
interrupt 6 request flag 
interrupt 5 request flag 
interrupt 4 request flag 
interrupt 3 request flag 
interrupt 2 request flag 



1 .6.2 Interrupt Vectors 





Vector 


Source 


xo 


0003H 


External 


so 


0023H 


UART SIO 


X5 


0053H 


External 5 


TO 


000BH 


Timer 


X6 


005BH 


External 6 


X1 


001 3H 


External 1 


X2 


003BH 


External 2 


X7 


0063H 


External 7 


T1 


001 BH 


Timer 1 


X3 


0043H 


External 3 


X8 


006BH 


External 8 


X4 


004BH 


External 4 


X9 


0073H 


External 9 



1 .7 Oscillator registers 

The on-chip circuitry of the 80CL51 is a single-stage inverting 
amplifier biased by an internal feedback resistor (Figure 13). For 
operation as standard quartz oscillator, no external components are 
needed except at 32 KHz. When using external capacitors, ceramic 
resonators, coils and RC networks to drive the oscillator, five 
different configurations are supported (see Figure 1 4 and oscillator 
options). 

In the Power-down mode the oscillator is stopped XTAL1 is pulled 
HIGH. The oscillator inverter is switched off to ensure no current will 
flow regardless of the voltage at XTAL1 . To drive the device with an 
external clock source, apply the external clock signal to XTAL1 , and 
leave XTAL2 to float, as shown in Figure 1 4(f). There are no 
requirements on the duty cycle of the external clock, since the input 
to the internal clocking circuitry is split sing a flip-flop. 

The following options are provided for optimum on-chip oscillator 
performance. Please state option when ordering. 

1.7.1 Oscillator options (see Figure 14) 

The following options are provided for optimum on-chip oscillator 
performance. Please state option when ordering. 

Osc.1 : Figure 14(c): An option for 32 kHz clock applications with 
external trimmer for frequency adjustment. A 4.7 MQ bias 
resistor is needed for use in parallel with the crystal. 

Osc. 2: Figure 1 4(e): An option for low-power, low-frequency 
operations using LC components. 

An option for medium frequency range applications. 

An option for high frequency range applications. 

Figure 14(g): An option for an RC oscillator. 



Osc. 3 
Osc. 4 
RC: 



Interrupt priority 

Each interrupt priority source can be set to either high or low priority. 
If both priorities are requested simultaneously, the controller will 
branch to the high priority vector. 

A low priority interrupt can only be interrupted by a high priority 
interrupt. A high priority interrupt routine cannot be interrupted. 

1.6.3 Related registers 

The following registers are used in conjunction with the interrupt 
system: 

Register Function 

1X1 Interrupt polarity register 

IRQ1 Interrupt enable register 

IEN1 Interrupt enable register (INT2-INT9) 

IPO Interrupt priority register 

IP1 Interrupt priority register (INT2-INT9) 







80CL51 



Cll 



JT 



TO INTERNAL 
TIMING CIRCUITS 



VDD 



i 



C 21 : 



Figure 13. Oscillator 



January 1995 



3-136 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 



80CL31/80CL51 



STANDARD QUARTZ 
OSCILLATOR 



QUARTZ OSCILLATOR 
WITH EXTERNAL 
CAPACITORS 



* 



/77 m 

(b) 



32 kH2 OSCILLATOR 



/77 



(c) 



CERAMIC RESONATOR 



ini — 

IUI 



rn 



LC-OSCILLATOR 



XTAL1 



/77 //7 
<•) 



EXTERNAL CLOCK 



RC-OSCILLATOR 



XTAL2 



VDD 



/77 



(g) 



Figure 14. Alternative Oscillator Configurations 



January 1 995 



3-137 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



OSCILLATOR TYPE SELECTION GUIDE 









C1 EXT. (pF) 


C2 EXT. (pF) 


MAX. RESONATOR 


RESONATOR 


f(MHz) 


OPTION 


MIN. 


MAX. 


MIN. 


MAX. 


SERIES RESISTANCE 


Quartz 


0.032 


OSC. 1 








5 


15 


15 kn 1 


Quartz 


1.0 


OSC. 2 





30 





30 


600 a 


Quartz 


3.58 


OSC. 2 





15 





15 


100 n 


Quartz 


4.0 


OSC. 2 





20 





20 


75 n 


Quartz 


6.0 


OSC. 3 





10 





10 


60 a 


Quartz 


10.0 


OSC. 4 





15 





15 


60 Q 


Quartz 


12.0 


OSC. 4 





10 





10 


40 a 


Quartz 


16.0 


OSC. 4 





15 





15 


20 n 


PXE 


0.455 


OSC. 2 


40 


50 


40 


50 


10£2 


PXE 


1.0 


OSC. 2 


15 


50 


15 


50 


100 11 


PXE 


3.58 


OSC. 2 





40 





40 


ion 


PXE 


4.0 


OSC. 2 





40 





40 


10 il 


PXE 


6.0 


OSC. 2 





20 







5£2 


PXE 


10.0 


OSC. 3 





15 





15 


6Q 


PXE 


12.0 


OSC. 4 


10 


40 


10 


40 


6fi 


LC 




OSC. 2 


20 


90 


20 


90 


10|iH = 1 Si 
100 uH = 5n 
1 mH = 75 a 



NOTES: 

1 . 32 kHz quartz crystals with a series resistance higher than 1 5 k£2 will reduce the guaranteed supply voltage range to 2.5 -3.5V. 

2. The equivalent circuit data of the internal oscillator compares with that of matched crystals. 



OSCILLATOR EQUIVALENT CIRCUIT PARAMETERS (SEE FIGURE 15) 



SYMBOL 


PARAMETER 


OPTION 


CONDITION 


MIN. 


TYP. 


MAX. 


UNIT 


9m 


Transconductance 


Osc.1 


T = +25 °C; Vqd = 4.5V 




15 




(IS 


9m 




Osc.2 


T = +25 °C; V DD = 4.5V 


200 


600 


1000 


US 


9m 




Osc.3 


T = +25 °C; Vqd = 4.5V 


400 


1500 


4000 


|1S 


9m 




Osc.4 


T = +25 °C; Vqd = 4.5V 


1000 


4000 


10000 


us 


C1, 


Input Capacitance 


Osc.1 






3.0 




pF 


C1i 




Osc. 2 






8.0 




pF 


C1j 




Osc.3 






8.0 




pF 


C1; 




Osc. 4 






8.0 




pF 


C2i 


Output Capacitance 


Osc.1 






23 




PF 


C2i 




Osc. 2 






8.0 




PF 


C2i 




Osc. 3 






8.0 




pF 


C2, 




Osc. 4 






8.0 




pF 


R2 


Output Capacitance 


Osc.1 






3800 




kn 


R2 




Osc.2 






65 




k£2 


R2 




Osc. 3 






18 




kn 


R2 




Osc. 4 






5.0 




kQ 



January 1995 



3-138 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



1 .7.2 RC Oscillator (see Figure 1 6) 

The externally adjustable RC-oscillator has a frequency range from 1 00 kHz to 500 kHz. 



C1| 



vi f© 9m R 2 



schmitt 

TRIGGER 



C2, 



Figure 15. Equivalent Circuit Diagram 







600 







2 4 6 

nc<ns> 

Figure 16. Frequency as a Function of RC 



January 1995 



3-139 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



1.8 Reset Circuitry 

To initialize the 80CL51 , a reset is performed by either of two 



- via the RST pin 

- via a power-on-reset 

It leaves the internal registers as follows: 



REGISTER 


CONTENT 


ACC 


0000 0000 


B 


0000 0000 


DPL 


0000 0000 


DPH 


0000 0000 


IEN0 


0000 0000 


IEN1 


0000 0000 


IPO 


XXOO 0000 


IP1 


0000 0000 


1X1 


0000 0000 


IRQ1 


0000 0000 


PCH 


0000 0000 


PCL 


0000 0000 


PCON 


OXXX 0000 


PSW 


0000 0000 


P0-P3 


1111 1111 


SOBUF 


XXXX XXXX 


SOCPN 


0000 0000 


SP 


0000 0111 


TCON 


0000 0000 


THO, TH1 


0000 0000 


TLO, TH1 


0000 0000 


TLO, TL1 


0000 0000 


TMOD 


0000 0000 



The reset state of the port pins is mask- programmable and can 
therefore be defined by the user. 

The standard reset value for port P0-P3 is 1111 1111. 

The reset input to the 80CL51 is RST pin 9. A Schmitt trigger 
qualifies the input for noise rejection. The output of the Schmitt 
trigger is sampled by the reset circuitry every machine cycle. 

A reset is accomplished by holding the RST pin HIGH for at least 
two machine cycles (24 oscillator periods), while the oscillator is 
running. The CPU responds by generating an internal reset. Port 
pins adopt their reset state immediately after RST goes HIGH. 
During reset ALE and PSEN are held HIGH. 

The external reset is asynchronous to the internal clock. The RST 
pin is sampled during State 5, Phase 2 of every machine cycle. After 
a HIGH is detected at the RST pin, an internal reset is repeated 
every cycle until RST goes LOW. 



The internal RAM is not affected by reset. When V D d is turned on 
the RAM contents are indeterminate. 

1.8.1 Power-on reset 

The 80CL51 contains on-chip circuitry which switch the port pins to 
the customer defined logic level as soon as V DD exceeds 
1 .3V. As soon as the minimum supply voltage is reached, the 
oscillator will start up. However, to ensure that the oscillator is stable 
before the controller starts, the clock signals are gated away from 
the CPU for a further 1 536 oscillator periods. During that time the 
CPU is held in a reset state. 

A hysteresis of approximately 50 mV at a typical power-on switching 
level of 1 .3 V will ensure correct operation. 

The on-chip Power-on circuitry can be switched off via the mask 
option "OFF'. This option reduces the power-down current to 
typically 800uA and can be chosen if external reset circuitry is used. 
For applications not requiring the internal reset option, "OFF" should 
be chosen. 

An automatic reset can be obtained at power-on by connecting the 
RST pin to V DD via a 10(iF capacitor. At power-on, the voltage on 
the RST pin is equal to V D d minus the capacitor voltage, and 
decreases from Vqq as the capacitor discharges through the 
internal resistor Rrst to ground. The larger the capacitor, the more 
slowly V H st decreases Vrst must remain above the lower threshold 
of the Schmitt trigger long enough to effect a complete reset. The 
time required is the oscillator start-up time, plus 2 machine cycles. 

1 .9 P80CL31 : ROMIess version of P80CL51 

The P80CL31 is a low voltage ROMIess version of the P80CL51 
microcontroller. The mask options on the P80CL31 are fixed as 
follows: 

• Port options: all ports have option "1S", i.e., standard port, high 
after reset 

• Oscillator option: OSC3 

• Power-on Reset option: OFF 

1.10 P80C51 : 5V standard version 

The P80C51 is a 5V version of the low voltage P80CL51 
microcontroller. All functional features of the P80CL51 are 
maintained in the P80C51 with the exception of the mask options. 
The mask options on the P80C51 are as follows: 

• Port options: all ports have option "1S", i.e., standard port, high 
after reset. 

• Oscillator options: OSC3 

• Power-on Reset option: OFF 





JJ 




RESET 
CIRCUITRY 


noi 







Figure 17. Reset Configuration at RST Pin 



January 1995 



3-140 



Philips Semiconductors 



Product specification 



80CL31/80CL51 







SWITCHING LEVEL 
POR 



SUPPLY 
VOLTAGE 



POWER-ON — 
RESET (INTERNAL) 



CPU RUNNING 



START-UP 
TIME 




1536 OSCILLATOR 
PERIODS DELAY 



Figure 18. Power-on Reset Switching Level 











vcc- 



vcc 



80CL51 



RRST 



Figure 19. Recommended Power-on Reset Circuitry 





■ 







January 1995 



3-141 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



2.0 RATINGS 

Limiting values in accordance with the Absolute Maximum System (IEC 134) 



SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNIT 


Vdd 


Supply voltage (pin 40) 


-0.5 


+ 6.5 


V 


v. 


All input voltages 


-0.5 


V DD +0.5 


V 


li, lo 


DC current into any input or output 




5 


mA 


Ptot 


Total power dissipation 




300 


mW 


T STG 


Storage temperature range 


-65 


+150 


°C 


T AMB 


Operating ambient temperature range 


-40 


+85 


°C 


Tj 


Operating junction temperature 




125 


°C 



1 1 1 1 1 



3-0 DC CHARACTERISTICS P80CL31/P80CL51 

V ss = 0V; T AMB = -40 to +85°C; all voltages with respect to V ss unless otherwise specified. 



SYMBOL 


PARAMETER 


CONDITIONS 


MIN. 


TYP. 


MAX. 


UNIT 


Vdd 


Supply voltage 


v ss = ov 


1.8 




6.0 


V 


Vdd 


RAM retention in power down mode 




1.0 






V 


Supply current operating (Note 1, Note 4) 


!dd 


OSC 1 option 


f C l k = 32KHz; V DD = 1.8V 
t amb - 25"C 






50 


uA 


'dd 


OSC 2 option 


f c)k = 3.58 MHz; V 0D = 3V 






2.5 


mA 


too 


OSC 3 option 


f c i k = 16MHz; V DD = 5V 






24 


mA 


Idd 


OSC 4 option 


f dk = 16MHz; V DD = 5V 






26 


mA 


Idle Mode (Note 2, Note 4) 


'dd 


OSC 1 option 


f dk = 32KHz; V DD = 1.8V 
t amb = 25°C 






25 


uA 


'dd 


OSC 2 option 


f dk = 3.58 MHz; V DD = 3V 






1.0 


mA 


!dd 


OSC 3 option 


f dk = 16MHz; V DD = 5V 






10 


mA 


Idd 


OSC 4 option 


fdk =16 MHz; V DD = 5V 






12 


mA 


IpD 


Power down (Note 3, Note 4) 


V DD = 1.8V, 
T AMB = 25°C 






10 


uA 


Inputs 


V|L 


Input voltage LOW 




Vss 




0.3V DD 


V 


V| H 


Input voltage HIGH 




0.7V DD 




Vdd 


V 


k. 


Input current logic (Port 1 , 2, 3) 


Vdd = SV, V| N = 0.4V 






100 


uA 


Vdd = 2.5V, V| N = 0.4V 






50 


uA 


Itl 


Input current logic 1 to transition 
(Port 1 , 2, 3) 


V DD =5V, V IN = V DD /2 






1.0 


mA 


Vdd = 2.5V, V, N = V DD /2 






500 


uA 


+/I IL 


Input leakage current (Port 0, EA) 


Vss < V| < Vqo 






10 


uA 


Outputs 




Output sink current LOW 


V DD = 5V, Vol = 0.4V 


1.6 






mA 


V DD = 2.5V, V OL = 0.4V 


0.7 






mA 


-IOH 


Output source current HIGH 
(push-pull options only) 


V DD = 5V; V 0H = V DD -0.4V 


1.6 






mA 


V DD = 2.5V; V 0H = V DD -0.4V 


0.7 






mA 


Rrst 


RST pull-down resistor 




10 




200 


k£J 



1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with t r = t f = 10ns; V| L = V ss ; V| H = V D d; 
XTAL 2 not connected; EA = RST = Port = V DD ; all open drain outputs connected to V S s- 

2. The idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with t r = t f = 10ns; V| L = V ss . XTAL 2 not 
connected; EA = Port = V D0 ; RST = V ss ; all open drain outputs connected to V S s 

3. The power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port = V D d; RST = V S s; all open 
drain outputs connected to Vss 

4. Circuits with Power-on Reset option "OFF" are tested at V DD minimum = 1 .8V; with option "ON" (typically 1 .3V) they are tested at V DD 
minimum = 2.3V. Please note, option "ON" is only available on P80CL51 . 



January 1995 



3-142 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



4.0 DC CHARACTERISTICS P80C51 

v S s = 



with respect to Vss unless otherwise specified. 



SYMBOL 


PARAMETER 


CONDITIONS 


MIN. 


TYP. 


MAX. 


UNIT 


V D 


Supply voltage 


v ss = ov 


4.5 





5.5 


V 


Supply Current 


Idd 


Operating (Note 1 ) 


'CLK= 16MHz, V DD = 5V 






24 


mA 


Idd 


Idle mode (Note 2) 


fcLK = 16MHz, V DD = 5V 






10 


mA 


IpD 


Power down (Note 3) 


V DD = 5V 






50 


M A 








V,L 


Input voltage LOW 




v S s 




0.3V DD 


V 


V|H 


Input voltage HIGH 




0.7V DD 




Vdd 


V 


IlL 


Input current logic (Port 1 , 2, 3) 


V| N = 0.4V 






100 


uA 


lit 


Input current logic 1 to transition (Port 1 , 2. 3) 


V IN = V DD /2 






1.0 


mA 


"lL 


II ipui ifc*d!\cty« uui itai it ^ui i u, Dtj 


V SS < V| < V D D 






10 


uA 


Outputs 


lot. 


Output sink current LOW 


V 0L = 0.4V 


1.6 






mA 


'OH 


Output source current HIGH 
(push-pull options only) 


V H = Vqd - 0.4V 


1.6 






mA 






Rrst 


RST pull-down resistor 




10 




200 





NOTES: 

1 . The operating supply current is measured with all output pins disconnected; XTAL 1 driven with tR = t F = 1 0ns; 
V IL = v SSi V IH = v DDi XTAL 2 not connected; EA = RST = Port = V DD ; all open drain outputs connected to V S s- 

2. The idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with tq = tp = 10ns; 
v il = V SS- XTAL 2 not connected; EA = Port = V DD ; RST = Vss; ail °P en drain outputs connected to Vss. 

3. The power-down current is measured with all output pins disconnected; XTAL 1 not connected; 
EA = Port = V DD ; RST = V S s; all open drain outputs connected to V ss . 

4. Please note, option "ON" is only available on P80CL51 . 




January 1995 



3-143 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 80CL31/80CL51 



5.0 AC CHARACTERISTICS 

Vqd = 5 V; Vss = 0V; T amb = -40 to +85°C; C|_ = 50 pF for Port 0, ALE and PSEN; C[_ = 40pF for all other outputs, unless otherwise specified. 



PROGRAM MEMORY (See Figure 20) 
, , 



SYMBOL 


PARAMETER 




VARIABLE CLOCK 


MIN. 


TYP. 


MAX. 


UNIT 




ALE pulse duration 


2T CK -40 






ns 


Ul 


Address set-up time to ALE 


Tck-40 






ns 


tLA 


Address hold time to ALE 


Tck-35 






ns 


tLC 


Time from ALE to control pulse PSEN 


Tck-25 






ns 


*LIV 


Time from ALE to valid instruction input 




- 


4T CK -100 


ns 


'cc 


Control pulse duration PSEN 


3T CK -35 







ns 


tew 


Time from PSEN to valid instruction input 






3T CK -125 








ns 


tci 


Input instruction hold time after PSEN 









ns 


t C IF 


Input instruction float delay after PSEN 






T C K-20 


ns 


Uiv 


Address to valid instruction input 






5T CK -115 


ns 


tAFC 


Address float time to PSEN 









ns 


EXTERNAL DATA MEMORY (See Figures 21 and 22) 


SYMBOL 


PARAMETER 




VARIABLE CLOCK 


MIN. 


TYP. 


MAX. 


UNIT 


*RR 


RD pulse duration 


6T CK -100 






ns 


<ww 


WR pulse duration 


6T CK -100 






ns 


tLA 


Address hold time after ALE 


Tck-35 






ns 


tRD 


RD to valid data input 


Tck-35 




5T CK -165 


ns 


tDFR 


Data float delay after RD 






2T CK -70 


ns 


tLD 


Time from ALE to valid data input 






8T CK -150 


ns 




Address to valid data input 






9T CK -165 


ns 


t|_w 


Time from ALE to RD and WR 


3T CK -50 




3T C k+50 


ns 


*AW 


Time from address to RD and WR 


4T CK -130 






ns 


*WHLH 


Time from RD or WR HIGH to ALE HIGH 


TCK-40 




Tck-40 


ns 


'dwx 


Data valid to WR transition 


Tck-60 






ns 


tDW 


Data set-up time before WR 


Tck-150 






ns 


tWD 


Data hold time after WR 


T O k-50 






ns 


twAFR 


Address float delay after RD (Note 1) 






12 


ns 



NOTE: 

1 . Interfacing the 80CL51 or P80C51 to devices with float times up to 75ns is permitted. This limited bus connection will not cause damage to 
Port drivers. 



January 1995 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 



80CL31/80CL51 



'cv - 



<LL- 



5 ER f 



X 



-'LC" 



'LA 



•AL 



ICC 



'CIV 



.H5 



■ 'AIV " 



-*j ^ J *— 'CIF 
I NSTIHPU p ^ AD OT 



\ r 



'CI 



ADDRESS A8 TO A15 



X 



ADDRESS A8 TO A15 



X 



Figure 20. Read from Program Memory 



•AL 



""^ < ' ADO TO AD7 



>: 



•ld 



'LW 



'LA 



'AW 



*RD 



< 



'AFR 



'AD 



'RR 



'WHLH 



x 



X 



'DFR 



X 



ADDRESS A8 TO A15 OR PORT 2 OUT 



X 



Figure 21 . Read from Data Memory 



January 1 995 



3-145 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 



80CL31/80CL51 



*WHLH ■ 



<AL — 



>: 



■ 'AW 



'LA 



\ 



•WW 



y 



T 'WX 



'DW - 



- 'WD - 



DATA OUTPUT 



X 



ADDRESS AS TO A15 OR PORT 2 OUT 



Figure 22. Write to Data Memory 



January 1995 



3-146 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 



80CL31/80CL51 







DOT TED LI NES 
IRE TOLTE WHEN 
RD OR WR 
ARE ACTIVE 



ONLY ACTIVE 
DURING A READ 
FROM EXTERNAL ' 
DATA MEMORY 

ONLY ACTIVE 
DURING A WRITE 
TO EXTERNAL 
DATA MEMORY 



EXTERNAL 
PROGRAM 



READ OR WRITE 
OF EXTERNAL 
DATA It 



XTAL1 
INPUT 



ONE MACHINE CYCLE 



se 

P1 P2 



ONE MACHINE CYCLE 



S1 S2 S3 

P1 P2 P1 K P1 P2 



P1 P2 



S6 
P1 P2 



I 



i_i — czzj — Li 



BUS 
(PORT 



llNSTl 

o, 1 in r~ 



ADDRESS 
A0-A7 



ADDRESS 




INST 


A0-A7 




IN 



INSTl Iaddress I I instI IaddressI I I 

IN I I A0-A7 | | IN | | A0-A7 | 



PORT 2 I | ADDRESS A8-A1S | ADDRESS AB-A1 5 | ADDRESS A8-A15 | ADDRESS A8-A^5 



BUS 

(PORT 0) 




DATA OUTPUT OR DATA INPUT | [ A °^^ S ^ 



ADDRESS A8-A15 OR PORT 2 OUT 



ADDRESS A8-A15 



PORT 1 I 
OUTPUT 



PORT 0,2,3 
OUTPUT | 



PORT 1 

output — T 



SERIAL 

PORT 

CLOCK 



SAMPLING TIME OF I/O PORT PINS DURING INPUT 



J~~L 



^4 



Figure 23. Instruction Cycle Timing 



January 1995 3-147 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 



80CL31/80CL51 



6.0 CHARACTERISTICS CURVES 



0.7V DD 



0.7V DD 



0.9V DD - 



0.4V DD - 



Figure 24. AC Testing Input Waveform 



500|lA 



SOO^A - - 



100HA 




2.5V 



Figure 25. Input Current at V D p = 5V 



January 1995 



3-148 



Philips Semiconductors 



Product specification 



Low-voltage single-chip 8-bit microcontrollers 



80CL31/80CL51 



10 
16 
14 
12 

<XTAL „ 
(MHz) 10 

8 
6 






























































































4 

2 






















■ 


* 












HMIiBHI 


2 4 6 
V DD (V) 

Figure 26. P80CL51/31 Frequency Operating Range 



'DD 

(mA) 











16 


MHz / 










> 


T 






















12 Ml 


it / 




































8 MHz 
























3.58 MHz 















2 4 6 

V DD (V) 

Figure 27. P80CL51/31 Typical Operating Current vs 
Frequency and V D0 , T amb = 25°C. 



•idle 

(mA) 











16 


J 

MHz / 














































12 MHz 






































'8 MHz 






















3 


58 MHz 



























VddM 

Figure 28. P80CL51/31 Typical Idle Current \ 
Frequency and V DD , T amb = 25°C. 



6 






4 

IpD 

fclA) 

2 














































































2 4 6 
V 0D (V) 

Figure 29. P80CL51/31 Typical Power-Down Current 
vs Frequency and V DD , T amb = 25«C. 



January 1995 



3-149 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 



87L51FA/87L51FB 



BLOCK DIAGRAM 




1996 Aug 16 



3-152 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



ORDERING INFORMATION 



8k x 8 
ROM 1 


6k x 8 
ROM1 


8k x 8 
EPROM 2 


16k x 8 
EPROM 2 


TEMPERATURE RANGE °C 
AND PACKAGE 


FREQ. 
(MHz) 


DWG. 
# 


S83L51FA-4N40 


S83L51FB-4N40 


S87L51FA-4N40 


S87L51FB-IN40 


OTP 


to +70, 

Af\ Pin Placti^ filial In. lino ParLano 
HL/^rlll rldallL L/Udl Ill-IllltS rdL-r\dyc 


3.5 
to 
16 


SOT129-1 






S87L51FA^tF40 


S87L51FB-4F40 


UV 


to +70, 

40-Pin Ceramic Dual In-line Package 
w/Window 


3.5 
to 
16 


0590B 


S83L51FA-4A44 


S83L51FB-4A44 


S87L51FA-4A44 


S87LS1FB-4A44 


OTP 


to +70, 
44"Pin Plsstic Lesded Chip Csrrier 


3.5 
to 
16 


SOT187-2 






S87L51FA-4K44 


S87L51FB-4K44 


UV 


to +70, 

44-Pin Ceramic Leaded Chip Carrier 
w/Window 


3.5 
to 
16 


1472A 


S83L51FA-4B44 


S83L51FB-4B44 


S87L51FA-4B44 


S87L51FB-4B44 


OTP 


to +70, 

AA Pin Plactir Onarl Plat Part 

*w-rin ridSuc wuau rial racK 


3.5 
to 
16 


SOT307-2 


S83L51FA-5N40 


S83L51FB-SN40 


S87L51FA-5N40 


S87L51FB-5N40 


OTP 


-40 to +85, 
40-Pin Plastic Dual In-line Package 


3.5 
to 
16 


SOT129-1 






S87L51FA-5F40 


S87L51FB-5F40 


UV 


-40 to +85, 
40-Pin Ceramic Dual In-line Package 
w/Window 


3.5 
to 
16 


0590B 


S87L51FA-5A44 


S87L51FB-5A44 


S87L51FA-5A44 


S87L51FB-5A44 


OTP 


-40 to +85, 
44-Pin Plastic Leaded Chip Carrier 


3.5 
to 
16 


SOT187-2 


S83L51FA-5B44 


S83L51FB-5B44 


S87L51FA-5B44 


S87L51FB-5B44 


OTP 


-40 to +85, 
44-rin plastic Quad Flat Pack 


3.5 
to 
16 


SOT307-2 


S83L51FA-7N40 


S83L51FB-7N40 


S87L51FA-7N40 


S87L51FB-7N40 


OTP 


Oto+70, 
40-Pin Plastic Dual In-line Package 


3.5 
to 
20 


SOT129-1 






S87L51FA-7F40 


S87L51FB-7F40 


UV 


0to+70, 

40-Pin Ceramic Dual In-line Package 
w/Window 


3.5 
to 
20 


0590B 


S83L51FA-7A44 


S83L51FB-7A44 


S87L51FA-7A44 


S87L51FB-7A44 


OTP 


to +70, 

AA-Pin PlaQtir i oaHori Phin Carrier 


3.5 
to 
20 


SOT 187-2 






S87LS1FA-7K44 


S87LS1FB-7K44 


UV 


to +70, 

44-Pin Ceramic Leaded Chip Carrier 
w/Window 


3.5 
to 
20 


1472A 


S83L51FA-8N40 


S83L51FB-8N40 


S87L51FA-6N40 


S87L51FB-8N40 


OTP 


to +85, 

40-Pin Plastic Dual In-line Package 


3.5 
to 
20 


SOT129-1 






S87L51FA-8F40 


S87L51FB-8F40 


UV 


-40 to +85, 
40-Pin Ceramic Dual In-line Package 
w/Window 


3.5 
to 
20 


0590B 


S83L51FA-8A44 


S83L51FB-8A44 


S87L51FA-6A44 


S87L51FB-8A44 


OTP 


-40 to +85, 
44-Pin Plastic Leaded Chip Carrier 


3.5 
to 
20 


SOT187-2 



NOTES: 

1 . Contact Philips for information on low voltage Mask-ROM versions. 

The 83C51 FA and 83C51FB are specified for 2.7V-5.5V operation @ 16MHz. 

2. OTP = One Time Programmable EPROM. UV = Erasable EPROM. 



1996 Aug 16 



3-151 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 



87L51FA/87L51FB 



DESCRIPTION 

The 87L51 FA and 87L51 FB Single-Chip 3.0V 8-Bit Microcontrollers 
are manufactured in an advanced CMOS process and are 
derivatives of the 80C51 microcontroller family. The 87L51 FA/B has 
the same instruction set as the 80C51 . 

This device provides architectural enhancements that make it 
applicable in a variety of applications for general control systems. 
The 87L51 FA contains 8k x 8 memory and the 87L51 FB contains 
16K x 8 memory, a volatile 256 x 8 read/write data memory, four 
8-bit I/O ports, three 1 6-bit timer/event counters, a Programmable 
Counter Array (PCA), a multi-source, two-priority-level, nested 
interrupt structure, an enhanced UART and on-chip oscillator and 
timing circuits. For systems that require extra capability, the 
87L51 FA/B can be expanded using standard 3.3V TTL compatible 
memories and logic. 

Its added features make it an even more powerful microcontroller for 
applications that require pulse width modulation, high-speed I/O and 
up/down counting capabilities such as motor control. It also has a 
more versatile serial channel that faci 
communications. 

FEATURES 

• 80C51 central processing unit 

• 3.0 to 4.5V V C c range 

•8kx8EPROM (87L51FA) 
16kx8EPROM (87L51FB) 

- Expandable externally to 64k bytes 

- Quick Pulse programming algorithm 

- Two level program security system 

• 256 x 8 RAM, expandable externally to 64k bytes 

• Three 1 6-bit timer/counters 

- T2 is an up/down counter 

• Programmable Counter Array (PCA) 

- High speed output 



PIN CONFIGURATIONS 




T2/P1.0[T 
T2EX/P1.1[T 
ECI/P1.2[? 
CEX0/P1.3[7 
CEX1/P1.4[T 
CEX2/P1. 5 [IF 

CExa/pi.6[T 

CEX4/P1.7[T 

rst[T 

RxD/P3.o[lO 
TxD/P3.lQT 
WTOP3.2Q2 
IHTT/P3.3Q3 
T(VP3.4Q4 
TI/P3.5Q5 
WR7P3.6[l6 
HC/P3.7[l7 
XTAL2[le 
XTAL1 [19 
Vss[20 



DUAL 
IN-LINE 
PACKAGE 



40] 



E 



E 



E 



E 



Voc 

POO/ADO 

P0.1/AD1 

P0.2/AD2 

P0.3/AD3 

P0.4/AD4 

P0.5/AD5 

P0.6/AD6 

P0.7/AD7 

EA/Vpp 

ALE/PROG 

PSEN 

P2.7/A15 

P2.6/A14 

P2.5/A13 

P2.4/A12 

P2.3/A11 

P2.2/A10 

P2.1/A9 

P2.0/A8 



Pulse Width Modulator 
Watchdog Timer 

• Four 8-bit I/O ports 

• Full-duplex enhanced UART 

- Framing error detection 

- Automatic address recognition 

• Power control modes 

- Idle mode 

- Power-down mode 

. Once , On Circuit Emuiation, Mode 

• Five package styles 

• OTP package available 



1996 Aug 16 



3-150 



853-172917200 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 



87L51 FA/87L51 FB 



CERAMIC AND PLASTIC LEADED CHIP CARRIER 
PIN FUNCTIONS 



7 Pf 



17 L 



□ 39 







L "1J 


u 










18 


28 






Pin 


Function 


Pin 


Function 


Pin 


Function 


1 


NC- 


16 


P3.4/T0 


31 


P2.7/A15 


2 


P1.0/T2 


17 


P3.5/T1 


32 


PSEN 


3 


P1.1/T2EX 


18 


P3.6/WR 


33 


ALE/PROG 


4 


P1.2/ECI 


19 


P3.7/RTJ 


34 


NC* 


S 


P1.3/CEX0 


20 


XTAL2 


35 


EAA/pp 


6 


P1.4/CEX1 


21 


XTAL1 


36 


P0.7/AD7 


7 


P1.5/CEX2 


22 


Vss 


37 


P0.6/AD6 


8 


P1.6/CEX3 


23 


NC* 


38 


P0.5/AD5 


9 


P1.7/CEX4 


24 


P2.0/A8 


39 


P0.4/AO4 


10 


RST 


28 


P2.1/A9 


40 


P0.3/A03 


11 


P3.0/RxD 


26 


P2.2/A10 


41 


P02/AD2 


12 


NC 


27 


P2.3/A11 


42 


P0.1/AD1 


13 


P3.1/TXD 


28 


P2.4/A12 


43 


POO/ADO 


14 


P3.2/TNT5 


29 


P2.5/A13 


44 




15 


P3.3/TNTT 


30 


P2.6/A14 







PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 



• DO NOT CONNECT 



o 







Y 








12 




Pin 


Function 


Pin 


Function 


1 


P1.5/CEX2 


16 


Vss 


2 


P1.6/CEX3 


17 


NC* 


3 


P1.7/CEX4 


18 


P2.0/A8 


4 


RST 


19 


P2.1/A9 


5 


P3.0/RKD 


20 


P2.2/A10 


6 


NC" 


21 


P2.3/A11 


7 


P3.1/TXD 


22 


P2.4/A12 


8 


P3.2/TNT0" 


23 


P2.5/A13 


8 


P3.3/1NTT 


24 


P2.6/A14 


10 


P3.4/T0 


25 


P2.7/A15 


11 


P3.5/T1 


26 


FST3J 


12 


P3.6/WH 


27 


ALE/PROG 


13 


P3.7/HD 


28 


NC" 


14 


XTAL2 


29 


EAWpp 


15 


XTAL1 


30 


P0.7/AD7 



Pin 


Function 


31 


P0.6/AD6 


32 


P0.5/AD5 


33 


P0.4/AD4 


34 


P0.3/AD3 


35 


P0.2/AD2 


36 


P0.1/AD1 


37 


P0.0/AD0 


38 




39 




40 


P1.0/T2 


41 


P1.1/T2EX 


42 


P1.2/ECI 


43 


P1.3/CEX0 


44 


P1.4/CEX1 



" DO NOT CONNECT 



PIN DESCRIPTIONS 



MNEMONIC 


PIN NUMBER 


TYPE 


DIP 


LCC 


QFP 


Vss 


20 


22 


16 


I 


Vcc 


40 


44 


38 


I 


PO.0-0.7 


39-32 


43-36 


37-30 


I/O 


P1.0-P1.7 


1-8 


2-9 


40-44, 


I/O 








1-3 






1 


2 


40 


I 




2 


3 


41 


I 




3 


4 


42 


I 




4 


5 


43 


I/O 




5 


6 


44 


I/O 




6 


7 


1 


I/O 




7 


8 


2 


I/O 




8 


9 


3 


I/O 


P2.0-P2.7 


21-28 


24-31 


18-25 


I/O 













NAME AND FUNCTION 







Ground: 0V reference. 

Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 

Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to 
them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data memory. In 
this application, it uses strong internal pull-ups when emitting 1s. Port also outputs the 
code bytes during program verification and receives code bytes during EPROM 
programming. External pull-ups are required during program verification. 

Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 1 pins that are externally pulled low will source current because of the internal pull-ups. 
(See DC Electrical Characteristics: l||_). Port 1 also receives the low-order address byte 
during program memory verification. Alternate functions include: 

T2 (P1.0): Timer/Counter 2 external count input/Clockout 

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 

ECI (P1 .2): External Clock Input to the PCA 

CEX0 (P1.3): Capture/Compare External I/O for PCA module 

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 2 pins that are externally being pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l| L ). Port 2 emits the high-order address byte 
during fetches from external program memory and during accesses to external data memory 
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal 
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses 
(MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins 
receive the high order address bits during EPROM programming and verification. 



1996 Aug 16 



3-153 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 



87L51FA/87L51FB 



PIN DESCRIPTIONS (Continued) 





PIN NUMBER 






MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAME AND FUNCTION 


P3.0-P3.7 


10-17 


11, 
13-19 


5, 
7-13 


I/O 


Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 3 pins that are externally being pulled low will source current because of the pull-ups. 
\oee uo tiecincai onaractenstics. luj. rort o aiso serves tne special features of tne oOOol 
family, as listed below: 




10 


11 


5 




RxD (P3.0): Serial input port 




11 


13 


7 





TxD (P3.1): Serial output port 




12 


14 


8 


I 


IHT0(P3.2): External interrupt 




13 


15 


9 


I 


INTT(P3.3): External interrupt 




14 


16 


10 


I 


TO (P3.4): Timer external input 




15 


17 


11 


I 


T1 (P3.5): Timer 1 external input 




16 


18 


12 





Wfi (P3.6): External data memory write strobe 


RST 


17 


19 


13 





RTJ (P3.7): External data memory read strobe 


9 


10 


4 


I 


Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to V ss permits a power-on reset using only an external 
capacitor to Vrjc- 


ALE/PROG 


30 


33 


27 


I/O 


Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the 
address during an access to external memory. In normal operation, ALE is emitted at a 
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. 
Note that one ALE pulse is skipped during each access to external data memory. This pin is 
also the program pulse input (PROG) during EPROM programming. 


PSEN 


29 


32 


26 





Program Store Enable: The read strobe to external program memorvWhen the 

87L51 FA/FB is executing code from the external program memory, PSEN is activated twice 






















each machine cycle, except that two PSEN activations are skipped during each access to 
external data memory. PSEN is not activated during fetches from internal program memory. 












ETWpp 


31 


35 


29 


I 


External Access Enable/Programming Supply Voltage: EA" must be externally held low 
to enable the device to fetch code from external program memory locations 0000H and 
1 FFFH. If EA" is held high, the device executes from internal program memory unless the 
program counter contains an address greater than 1 FFFH. This pin also receives the 
12.75V programming supply voltage (V PP ) during EPROM programming. If security bit 1 is 
programmed, EA" will be internally latched on Reset. 


XTAL1 


19 


21 


15 


I 


Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 


XTAL2 


18 


20 


14 





Crystal 2: Output from the inverting oscillator amplifier. 



NOTE: 

To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V cc + 0.5V or V ss - 0.5V, respectively. 
TIMER 2 

This is a 16-bit up or down counter, which can be operated as either 
a timer or event counter. It can be operated in one of three different 
modes (autoreload, capture or as the baud rate generator for the 
UART). 



In the autoreload mode the Timer can be set to count up or down by 
setting or clearing the bit DCEN in the T2CON Special Function 
Register. The SFR's RCAP2H and RCAP2L are used to reload the 
Timer upon overflow or a 1-to-0 transition on theT2EX input (P1.1). 

In the Capture mode Timer 2 can either set TF2 and generate an 
interrupt or capture its value. To capture Timer 2 in response to a 
1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON 
must be set. Timer 2 is then captured in SFR's RCAP2H and 
RCAP2L. 

As the baud rate generator, Timer 2 is selected by setting TCLK 
and/or RCLK in T2CON. As the baud rate generator Timer 2 is 
incremented at V2 the oscillator frequency. 



ENHANCED UART 

The 87L51 FA/FB UART has all of the capabilities of the standard 
80C51 UART plus Framing Error Detection and Automatic Address 
Recognition. As in the 80C51 , all four modes of operation are 
supported as well as the 9th bit in modes 2 and 3 that can be used 
to facilitate multiprocessor communication. 

The Framing Error Detection allows the UART to look for missing 
stop bits. If a Stop bit is missing, the FE bit in the SCON SFR is set. 
The FE bit can be checked after each transmission to detect 
communication errors. The FE bit can only be cleared by software 
and is not affected by a valid stop bit. 

Automatic Address Recognition is used to reduce the CPU service 
time for the serial port. The CPU only needs to service the UART 
when it is addressed and, with this done by the on-chip circuitry, the 
need for software overhead is greatly reduced. This mode works 
similar to the 9-bit communication mode, except that it uses only 8 
bits and the Stop bit is used to cause the Rl bit to be set. There are 
two SFRs associated with this mode. They are SADDR, which holds 
the slave address and SADEN, which contains a mask that allows 
selective masking of the slave address so that broadcast addresses 
can be used. 



1996 Aug 16 



3-154 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



PROGRAMMABLE COUNTER ARRAY 

The PCA is a sophisticated free-running 1 6 bit Timer/Counter that 
drives 5 modules that can be individually configured as Capture 
inputs, software timers, high speed outputs, or pulse width 
modulated outputs. In addition, module 4 can be configured as a 
software controlled watchdog timer. 

The Timer portion of the PCA can be configured to run in one of four 
different modes. The modes are: V2 the oscillator frequency, V 4 the 
oscillator frequency, Timer overflows, or from the ECI input. 

For the Capture/Compare mode each of the modules has a pair of 
registers associated with it called CCAPnH and CCAPnL (where 
n = 0, 1 , 2, 3, 4 depending on the module). Both positive and 
negative transitions can be captured. This means that the PCA has 
the flexibility to measure phase differences, duty cycles, pulse 
widths and a wide variety of other digital pulse characteristics. 

In the 16-bit software timer mode each of the modules can generate 
an interrupt upon a compare. 

For applications that require accurate pulse widths and edges the 
PCA modules can be used as High Speed Outputs (HSO). The PCA 
toggles the appropriate CEXn pin when there is a match between 
the PCA timer and the modules compare registers. 

The pulse width modulator mode for the PCA allows the conversion 
of digital information into analog signals. Each of the 5 modules can 
be used in this mode. The frequency of the PWM depends on the 
clock source for the PCA. The 8-bit PWM output is generated by 
comparing the low byte of the PCA (CL) with the module's CCAPnL 
SFR. When CL < CCAPnL, the output is high. When CL > CCAPnL, 
the output is low. 



POWER OFF FLAG 

The Power Off Flag (POF) is set by on-chip circuitry when the V cc 
level on the 87L51 FA/FB rises from to 3.3V. The POF bit can be 
set or cleared by software allowing a user to determine if the reset is 
the result of a power-on or a warm start after powerdown. The Vcc 
level must remain above 2.0V for the POF to remain unaffected by 
the V cc level. 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 
oscillator. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements 
on the duty cycle of the external clock signal, because the input to 
the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 

Reset 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-on reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. At power-on, the voltage on 
V cc and RST must come up at the same time for a proper start-up. 



Idle Mode 

In the idle mode, the CPU puts itself to sleep while all of the on-chip 
peripherals stay active. The instruction to invoke the idle mode is the 
last instruction executed in the normal operating mode before the 
idle mode is activated. The CPU contents, the on-chip RAM, and all 
of the special function registers remain intact during this mode. The 
idle mode can be terminated either by any enabled interrupt (at 
which time the process is picked up at the interrupt service routine 
and continued), or by a hardware reset which starts the processor in 
the same manner as a power-on reset. 

Power-Down Mode 

To save even more power, a Power Down mode can be invoked by 
software. In this mode, the oscillator is stopped and the instruction 
that invoked Power Down is the last instruction executed. The 
on-chip RAM and Special Function Registers retain their values until 
the Power Down mode is terminated. 

On the 87L51 FA/FB either a hardware reset or external interrupt can 
use an exit from Power Down. Reset redefines all the SFRs but 
does not change the on-chip RAM. An external interrupt allows both 
the SFRs and the on-chip RAM to retain their values. 

To properly terminate Power Down the reset or external interrupt 
should not be executed before V C c is restored to its normal 
operating level and must be held active long enough for the 
oscillator to restart and stabilize (normally less than 10ms). 

With an external interrupt, INTO and INT1 must be enabled and 
configured as level-sensitive. Holding the pin low restarts the 
oscillator but bringing the pin back high completes the exit. Once the 
interrupt is serviced, the next instruction to be executed after RETI 
will be the one following the instruction that put the device into 
Power Down. 

Design Consideration 

• When the idle mode is terminated by a hardware reset, the device 
normally resumes program execution, from where it left off, up to 
two machine cycles before the internal rest algorithm takes 
control. On-chip hardware inhibits access to internal RAM in this 
event, but access to the port pins is not inhibited. To eliminate the 
possibility of an unexpected write when Idle is terminated by reset, 
the instruction following the one that invokes Idle should not be 
one that writes to a port pin or to external memory. 

ONCE™ Mode 

The ONCE ("On-Circuit Emulation") Mode facilitates testing and 
debugging of systems using the 87L51 FA/FB without the 
87L51 FA/FB having to be removed from the circuit. The ONCE 
Mode is invoked by: 

1 . Pull ALE low while the device is in reset and PS EN is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in ONCE Mode, the Port pins go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the 87L51 FA/FB is 
in this mode, an emulator or test CPU can be used to drive the 
circuit. Normal operation is restored when a normal reset is applied. 



1996 Aug 16 



3-155 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 



87L51FA/87L51FB 



Table 1 . External Pin Status During Idle and Power-Down Mode 



MODE 


PROGRAM 
MEMORY 


ALE 


PSER 


PORTO 


PORT 1 


PORT 2 


PORT 3 


idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Float 


Data 


Data 


Data 



ABSOLUTE MAXIMUM RATINGS 12 3 



PARAMETER 


RATING 


UNIT 


Operating temperature under bias 




to +70 or -40 to +85 


°C 


Storage temperature range 


-65 to +150 


°c 


Voltage on FJAVVpp pin to Vss 


to +13.0 


V 


Voltage on any other pin to Vss 






-0.5 to +6.5 


V 


Maximum Iql per I/O pin 


15 


mA 


Power dissipation (based on pac 
device power consumption) 


kage heat transfer limitations, not 


1.5 


W 



NOTES: 

1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V s s unless otherwise 
noted. 

Electrical Deviations from Commercial Specifications for Extended Temperature Range 

DC and AC parameters not included here are the same as in the commercial temperature range table. 



1996 Aug 16 



3-156 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



DC ELECTRICAL CHARACTERISTICS 



SYMBOL 


PARAMETER 


TCCT 
1 CO 1 

CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 












Vi£ 


Input low voltage, except EA 2 ' 3 




-0.5 




0.8 


V 


V,L1 


— — 

Input low voltage to EA 2 ' 3 









0.8 


V 


V| H 


Input high voltage, except XTAL1 , RST 2 ' 4 




2.0 




Vcc+0.5 


V 


V,H1 


Input high voltage, XTAL1 , RST 2 ' 4 




0.7V C c 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 3 s 


Iol = 1 -6mA 6 






0.45 


V 


V li 


Output low voltage, port 0, ALE, PSEN 5 


Iol = 3.2mA 6 






0.45 


V 


Voh 


Output high voltage, ports 1 , 2, 3, ALE, PSEN' 


■OH - tU^lM 


V cc " 0-5 






V 


V H1 


Output high voltage (port In external bus mode), 


I h = -3.2mA 


Vcc-0.7 






V 


ALE 8 , PSEN' 












IlL 


Logical input current, ports 1 , 2, 3 2 


V| N = 0.4V 






-50 


HA 


Itl 


Logical 1 -to-0 transition current, ports 1 , 2, 3 2 


See note 9 






-650 


HA 


!u 


Input leakage current, port 


0.45 V, N < V co - 0.3 






±10 


HA 


Ice 


Power supply current:2 


See note 1 1 










Active mode @ 20MHz 10 
Idle mode @ 20MHz 
Power-down mode 






9 
2 
10 


22 
6 
75 


mA 
mA 
HA 








First 


Internal reset pull-down resistor 




40 




225 


kfl 










Cio 


Pin capacitance 12 (except EA") 








15 


pF 









NOTES: 

1. 
2. 
3. 
4. 
5. 



Typical ratings are not guaranteed. The values listed are at room temperature, 3.3V. 
These values apply only to T amb = 0°C to +70°C. 
For V c c voltages above 3.6V and less than 5.5V, V| L - 0.3V C c - 0.1 
For V c voltages above 3.6V and less than 5.5V, V| H = 0.3V C c + 0.92 
Under steady state (non-transient) conditions, Iol m ust be externally limited as follows: 
Maximum I l per port pin: 1 5mA ("NOTE: This is 85°C specification.) 

Maximum Iol per 8-bit port: 26mA 
Maximum total Iol f ° r all outputs: 71 mA 
If I l exceeds the test condition, V l may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

6. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the Vols of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Iol can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs ex ceed th e test conditions. 

7. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the 0.9V CC specification when the 
address bits are stabilizing. 

8. ALE is tested to Vom , except when ALE is off then Voh is 'he voltage specification. 

9. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when Vin is approximately 1 .5V. 

1° Iocmax at other frequencies is given by: Active mode: Iccmax = 0.8 x FREQ + 6: Idle mode: Iccmax = 0-19 x FREQ +2.50, 
where FREQ is the external oscillator frequency in MHz. Iccmax is given in mA. See Figure 8. 

11. See Figures 9 through 12 for l C c test conditions. 

12. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). These values are 
guaranteed by design and are not tested. 



1996 Aug 16 



3-157 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



AC ELECTRICAL CHARACTERISTICS 

Tamb = "°C to +7CTC, -40 to +85°C, V CC = 3.0V to 4.5V, V SS = 0V 1 ■ 2 ' 3 



SYMBOL 


FIGURE 


r% A n ami r- T r~~ n 

PARAMETER 


16MHz CLOCK 


VARIABLE CLOCK 


UNIT 


MIN 


MAX 


MIN 


MAX 


1/tcLCL 


1 




Oscillator frequency -4, -5 






3.5 


16 


MHz 


-7, -8 






3.5 


20 


MHz 


*LHLL 




ALE pulse width 


85 




2tcLCL-40 




ns 


UvLL 




Address valid to ALE low 


22 




tcLCL-^0 




ns 


'llax 




Address hold after ALE low 


32 




tCLCL-30 




ns 


'lLIV 




ALE low to valid instruction in 




150 




4tcLCL-100 


ns 


tLLPL 




ALE low to PSEN low 


32 




•CLCL-SO 




ns 


tPLPH 




PSEN pulse width 


142 




3tcLCL^t5 




ns 


tpLIV 




PSEN low to valid instruction in 




82 




3tcLOL-105 


ns 


l PXIX 


Input instruction hold after PSEN 












ns 


tpxiz 




Input instruction float after PSEN 




37 




tCLCL-25 


ns 


'aviv 




Address to valid instruction in 




207 




5tCLCL-105 


ns 


tpLAZ 




PSEN low to address float 




10 




10 


ns 


Data Memory 


'rlrh 


2,3 


RD pulse width 


275 




6tci_CL-100 




ns 


twLWH 


2,3 


WR pulse width 


275 




6tc LCL -100 




ns 


tRLDV 


2,3 


RD low to valid data in 




147 




5t CLCL -165 


ns 


*RHDX 


2,3 


Data hold after RD 












ns 


tRHDZ 


2,3 


Data float after RD 




65 




2tcLCL-60 


ns 


Illdv 


2,3 


ALE low to valid data in 




350 




8tcLCL-150 


ns 


tAVDV 


2,3 


Address to valid data in 




397 




9t C LCL-165 


ns 


*LLWL 


2,3 


ALE low to RD or WR low 


137 


237 


3ICLCL-50 


3tcLCL+50 


ns 


Iavwl 


2, 3 


Address valid to WR low or HE low 


122 




4tcLCL-130 




ns 


tQVWX 


2,3 


Data valid to WR transition 


13 




tcLCL-50 




ns 


'WHQX 


2,3 


Data hold after WR 


13 




tcLCL-50 




ns 


tQVWH 


3 


Data valid to WR high 


287 




7tcLCL-150 




ns 


(rlaz 


2, 3 


RD low to address float 












ns 


'WHLH 


2, 3 


RD or WR high to ALE high 


23 


103 


tCLCL-^0 


tcLCL+40 


ns 


External Clock 


tCHCX 


5 


High time 


12 




20 




ns 


feLCX 


5 


Low time 


12 




20 




ns 


tdCH 


5 


Rise time 




20 




20 


ns 


tcHCL 


5 


Fall time 




20 




20 


ns 


Shift Register 


txLXL 


4 


Serial port clock cycle time 


1 




1 2tcLCL 




us 


<QVXH 


4 


Output data setup to clock rising edge 


492 




10tcLCL-133 




ns 


*XHQX 


4 


Output data hold after clock rising edge 


8 




21CLCL-H7 




ns 


txHDX 


4 


Input data hold after clock rising edge 












ns 


txHDV 


4 


Clock rising edge to input data valid 




492 




10tcLCL-133 


ns 



NOTES: 

1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 87L51 FA/FB to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 



1996 Aug 16 



3-158 



Philips Semiconductors 



Product specification 



8-bit microcontrollers 



87L51FA/87L51FB 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 

T (= time). The other characters, depending on their positions, 

indicate the name of a signal or the logical status of that signal. The 

designations are: 

A - Address 

C - Clock 

D - Input data 

H - Logic level high 

I - Instruction (program memory contents) 
L - Logic level low, or ALE 



P - PEER 
Q- Output data 
R - ED signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: Iavll = Ti me f° r address valid to ALE low. 
t ULPU = Time for ALE low to PEER low. 




Wll 



PORT 2 



Illdv 



t|_LWL ' 



'llax 



\ j ' A0-A7 \ 

? V FROM Rl OR DPL / 



*AVWL 



tptLRH 



'rldv 



tAVDV 



•rhdx " 



■< DATA IN 



*WHLH 



Irhdz. 




A0-A7 FROM PCL 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15FROM POH 



Figure 2. External Data Memory Read Cycle 



1996 Aug 16 



3-159 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 



87L51FA/87L51FB 







•avll 

>x 



y 



tLLWL 



'llax 



A0-A7 
FROM Rl OR DPL 



X 



twLWH 



*QVWX 



twHLH 



*AVWL 



•qvwh 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 3. External Data Memory Write Cycle 



INSTRUCTION | o|l|2|3|«| 5 |e|7|e| 

- JLJIJTJLJLJIJTJIJIJT^^ 



f*~ *XLXL -*j 



OUTPUT DATA . 

f ' 
WRITE TO SBUF 



tQVXH 



r 



( XHQX 



_t~lj- 



^IX>C^>CZ3<ZI3<C3I>CI3<IEXIE7 

J ~*"| H~ 'XHDX 

"1 SETTI 



( XHDV 



CLEAR Rl 



t 

SET Rl 



Figure 4. Shift Register Mode Timing 



Vfjc-0-5 J 

0.45V ~T 0.2VCC-0-- 

<CHCL- 



>i y 



~tCLCX~* 
— tCLCL 



tCHCX* 
"toLCH 



Figure 5. External Clock Drive 



5U<"C309 
_ 



1996 Aug 16 



3-160 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



VcC-0-3 



X 



0.3VCC+0-92 
0.3VCG-0-1 




NOTE: 

AC inputs during testing are driven at V cc -0.3 for a logic T and 0.3V lor a logic '0'. 
Timing measurements are made at V, H min lor a logic '1' and V| L lor a logic '0'. 



Figure 6. AC Testing Input/Output 



vload - 



vload-o.iv 



TIMING 
REFERENCE 
POINTS 



>V H-01V 
VQL+0.1V 



NOTE: 

For timing purposes, a port Is no longer floating when a 100mV change from load voltage occurs, 
and begins to float when a 100mV change from the loaded V 0H /V 0L level occurs. IcWol * ±20mA. 



Figure 7. Float Waveform 



25 

Note: 3.3V operation will reduce l C c 
vs. XTAL frequency. This curve will 

ibe- 20 



ICC mA 




MAX ACTIVE MODE 

= 0.8 X FREQ. + 6.0 



'DDMAX = 



TYP ACTIVE MODE 



MAX IDLE MODE 
'ODIDLE- -' 9 X FREQ. ♦ 2.5 

TYP IDLE MODE 



8MHz 12MHz 
FREQ AT XTALI 



16MHz 20MHz 



Figure 8. l C c vs. FREQ Valid only within frequency specifications of the device under test 



1996 Aug 16 



3-161 



Philips Semiconductors 



Product specification 



CMOS: 



J.OV 8-bit microcontrollers 87L51 FA/87L51 FB 



yep 



(NO- 



CLOCK SIGNAL - 





Vcc 




RST 


PO 




ES 


XTAL2 




XTAL1 







lec 



Vcc 



(NO- 



CLOCK SIGNAL - 



ft 



RST 


Vcc 




PO 






XTAL2 




XTAL1 




Vss 





I 



— 



Figure 9. Ice Test Condition, Active Mode 
All other pins are disconnected 



Figure 1 0. Ice Test Condition, Idle Mode 
All other pins are disconnected 



tCHCL" 



y 



•-•choc* 

*-*CLC>cH *— tCLCH 



tCLCL 




nal Waveform for l cc Tests In Active and Idle Modes 
«CLCH = tCHCL = 5ns 



r 



(NQ- 



Vcc 



Vcc 



XTAL2 
XTAL1 

vss 



lcc 

L 



Figure 12. I cc Test Condition, Power Down Mode 
All other pins are disconnected. V C c = 2V to 4.5V 



1996 Aug 16 



3-162 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



EPROM CHARACTERISTICS 

The 87L51 FA/FB is programmed by using a modified Quick-Pulse 
Programming™ algorithm. It differs from older methods in the value 
used for V PP (programming supply voltage) and in the width and 
number of the ALE/PROG pulses. 

The 87L51 FA/FB contains two signature bytes that can be read and 
used by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87L51 FA/FB manufactured 
by Philips. 

Table 2 shows the logic levels for reading the signature byte, and for 
programming the program memory, the encryption table, and the 
security bits. The circuit configuration and waveforms for quick-pulse 
programming are shown in Figures 1 3 and 1 4. Figure 1 5 shows the 
circuit configuration for normal program memory verification. 

Quick-Pulse Programming 

The setup for microcontroller quick-pulse programming is shown in 
Figure 13. Note that the 87L51 FA/FB is running with a 4 to 6MHz 
oscillator. The reason the oscillator needs to be running is that the 
device is executing internal address and program data transfers. 

The address of the EPROM location to be programmed is applied to 
ports 1 and 2, as shown in Figure 13. The code byte to be 
programmed into that location is applied to port 0. RST, PSEN and 
pins of ports 2 and 3 specified in Table 2 are held at the 'Program 
Code Data' levels indicated in Table 2. The ALE/PROG is pulsed 
low from 5 to 25 times as shown in Figure 14. 

To program the encryption table, repeat the S to 25 pulse 
programming sequence for addresses through 1 FH, using the 
'Pgm Encryption Table' levels. Do not forget that after the encryption 
table is programmed, verification cycles will produce only encrypted 
data. 

To program the security bits, repeat the 5 to 25 pulse programming 
sequence using the 'Pgm Security Bit' levels. After one security bit is 
programmed, further programming of the code memory and 
encryption table is disabled. However, the other security bit can still 
be programmed. 

Note that the EATVpp pin must not be allowed to go above the 
maximum specified V PP level for any amount of time. Even a narrow 
glitch above that voltage can cause permanent damage to the 
device. The V PP source should be well regulated and free of glitches 
and overshoot. 



Program Verification 

If security bit 2 has not been programmed, the on-chip program 
memory can be read out for program verification. The address of the 
program memory locations to be read is applied to ports 1 and 2 as 
shown in Figure 15. The other pins are held at the 'Verify Code Data' 
levels indicated in Table 2. The contents of the address location will 
be emitted on port 0. External pull-ups are required on port for this 
operation. 

If the encryption table has been programmed, the data presented at 
port will be the exclusive NOR of the program byte with one of the 
encryption bytes. The user will have to know the encryption table 
contents in order to correctly decode the verification data. The 
encryption table itself cannot be read out. 

Reading the Signature Bytes 

The signature bytes are read by the same procedure as a normal 
verification of locations 030H and 031 H, except that P3.6 and P3.7 
need to be pulled to a logic low. The values are: 
(030H) = 15H indicates manufactured by Philips 
(031 H) = B1H indicates 87L51 FA 
= B2H indicates 87L51FB 

Program/Verify Algorithms 

Any algorithm in agreement with the conditions listed in Table 2, and 
which satisfies the timing specifications, is suitable. 

Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is exposed to 
light with wavelengths shorter than approximately 4,000 angstroms. 
Since sunlight and fluorescent lighting have wavelengths in this 
range, exposure to these light sources over an extended time (about 
1 week in sunlight, or 3 years in room level fluorescent lighting) 
could cause inadvertent erasure. For this and secondary effects, 
it is recommended that an opaque label be placed over the 
window. For elevated temperature or environments where solvents 
are being used, apply Kapton tape Fluorglas part number 2345-5, or 
equivalent. 

The recommended erasure procedure is exposure to ultraviolet light 
(at 2537 angstroms) to an integrated dose of at least 15W-s/cm 2 . 
Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm 2 rating 
for 20 to 39 minutes, at a distance of about 1 inch, should be 
sufficient. 

Erasure leaves the array in an all 1s state. 



Table 2. EPROM Programming Modes 1 2 3 



MODE 


RST 


PSEN 


ALE/PROG 


ES/Vpp 


P2.7 


P2.6 


P3.7 


P3.6 


Read signature 







1 


1 














Program code data 







0" 


V PP 


1 





1 


1 


Verify code data 







1 


1 








1 


1 


Pgm encryption table 









Vpp 


1 





1 





Pgm security bit 1 







0" 


Vpp 


1 




1 


Pgm security bit 2 







0" 


Vpp 


1 


1 









NOTES: 

1 . '0' = Valid low for that pin, '1 ' = valid high for that pin. 

2. V P p = 12.75V ±0.25V. 

3. Vcc = 5V±1 0% during programming and verification. 

4. ALE/PROG receives 5 to 25 programming pulses while V PP is held at 12.75V. Each programming pulse is low for 100ps (±10jis) and high for 
a minimum of 10ns. 



"Trademark phrase of Intel Corporation. 



1996 Aug 16 



3-163 



Philips Semiconductors 



Product specification 



CMOS single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 



\ 

A0-A7 ) 

V 



RST 
P3.6 
P3.7 



XTAL1 

vss 



87L51FA 
87L51FB 



VCC 
PO 

EATVpp 
ALE/PT1D5 
PSER 

P2.7 
P2.6 
P2.0-P2.5 



A- 
V 







A- 
V 



PGM DATA 
+12.75V 

25 100)is PULSES TO GROUND 



1 



A8-A13 











SU00053A 



1 



Figure 13. Programming Configuration 



5 10 25 PULSES 



ALE/PRCTT 



"LrLTLTLTL, "LrLTLTLTLr 



1<VsMIN 



H |- ,0 * si, ° r| 

TL 



Figure 14. PROG Waveform 



pi 

RST 
P3.6 
P3.7 
XTAL2 

XTAL1 

v ss 



vcc 



EAWpp 



67L51FA PSER 
87L51FB 

P2.7 
P2.6 



h 



V 



PGM DATA 

1 


ENABLE 



A8-A12 



Figure 15. Program Verification 



1996 Aug 16 



3-164 



Philips Semiconductors 




Product specification 



5 single-chip 3.0V 8-bit microcontrollers 87L51 FA/87L51 FB 











EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


V PP 


Programming supply voltage 


12.5 


13.0 


V 


lp P 


Programming supply current 




50 


mA 


1/tCLCL 


Oscillator frequency 


4 


6 


MHz 


•avgl 


Address setup to PROG low 


48to L GL 








tGHAX 


Address hold after PROG 


481CLCL 






'dvgl 




Data setup to PROG low 


48tc LCL 






tQHDX 


Data hold after PROG 


48tcLCL 






'ehsh 


P2.7 (ENABLE) high to V PP 


•*8tcLCL 






tSHGL 


Vp P setup to PROG low 


10 




us 


•qhsl 


V PP hold after PROG 


10 




(IS 


*GLGH 


PRUG width 


90 


110 


us 


<AVQV 


Address to data valid 




48t C LCL 




*ELQZ 


ENABLE low to data valid 




48tc L CL 




'ehqz 


Data float after ENABLE 





48tcLCL 




tGHGL 


PROG high to PROG low 


10 




us 



R.O-P1.7 
P2.0-P2.4 



c 



ALE/PHD5 



*DVGL 

Iavgl 



PROGRAMMING 



^ DATA IN > 



*GLGH 
'SHGL 



EAWpp 



P2.7 
ENABLE 



* t£HSH -* 



VERIFICATION 



> 



< 



tGHDX 
tGHAX 



tGHGL 



tGHSL 



LOGIC 1 



/ 



•elqv 



'avqv 



tEHQZ 



NOTE: 

* FOR PROGRAMMING VERIFICATION SEE FIGURE 13. 
FOR VERIFICATION CONDITIONS SEE FIGURE 15. 

Figure 16. EPROM Programming and Verification 



1996 Aug 16 



3-165 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



DESCRIPTION 

The Philips 80C32/87C52 is a high-performance microcontroller 
fabricated with Philips high-density CMOS technology. The Philips 
CMOS technology combines the high speed and density 
characteristics of HMOS with the low power attributes of CMOS. 
Philips epitaxial substrate minimizes latch-up sensitivity. 

The 87C52 contains an 8k x 8 EPROM and the 80C32 is ROMIess. 
Both contain a 256 x 8 RAM, 32 I/O lines, three 16-bit 
counter/timers, a six-source, two-priority level nested interrupt 
structure, a serial I/O port for either multi-processor 
communications, I/O expansion or full duplex UART, and on-chip 
oscillator and clock circuits. 

In addition, the 80C32/87C52 has two software selectable modes of 
power reduction — idle mode and power-down mode. The idle mode 
freezes the CPU while allowing the RAM, timers, serial port, and 
interrupt system to continue functioning. The power-down mode 
saves the RAM contents but freezes the oscillator, causing all other 
chip functions to be inoperative. 

See f 



FEATURES 

• 80C51 based architecture 



PIN CONFIGURATIONS 



- 8k x 8 EPROM (87C52) 

- ROMIess (80C32) 

- 256 x 8 RAM 

- Three 1 6-bit counter/timers 

- Full duplex serial channel 

- Boolean processor 

• Memory addressing capability 

- 64k ROM and 64k RAM 

• Power control modes: 

- Idle mode 

- Power-down mode 

• CMOS and TTL compatible 

• Three speed ranges: 

- 3.5 to 16MHz 

- 3.5 to 24MHz 

- 3.5 to 33MHz 

• Five package styles 

• Extended temperature ranges 

• OTP package available 



P1.0/T2 [7 

P1.1/T2EX [T 

P1.2 [T 

P1.3 [4 

P1.4 [? 

P1.5 [| 

P1.6 (T 

P1.7 [T 

RST [7 

RXD/P3.0 [To 

TXD/P3.1 [TT 

TNT07P3.2 [TJ 

INTT/P3.3 [Tj 

T0/P3.4 [TJ 

T1/P3.5 [TJ 

WR7P3.6 [TJ 

HD7P3.7 [TJ 

XTAL2 [TJ 

XTAL1 [TJ 

Vss [20 



CERAMIC 

AND 
PLASTIC 
DUAL 
IN-LINE 
PACKAGE 



*5| V D0 
39] P0.O/AD0 
38] P0.1/AD1 
37] P0.2/AD2 
36] P0.3/AD3 
35] P0.4/AD4 
34] P0.5/AD5 
33] P0.6/AD6 
3| P0.7/AD7 
5l] EATVpp 
io] ALE/PROS 
JJ] PSEN 
JJ] P2.7/A15 
IH P2.6/A14 
26] P2.5/A13 
2§ P2.4/A12 
H] P2.3/A1I 
H] P2.2/AI0 
H] P2.1/A9 
|TJ P2.0/A8 



1996 Aug 16 



3-166 



853-1562 17195 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



ORDERING INFORMATION 



ROMIess 


EPROM 1 


TEMPERATURE RANGE °C 
AND PACKAGE 


FREQ 
MHz 


DRAWING 
NUMBER 


P80C32EBP N 


P87C52EBP N 


OTP 


to +70, Plastic Dual In-line Package 


16 


SOT129-1 


P80C32EBA A 


P87C52EBA A 


OTP 


to +70, Plastic Leaded Chip Carrier 


16 


SOT187-2 




P87C52EBF FA 


UV 


to +70, Ceramic Dual In-line Package 


16 


0590B 




P87C52EBL KA 


UV 


to +70, Ceramic Leaded Chip Carrier 


16 


1472A 


P80C32EBB B 


P87C52EBB B 


OTP 


to +70, Plastic Quad Flat Pack 


16 


SOT307-2 


P80C32EFP N 


P87C52EFP N 


OTP 


—40 to +85, Plastic Dual In-line Package 


16 


SOT129-1 


P80C32EFA A 


P87C52EFA A 


OTP 


—40 to +85, Plastic Leaded Chip Carrier 


16 


SOT1 87-2 




P87C52EFF FA 


UV 


—40 to +85, Ceramic Dual In-line Package 


16 


0590B 


P80C32EFB B 


P87C52EFB B 


OTP 


—40 to +85, Plastic Quad Flat Pack 


16 


SOT307-2 


P80C32IBP N 


P87C52IBP N 


OTP 


to +70, Plastic Dual In-line Package 


24 


SOT129-1 


P80C32IBA A 


P87C52IBA A 


OTP 


to +70, Plastic Leaded Chip Carrier 


24 


SOT187-2 


P80C32IBB B 






to +70, Plastic Quad Flat Pack 


24 


SOT307-2 




P87C52IBF FA 


UV 


to +70, Ceramic Dual In-line Package 


24 


0590B 




P87C52IBL KA 


UV 


to +70, Ceramic Leaded Chip Carrier 


24 


1472A 


P80C32IFP N 


P87C52IFP N 


OTP 


-40 to +85, Plastic Dual In-line Package 


24 


SOT129-1 


P80C32IFA A 


P87C52IFA A 


OTP 


-40 to +85, Plastic Leaded Chip Carrier 


24 


SOT187-2 


P80C32IFB B 






-40 to +85, Plastic Quad Flat Pack 


24 


SOT307-2 














P87C52IFF FA 


UV 


-40 to +85, Ceramic Dual In-line Package 


24 


0590B 


P80C32NBA A 






to +70, Plastic Leaded Chip Carrier 


33 


SOT187-2 


P80C32NBP N 






to +70, Plastic Dual In-line Package 


33 


SOT129-1 


P80C32NBB B 






to +70, Plastic Quad Flat Pack 


33 


SOT307-2 


P80C32NFA A 






-40 to +85, Plastic Leaded Chip Carrier 


33 


SOT187-2 


P80C32NFP N 






-40 to +85, Pastic Dual In-line Package 


33 


SOT129-1 


P80C32NFB B 






-40 to +85, Plastic Quad Flat Pack 


33 


SOT307-2 



NOTE: 

1 . OTP = One Time Programmable EPROM. UV = UV erasable EPROM 

2. For 33MHz ROM 80C52 operation, see 80C52/80C54/80C58 data sheet. 




1996 Aug 16 



3-167 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80C32/87C52 



CERAMIC AND PLASTIC LEADED CHIP CARRIER 
PIN FUNCTIONS 




* DO NOT CONNECT 



PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 




Pin 


Function 


Pin 


Function 


Plr 


Function 


1 


P1.5 


16 


Vss 


31 


P0.6/AD6 


2 


P1.6 


17 


NC 


32 


P0.5/AD5 


3 


P1.7 


18 


P2.0/A8 


33 


P0.4/AD4 


4 
5 
6 

7 


RST 

RXD/P3.0 
NC- 

TXD/P3.1 


19 
20 
21 
22 


P2.1/A9 
P2.2/A10 
P2.3/A11 
P2.4/A12 


34 P0.3/AD3 

35 P0.2/AD2 

36 P0.1/AD1 

37 PO.O/ADO 


8 


IOTu7P3.2 


23 


P2.5/A13 


38 




S 


IHTT/P3.3 


24 


P2.6/A14 


39 




10 


T0/P3.4 


25 


P2.7/A15 


40 


T2/P1.0 


11 


T1/P3.5 


26 


P5EN 


41 


T2EX/P1.1 


12 


WR7P3.6 


27 


ALE/PROG 


42 


P1.2 


13 


HD7P3.7 


28 


NC* 


43 


PI.3 


14 


XTAL2 


29 


ESfl/pp 


44 


P1.4 


15 


XTAL1 


30 


P0.7/AD7 







• DO NOT CONNECT 



LOGIC SYMBOL 



Vcc v ss 



T 



RST 
ES/Vpp . 
P5ER . 
ALE/PROG* 

~RxD »• 

TxD« 

INTO — ► 

„ <*> 

IRTT — ► i- 
TO— »-§ 
T1— ► CL 

WR 



i 
> 

| 

SL'rd- 



ADDRESS AND 
DATA BUS 



- T2 
" T2EX 



ADDRESS BUS 



1996 Aug 16 



3-168 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 



80C32/87C52 



BLOCK DIAGRAM 



ru.u-ru.i ri.u-rt.i 



Vccj 

vssl 



PORTO 
DRIVERS 




PORT 2 
DRIVERS 


I 






"> <> 



7y 



H 1 



PORTO 




PORT 2 


LATCH 




LATCH 



I 



i: z 



POINTER 







TMP2 




TMP1 














ALU 



ALE' 
RST- 





Z 




Q a: 


TIMING 


£l 


AND 


INSTRU 
REGIE 


CONTROL 



PCON 


SCON 


TMOD 


TCON 


T2CON 


THO 


TLO 


TH1 


TL1 


TH2 


TL2 


RCAP2H 


RCAP2L 


SBUF 


IE 


IP 


INTERRUPT, SERIAL 
PORT AND TIMER BLOCKS 



7> <> 



PROGRAM A- 
ADDRESS V- 
REGISTER 



PC 
INCRE- 



PROGRAM 
COUNTER 



PORT 1 
LATCH 



|_XJAL1 



— IQI — ■ ■ 



I 



PORT 1 
DRIVERS 



JL 



DPTR ^> 



PORT 3 
LATCH 



PORT 3 
DRIVERS 



s — » -IMF- 











1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



Table 1 . 8XC52 Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 
MSB LSB 


RESET 
VALUE 


ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


00H 


B* 


B register 


FOH 


F7 


F6 


F5 


F4 


F3 


F2 


F1 


FO 


00H 


DPTR: 
DPH 
DPL 


Data pointer (2 bytes) 
Data pointer high 
Data pointer low 


83H 
82H 


















00H 
00H 








AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 




IE* 


Interrupt enable 


A8H 


EA 




ET2 


ES 


ET1 


EX1 


ETO 


EXO 


OxOOOOOOB 








BF 


BE 


BD 


BC 


BB 


BA 


B9 


B8 




IP* 


Interrupt priority 


B8H 




I " 


r 

PT2 


PS 


PT1 


PX1 


PTO 


PXO 


xxOOOOOOB 






8 ' 


86 


85 


84 


83 


82 


81 


80 




PO* 


PortO 


80H 


AD7 


AD6 


AD5 


AD4 


AD3 


AD2 


AD1 


ADO 


FFH 








97 


96 


95 


94 


93 


92 


91 


90 




P1* 


Port 1 


90H 


- 


- 


- 




- 


- 


T2EX 


T2 


FFH 








A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 




P2* 


Port 2 






















AOH 


A15 


A14 


A13 


A12 


A11 


A10 


A9 


A8 


FFH 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




P3* 


Port 3 


BOH 


HD 


WR 


T1 


TO 


1NTT 


INTO 


TxD 


RxD 


FFH 


PCON 1 


Power control 


87H 


SMOD 


- 


- 


- 


GF1 


GFO 


PD 


IDL 


flvvvvvYvR 








D7 


D6 


D5 


D4 


D3 


D2 








PSW* 


Program status word 


DOH 


CY 


AC 


FO 


RS1 


RSO 


OV 






00H 


RCAP2H# 
RCAPL# 


Capture high 
Capture low 


CBH 
CAH 


















00H 
00H 


SBUF 


Serial data buffer 


99H 


















xxxxxxxxB 








9F 


9E 


9D 


9C 


9B 


9A 


99 


98 




SCON* 


Serial controller 


98H 


SMO 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


00H 


SP 


Stack pointer 


81 H 


















07H 








8F 


8E 


8D 


8C 


8B 


8A 


89 


88 




TCON* 


Timer control 


88H 


TF1 


TR1 


TFO 


TRO 


IE1 


IT1 


IE0 


ITO 


00H 








CF 


CE 


CD 


cc 


CB 


CA 


C9 C8 




T2CON*# 


Timer 2 control 


C8H 


TF2 


EXF2 


RCLK 


TCLK 


EXEN2 


TR2 


C/T2 


CP/RT2 


00H 


THO 

TH1 

TH2# 

TLO 

TL1 

TL2# 


Timer high 
Timer high 1 
Timer high 2 
Timer low 
Timer low 1 
Timer low 2 


8CH 
8DH 
CDH 
8AH 
8BH 
CCH 




00H 
00H 
00H 
00H 
00H 
00H 


TMOD 


Timer mode 


89H 


GATE ] 


en \ 


M1 | 


MO | 


GATE 


C/T | 


M1 


MO 


00H 



* Bit addressable 

# SFRs are modified from or added to the 80C51 SFRs. 

1 . Bits GF1 , GFO, PD, and IDL of the PCON register are not implemented in the NMOS 8XC52. 



1996 Aug 16 



3-170 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



PIN DESCRIPTION 






PIN NO. 






MNEMONIC 


DIP 


i r*r* 




TYPE 


NAME AND FUNCTION 


Vee 
V SS 


20 


22 


16 


I 


Ground: 0V reference. 


Vcc 


40 


44 


38 


I 


Power Supply: This is the power supply voltage for normal, idle, and power-down 
operation. 












PO.0-0.7 


39-32 


43-36 


37-30 


I/O 


Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to 
them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data memory. In 
this application, it uses strong internal pull-ups when emitting 1 s. Port also outputs the 
code bytes during program verification in the 87C52. External pull-ups are required during 
program verification. 


P1.0-P1.7 


1-8 


2—9 


40—44 
1-3 


I/O 


Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As 
inputs, port 1 pins that are externally pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l !L ). Pins P1 .0 and P1 .1 also. Port 1 also 
receives the low-order address byte during program memory verification. Port 1 also serves 












alternate functions for timer 2: 

T2 (P1.0): Timer/counter 2 external count input. 




1 


2 


40 


I 




2 


3 


41 




T2EX (P1 .1 ): Timer/counter 2 trigger input. 


P2.0-P2.7 


21-28 


24—31 


18-25 


I/O 


Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As 
inputs, port 2 pins that are externally being pulled low will source current because of the 
internal pull-ups. (See DC Electrical Characteristics: l| L ). Port 2 emits the high-order 
address byte during fetches from external program memory and during accesses to 
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it 
uses strong internal pull-ups when emitting 1s. During accesses to external data memory 
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function 
register. 


P3.0-P3.7 


10-17 


11, 
13-19 


5, 
7-13 


I/O 


Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As 
inputs, port 3 pins that are externally being pulled low will source current because of the 
pull-ups. (See DC Electrical Characteristics: l| L ). Port 3 also serves the special features of 
the 80C51 family, as listed below: 




10 


11 


5 


I 


RxD (P3.0): Serial input port 




11 


13 


7 


o 


TxD (P3.1): Serial output port 




12 


14 


8 


I 


INTO (P3.2): External interrupt 




13 


15 


9 


I. 


IHTT (P3.3): External interrupt 




14 


16 


10 


I 


TO (P3.4): Timer external input 




15 


17 


11 


I 


T1 (P3.5): Timer 1 external input 




16 


18 


12 


o 


WR (P3.6): External data memory write strobe 




17 


19 


13 





RTJ (P3.7): External data memory read strobe 


RST 


9 


10 


4 


I 


Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to V ss permits a power-on reset using only an external 
capacitor to Vco 


ALE/PROG 


30 


33 


27 


I/O 


Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the 
address during an access to external memory. In normal operation, ALE is emitted at a 
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. 
Note that one ALE pulse is skipped during each access to external data memory. This pin is 
also the program pulse input (PROG) during EPROM programming. 


PSEN 


29 


32 


26 


o 


Program Store Enable: The read strobe to extemalprogram memory. When the device is 
executing code from the external program memory, PSEN is activated twice each machine 






















cycle, except that two PSEN activations are skipped during each access to external data 












memory. PSEN is not activated during fetches from internal program memory. 


EAWpp 


31 


35 


29 




External Access Enable/Programming Supply Voltage: EA must be externally held low 
to enable the device to fetch code from external program memory locations 0000H to 
1 FFFH. If ES is held high, the device executes from internal program memory unless the 
program counter contains an address greater than 1 FFFH. This pin also receives the 
12.75V programming supply voltage (Vpp) during EPROM programming. 


XTAL1 


19 


21 


15 


I 


Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 


XTAL2 


18 


20 


14 


o 


Crystal 2: Output from the inverting oscillator amplifier. 



1996 Aug 16 



3-171 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



DIFFERENCES FROM THE 80C51 
Special Function Registers 

The special function register space is the same as the 80C51 except 
that the 80C32/87C52 contains the additional special function 
registers T2CON, RCAP2L, RCAP2H, TL2, and TH2. Since the 
standard 80C51 on-chip functions are identical in the 8XC52, the 
SFR locations, bit locations, and operation are likewise identical. 
The only exceptions are in the interrupt mode and interrupt priority 
SFRs (see Table 1). 

Timer/Counters 

In addition to timer/counters and 1 of the 80C51 , the 80C32/87C52 
contains timer/counter 2. Like timers and 1 , timer 2 can operate as 
either an event timer or as an event counter. This is selected by bit 
C/T2 in the special function register T2CON (see Figure 1). It has 
three operating modes: capture, auto-load, and baud rate generator, 
which are selected by bits in the T2CON as shown in Table 2. 

In the Capture Mode there are two options which are selected by bit 
EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 1 6-bit timer or 
counter which upon overflowing sets bit TF2, the Timer 2 overflow 
bit, which can be used to generate an interrupt. If EXEN2 = 1 , then 
Timer 2 still does the above, but with the added feature that a 1-to-0 
transition at external input T2EX causes the current value in the 
Timer 2 registers, TL2 and TH2, to be captured into registers 
RCAP2L and RCAP2H, respectively. (RCAP2L and RCAP2H are 
new special function registers in the 80C52.) In addition, the 
transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 
like TF2 can generate an interrupt. The Capture Mode is illustrated 
in Figure 2. 

In the auto-reload mode, there are again two options, which are 
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 
rolls over it not only sets TF2 but also causes the Timer 2 registers 
to be reloaded with the 16-bit value in registers RCAP2L and 
RCAP2H, which are preset by software. If EXEN2 = 1 , then Timer 2 
still does the above, but with the added feature that a 1-to-0 



transition at external input T2EX will also trigger the 1 6-bit reload 
and set EXF2. The auto-reload mode is illustrated in Figure 3. 

The baud rate generation mode is selected by RCLK = 1 and/or 
TCLK = 1 . It will be describ 



except 



80C51 



Serial Port 

The serial port of the 8XC52 is identical to that of the 
that counter/timer 2 can be used to generate baud rates. 

In the 8XC52, Timer 2 is selected as the baud rate generator by 
setting TCLK and/or RCLK in T2CON (see Figure 1 ). Note that the 
baud rate for transmit and receive can be simultaneously different. 
Setting RCLK and/or TCLK puts Timer into its baud rate generator 
mode, as shown in Figure 4. 

The baud rate generator mode is similar to the auto-reload mode, in 
that a rollover in TH2 causes the Timer 2 registers to be reloaded 
with the 16-bit value in registers RCAP2H and RCAP2L, which are 
preset by software. 

Now, the baud rates in Modes 1 and 3 are determined by Timer 2's 
overflow rate as follows: 

Modes 1, 3 Baud Rate = 

The timer can be configured for either "timer" or "counter" operation. 
In the most typical applications, it is configured for "timer" operation 
(C/T2 = 0). Timer" operation is a little different for Timer 2 when it's 
being used as a baud rate generator. Normally, as a timer it would 
increment every machine cycle (thus at 1/12 the oscillator 
frequency). As a baud rate generator, however, it increments every 
state time (thus at 1/2 the oscillator frequency). In that case the 
baud rate is given by the formula: 

, „ ' . _ Oscillator Frequency 

Modes 1, 3 Baud Rate = 32 x [6S536 _ (RCAP2H , RC AP2L)] 

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L 
taken as a 16-bit unsigned integer. 



TF2 


EXF2 


RCLK 


TCLK 


EXEN2 


TR2 


C/TZ 


CP/BI3 



TF2 


T2CON.7 


EXF2 


T2CON.6 


RCLK 


T2CON.5 


TCLK 


T2CON.4 


EXEN2 


T2CON.3 


TR2 


T2CON.2 


cm 


T2CON.1 


CP/RT2 


T2CON.0 



Timer 2 overflow flag sel by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1 . 

Timer 2 externa! flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 
interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. 

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 
causes Timer 1 overflow to be used for the receive clock. 

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 
causes Timer 1 overflows to be used for the transmit clock. 

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not 
being used to clock the serial port. EXEN2 = causes Timer 2 to ignore events at T2EX. 

Start/stop control for Timer 2. A logic 1 starts the timer. 

Timer or counter select. (Timer 2) 

= Internal timer (OSC/12) 

1 = External event counter (falling edge triggered). 

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1 . When 
occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1 . When either RCLK = 1 
d and the timer is forced to auto-reload on Timer 2 overflow. 




Figure 1 . Timer/Counter 2 (T2CON) Control Register 



1996 Aug 16 



3-172 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



osc 




♦ 12 





C/T5 = 

■o 




— 




TL2 


TH2 












mm 


(8-bits) 

















Transition 
Detector 



7,12 Capture 



-o-~i"*o— 







RCAP2L 


RCAP2H 



-Eh 



Tuner 2 
Interrupt 



Figure 2. Timer 2 in Capture Mode 




T2PIN 



C/T5.1 







TL2 
(8-BITS) 


TH2 


(8-BITS) 




EXEN2 



















T2EXPIN » 












EXF2 























RCAP2L 


RCAP2H 



i 



Figure 3. Timer 2 in Auto-Reload Mode 



1996 Aug 16 



3-173 



Philips Semiconductors 



rroauci specincauon 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



Timer 1 



NOTE: OSC. Freq. is divided by 2. not 12. 




TL2 


TH2 


(8-bits) 


(8-bits) 



■0- b 




SMOD 
RCLK 



. TCLK 

►EH 



Figure 4. Timer 2 in Baud Rate Generator Mode 



Table 2. Timer 2 Operating Modes 



RCLK + TCLK 


CP/RT2 


TR2 


MODE 








1 


16-bit Auto-reload 





1 


1 


16-bit Capture 


1 


X 


1 


Baud rate generator 


X 


X 





(off) 



Timer 2 as a baud rate generator is shown in Figure 4. This figure is 
valid only if RCLK + TCLK = 1 in T2CON. Note that a rollover in TH2 
does not set TF2, and will not generate an interrupt. Therefore, the 
Timer 2 interrupt does not have to be disabled when Timer 2 is in 
the baud rate generator mode. Note too, that if EXEN2 is set, a 
1-to-0 transition in T2EX will set EXF2 but will not cause a reload 
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in 
use as a baud rate generator, T2EX can be used as an extra 
external interrupt, if desired. 

It should be noted that when Timer 2 is running (TR2 = 1) in "timer" 
function in the baud rate generator mode, one should not try to read 
or write TH2 or TL2. Under these conditions the timer is being 
incremented every state time, and the results of a read or write may 
not be accurate. The RCAP registers may be read, but should not 
be written to, because a write might overlap a reload and cause 
write and/or reload errors. Turn the timer off (clear TR2) before 
accessing the Timer 2 or RCAP registers, in this case. 



Timer/Counter 2 Set-up 

Except for the baud rate generator mode, the values given for 
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 
must be set, separately, to turn the timer on. See Table 3 for set-up 
of timer 2 as a timer. See Table 4 for set-up of timer 2 as a counter. 

Using Timer/Counter 2 to Generate Baud Rates 

For this purpose, Timer 2 must be used in the baud rate generating 
mode. If Timer 2 is being clocked through pin T2 (P1 .0) the baud 
rate is: 



Timer 2 Overflow Rate 
16 



Baud Rate < 

And if it is being clocked internally, the baud rate is: 
Baud Rate 



Oscillator Frequency 



32 x [65536 - (RCAP2H, RCAP2L)] 

To obtain the reload value for RCAP2H and RCA02L. the above 
equation can be rewritten as: 



RCAP2H, RCAP2L = 65536 



Oscillator Frequency 
32 x Baud Rate 



1996 Aug 16 



3-174 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



Interrupts 

The 80C32/87C52 has 6 interrupt sources. All except TF2 and EXF2 
are identical sources to those in the 80C51 . 

The Interrupt Enable Register and the Interrupt Priority Register are 
modified to include the additional 80C32/87C52 interrupt sources. 
The operation of these registers is identical to the 80C51 . 

In the 80C32/87C52, the Timer 2 Interrupt is generated by the 
logical OR of TF2 and EXF2. Neither of these flags is cleared by 
hardware when the service routine is vectored to. In fact, the service 
routine may have to determine whether it was TF2 or EXF2 that 
generated the interrupt, and the bit will have to be cleared in 



by hardware. That is, interrupts can be generated or pending 
interrupts can be canceled in software. 

The interrupt vector addresses and the interrupt priority for requests 
in the same priority level are given in the following: 



Source 

1. IE0 

2. TFO 

3. IE1 

4. TF1 

5. RI+TI 

6. TF2 + EXF2 



Vector Priority Within 
Address Level 



0003H 
000BH 
001 3H 
001 BH 
0023H 
002BH 



(highest) 
(lowest) 



All of the bits that generate interrupts can be set or cleared by 
software, with the same result as though it has been set or cleared 



Table 3. Timer 2 as a Timer 



Note that they are identical to those in the 80C51 except for the 
addition of the Timer 2 (TF1 and EXF2) interrupt at 002BH and at 
the lowest priority within a level. 



MODE 


T2CON 


INTERNAL CONTROL 
(Notel) 


EXTERNAL CONTROL 
(Note 2) 


16-bit Auto-Reload 


00H 


08H 


1 6-bit Capture 




01H 


09H 


Baud rate generator receive and transmit same baud rate 


34H 


36H 


Receive only 


24H 


26H 


Transmit only 


14H 


16H 


Table 4. Timer 2 as a Counter 


MODE 


TMOD 


INTERNAL CONTROL 
(Notel) 


EXTERNAL CONTROL 
(Note 2) 


16-bit 


02H 


OAH 


Auto-Reload 


03H 


OBH 



NOTES: 

1 . Capture/reload occurs only on timer/counter overflow. 

2. Capture/reload occurs on timer/counter overflow and a 1 -to-0 transition on T2EX (P1 .1 ) pin except when timer 2 is used in the baud rate 
generator mode. 



1996 Aug 16 



Product specification 



CMOS single-chip 8-bit microcontrollers 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 
oscillator, as shown in the Logic Symbol, page 3-168. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements 
on the duty cycle of the external clock signal, because the input to 
the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 

RESET 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-up reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. 

IDLE MODE 

In idle mode, the CPU puts itself to sleep while all of the on-chip 
peripherals stay active. The instruction to invoke the idle mode is the 
last instruction executed in the normal operating mode before the 
idle mode is activated. The CPU contents, the on-chip RAM, and all 



of the special function registers remain intact during this mode. The 
idle mode can be terminated either by any enabled interrupt (at 
which time the process is picked up at the interrupt service routine 
and continued), or by a hardware reset which starts the processor in 
the same manner as a power-on reset. 



POWER-DOWN MODE 

In the power-down mode, the oscillator is stopped and the 
instruction to invoke power-down is the last instruction executed. 
Only the contents of the on-chip RAM are preserved. A hardware 
reset is the only way to terminate the power-down mode, the control 
bits for the reduced power modes are in the special function register 
PCON. 

DESIGN CONSIDERATIONS 

At power-on, the voltage on V oc and RST must come up at the 
same time for a proper start-up. 

Table 5 shows the state of I/O ports during low current operating 
modes. 

As a precaution to coming out of an unexpected power down, INTO 
and INT1 should be disabled prior to enterring power down. 



Table 5. External Pin Status During Idle and Power-Down Modes 



MODE 


PROGRAM MEMORY 


ALE 


PEER 


PORT 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 




Internal 








Data 


Data 


Data 


Data 














Power-down 


External 








Float 


Data 


Data 


Data 









1996 Aug 16 



3-176 



Philips Semiconductors ^ Product specification 

CMOS single-chip 8-bit microcontrollers 80C32/87C52 



Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C52) 

DC and AC parameters not included here are the same as in the commercial temperature range table. 



DC ELECTRICAL CHARACTERISTICS 

Tamb = -40°C to +85°C, V CC = 5V ±1 0%, V ss = 0V 


SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


MAX 


V|L 


Input low voltage, except EA~ 




-0.5 


0.2V CC -0.15 


V 








VlLI 


Input low voltage to EA" 







0.2V cc -0.35 


V 


VlH 


Input high voltage, except XTAL1 , RST 




0.2V CC +1 


Vcc+0.5 


V 


V|H1 


Input high voltage to XTAL1 , RST 




0.7V C c+0.1 


Vcc+0.5 


V 


l|L 


Logical input current, ports 1 , 2, 3 


V IN = 0.45V 




-75 


uA 












In. 


Logical 1 -to-0 transition current, ports 1 , 2, 3 


V, N £ 2.0V 




-750 


HA 


ice 


Power supply current: 
Active mode 
Idle mode 
Power-down mode 


V 0C = 4.5-5.5V, 




32 
5 
50 


mA 
mA 
uA 


ABSOLUTE MAXIMUM RATINGS' z 3 


PARAMETER 


RATING 


UNIT 


Operating temperature under bias 


to +70 or -40 to +85 


°C 


Storage temperature range 




-65 to +150 


°C 


Voltage on EATVpp pin to Vss 


to +13.0 


V 








Voltage on any other pin to Vss 


-0.5 to +6.5 


V 


Maximum Iol per i/O pin 




mA 


Power dissipation (based on package heat transfer limitations, not 
device power consumption) 


1.5 


W 



NOTES: 



1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vss unless otherwise 
noted. 

■ 



1996 Aug 16 



3-177 



Philips Semiconductors 



Product specification 



i 8-bit microcontrollers 80C32/87C52 



DC ELECTRICAL CHARACTERISTICS 

Tamb = °°C to +70°C or -40°C to +85°C, V cc = 5V ±1 0%, V ss = 0V (87C52) 
Tamb = 0°C to +70°C or -40°C to +85°C, V cc = 5V ±1 0%, V SS = 0V (80C32) 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 


Vil 


Input low voltage, except EA 7 




-0.5 




0.2V CC -0.1 


V 


V|L1 


Input low voltage to EA' 









0.2V cc -0.3 


V 


VlH 


Input high voltage, except XTAL1, RST 7 




0.2V cc +0.9 




Vcc+0.5 


V 


V|H1 


Input high voltage, XTAL1 , RST 7 




0.7V CC 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1, 2, 3 9 


l OL = 1.6mA 2 






0.45 


V 


Von 


Output low voltage, port 0, ALE, PSEN 9 


I l = 3.2mA 2 






0.45 


V 


Voh 


Output high volt 


age, ports 1 , 2, 3, ALE, PSEN J 


Ioh = -60|iA, 
I h = -25uA 


2.4 
0.75Vcc 






V 
V 
V 






l OH = -10uA 


0.9V CC 




Vom 


Output high volt 


ige (port in external bus mode) 


lOH = -800nA, 
l H = -300jiA 
Ioh = -80nA 


2.4 
0.75V CC 
0.9V CC 






V 
V 
V 


IlL 


Logical input current, ports 1 , 2, 3 7 


V| N = 0.45V 






-50 


uA 


Itl 


Logical 1 -to-0 transition current, ports 1 , 2, 3 7 


See note 4 






-650 


HA 


lu 


Input leakage current, port 


Vin = V| L or V| H 






±10 


HA 


ice 


Active mode @ 16MHz 5 
Idle mode @ 16MHz 


See note 6 




11.5 
1.3 


32 
5 








mA 
mA 




Power-down mode Tamb = to 70°C 

Tamb = -40 to +85°C 






3 


50 
75 


HA 
|tf 


R RST 


Internal reset pull-down resistor 




50 




300 


kO 


ClO 


Pin capacitance 10 








15 


PF 



NOTES: 



1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the Vols of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I l can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs exceed the test conditions. 

3. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the 0.9V C c specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 

5 - 'ccmax at other frequencies is given by: Active mode: Iccmax = 1 .5 x FREQ + 8.0: Idle mode: Iqcmax = 0. 1 4 x FREQ +2.31 , 
where FREQ is the external oscillator frequency in MHz. I CC max is given in mA. See Figure 12. 

6. See Figures 13 through 16 for Ice test conditions. 

7. These values apply only to T amb = 0°C to +70°C. For T^ = -40°C to +85°C, see table on previous page. 

8. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

9. Under steady state (non-transient) conditions, Iol must be externally limited as follows: 

Maximum Iql per port pin: 1 5mA ('NOTE: This is 85°C specification.) 

Maximum Iol per 8-bit port: 26mA 

Maximum total Iol for all outputs: 67mA 
If Iol exceeds the test condition, Vol may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

1 0. This limit is for plastic packages. For ceramic packages, the maximum limit is 20pF. 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to +85°C, V cc = 5V ±10%, V S s = °V (87C52) 1 ' 2 - 3 



QYMROL 

O I IVIUUL 


FIGURE 




16MHz CLOCK 


VARIABLE CLOCK 


UNIT 


PARAMETER 


MIN 


MAX 


MIN 


MAX 


1/t CLCL 


5 


Oscillator frequency 
Speed versions : E 






3.5 


16 


MHz 


'lhll 


5 


ALE pulse width 


85 




2tcLCL-40 




ns 


Iavll 


5 


Address valid to ALE low 


22 




tCLCL-40 




ns 


tLLAX 


5 


Address hold after ALE low 


32 




tCLCL-30 




ns 


*ujv 


5 


ALE low to valid instruction in 




150 




-"CLCL-100 


ns 


tLLPL 


5 


ALE low to PSEN low 


32 




tcLCL-30 




ns 


'PLPH 


5 


PSEN pulse width 


142 




SICLCL-^S 




ns 


tPLIV 


5 


PSEN low to valid instruction in 




82 




3tcLCL-105 


ns 


tpxix 


5 


Input instruction hold after PSEN 












ns 


tpxiz 


5 


Input instruction float after PSEN 




37 




tcLCL-25 


ns 


WlV 


5 


Address to valid instruction in 




207 




5tcLCL-105 


ns 


tpLAZ 


5 


PSEN low to address float 




10 




10 


ns 


Data Memory 


tRLRH 


6,7 


RD~ pulse width 


275 




6tcLCL-100 




ns 


twLWH 


6,7 


WR pulse width 


275 




etcLCL-100 




ns 


•rldv 


6,7 


RD" low to valid data in 




147 




5tcLCL - 1 65 


ns 


Irhdx 


6, 7 


Data hold after RD 












ns 


'rhdz 


6,7 


Data float after RD 




65 




2tcLCL-60 


ns 


'lldv 


6,7 


ALE low to valid data in 




350 




Siclcl-150 


ns 


'avdv 


6, 7 


Address to valid data in 




397 




91CLCL-165 


ns 


'llwl 


6,7 


ALE low to RD or WR low 


137 


239 


3tcLCL-50 


3tcLCL+50 


ns 


'aVWL 


6,7 


Address valid to WR low or RD low 


122 




4tcLCL-130 




ns 


<QVWX 


6,7 


Data valid to WR transition 


13 




tCLCL-50 




ns 


tWHQX 


6,7 


Data hold after WR 


13 




tcLCL-50 




ns 


tQVWH 


7 


Data valid to WR high 


287 




7tc.cL.-1 50 




ns 


'rlaz 


6, 7 


R0 low to address float 












ns 


'WHLH 


6.7 


RD or WR high to ALE high 


23 


103 


tcLCL-^0 


tCLCL+40 


ns 


External Clock 


•cHCX 


9 


High time 


20 




20 


•CLCL-ICLCX 


ns 


tCLCX 


9 


Low time 


20 




20 


tCLCL-tCHCX 


ns 


tCLCH 


9 


Rise time 




20 




20 


ns 


'CHCL 


9 


Fall time 




20 




20 


ns 


Shift Register 


'XLXL 


8 


Serial port clock cycle time 


750 




1 2t CLCL 




ns 


*QVXH 


8 


Output data setup to clock rising edge 


492 




10tcLCL-133 




ns 


•XHQX 


8 


Output data hold after clock rising edge 


8 




2tcLCL"117 




ns 


'XHDX 


8 


input data hold after clock rising edge 












ns 


<XHDV 


8 


Clock rising edge to input data valid 




492 




10tcLCL-133 


ns 



NOTES: 



1 . Parameters are valid over operating temperature range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. See application note AN457 for external memory interface. 



1996 Aug 16 



3-179 



Product specification 




microcontrollers 80C32/87C52 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70-C or -40°C to +85°C, V CC = 5V ±1 0%, V ss = 0V 1 ■ 2 - 3 



SYMBOL 






24MHz CLOCK 


VARIABLE CLOCK 


33MHz CLOCK 


UNIT 


FIGURE 


PARAMETER 


MIN 


MAX 


MIN 


MAX 


MIN 


MAX 


1/tCLCL 


5 


Oscillator frequency 

Speed versions : I 

: N 






3 5 


24 


3.5 


33 


MHz 


'lhll 


5 


ALE pulse width 


43 




2tcLCL-^0 




21 




ns 


tAVLL 


5 


Address valid to ALE low 


17 




tcLCL- 25 




5 




ns 


tl_LAX 


5 


Address hold after ALE low 


17 




tcLCL-25 




5 




ns 


t|_LIV 


5 


ALE low to valid instruction in 




102 




4tci_CL-65 




56 


ns 


<LLPL 


5 


ALE low to PSEN low 


17 




tcLCL- 25 




5 




ns 


tpLPH 


5 


PSEN pulse width 


80 




3tci_CL-45 






46 


ns 


tpLIV 


5 


PSEN low to valid instruction in 




65 




3t C LCL-60 




31 


ns 


tpxix 


5 


Input instruction hold after PSEN 

















ns 


•pxiz 


5 


Input instruction float after PSEN 




17 




tci_CL-25 




5 


ns 


*AVIV 


5 


Address to valid instruction in 




128 




5tCLCL"80 




72 


ns 


•PLAZ 


5 


PSEN low to address float 




10 




10 




10 


ns 


Data Memory 


tRLRH 


6, 7 


RD pulse width 


150 




6tci_CL-100 




82 




ns 


'WLWH 


6,7 


WR pulse width 


150 




6tcLCL-100 




82 




ns 


tRLDV 


6, 7 


RD low to valid data in 




118 




5t CL CL-90 




62 


ns 


tRHDX 


6, 7 


Data hold after RD 

















ns 






















( RHDZ 


6, 7 


Data float after RD 




55 




2ICLCL-28 




33 


ns 


tLLDV 


6, 7 


ALE low to valid data in 




183 




8tcLCL-150 




92 


ns 


<AVDV 


6,7 


Address to valid data in 




210 




9tcLCL-165 




108 


ns 


'llwl 


6,7 


ALE low to RD or WR low 


75 


175 


3tci_CL-50 


3ICLCL+50 


41 


141 


ns 


Wwl 


6, 7 


Address valid to WR low or RD low 


92 




4t0LCL-75 




46 




ns 


Iqvwx 


6, 7 


Data valid to WR transition 


12 




tCLCL-30 




0.3 




ns 


twHQX 


6, 7 


Data hold after WR 


17 




tcLCL-25 




5 




ns 


tQVWH 


7 


Data valid to WR high 


162 




7tcLCL-130 




82 




ns 


<rlaz 


6,7 


RD low to address float 

















ns 


twHLH 


6, 7 


RD or WR high to ALE high 


17 


67 


tc L CL-25 


tCLCL+25 


5 


5 


ns 


External Clock 


'CHCX 


9 


High time 


17 




17 


tCLCL-tciCX 






ns 


tCLCX 


9 


Low time 


17 




17 


'CLCL-tCHCX 






ns 


•CLCH 


9 


Rise time 




5 




5 






ns 


tCHCL 


9 


Fall time 




5 




5 






ns 


Shift Register 


*XLXL 


8 


Serial port clock cycle time 


505 




12 toLCL 




363 




ns 


kavxH 


8 


Output data setup to clock rising edge 


283 




10tcLCL-133 




170 




ns 


l XHQX 


8 


Output data hold after clock rising edge 


3 




2tcLCL-80 




19 




ns 


*XHDX 


8 


Input data hold after clock rising edge 

















ns 


txHDV 


8 


Clock rising edge to input data valid 




283 




IOtcLCL-133 




170 


ns 



NOTES: 

1 . Parameters are valid over operating temperature range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 8XC52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port drivers. 

4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz,see 16MHz 
"AC Electrial Characteristics", page 3-179. 



1996 Aug 16 



3-180 



Product specification 



CMOS single-chip 8-bit microcontrollers 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 

T (= time). The other characters, depending on their positions, 

indicate the name of a signal or the logical status of that signal. The 

designations are: 

A - Address 

C - Clock 

D - Input data 

H - Logic level high 

I - Instruction (program memory contents) 
L - Logic level low, or ALE 



P - P5ETJ 
Q - Output data 
R - RTJ signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: t AVLL = Time for address va lid to A LE low. 
t LLPL = Time for ALE low to P5EN low. 



•lhll 



PORT 2 



zx 




y v 



fpLAZ 



WlV 



tpxix " 



- tpxiz— »• 



S > INSTR IN ^ ^ A0 ~ A7 



X 



Figure 5. External Program Memory Read Cycle 



RT5_ 



tAVLL 



>X 

zx 



r 



l LLDV 



'llwl 



*LLAX 



A0-A7 
FROM Rl OR DPL 



> 



,' RLA2 > 



t A VWL 



*RLRH 



' 'RLDV 



UVDV 



*RHDX " 



< 



<WHLH 



^ / 



*RHDZ. 



A0-A7 FROM PCL 



y 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 6. External Data Memory Read Cycle 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontroiiers 80C32/87C52 



« — 



Wll 



PORT \ / A0-A7 V' 

? \ FROM Rl OR DPL A, 

t A VWL 





/ \ / 

v N / 



Illax 



tWLWH 



\ I 

'qvwx 



tWHLH -*" 



X / 



twHQX 



XX 



A0-A7 FROM PCL. 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 









Figure 7. External Data Memory Write Cycle 



INSTRUCTION | | 1 | 2 | 3 | 4 | 5 | 6 7 | 8 

- JLJIJIJIJTJLJLJLJIJIJIJ^^ 



■ 



tQVXH 



OUTPUT DATA . 



"LJ-i_r 

|*~ tXHQX | 



"L_r-L_r-L_r 



WRITE TO SBUF 



^ 'XHDX 



txHDV 



SETTI 



f 

CLEAR Rl 



SET Rl 



SU00027 



Figure 8. Shift Register Mode Timing 



vcc-o-5 - - 

0.45V — : 



f- 0.7V OC 
0.2V CC -0.1 

*CHCL- 



^ r 



-topic* 

E tCLCL 



*-tCHCX-»- 
'CLCH 



Figure 9. External Clock Drive 



1996 Aug 16 



3-182 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



- 



vcc-o.5 



X0.2V CC *0.9 



NOTE: 

AC inputs during testing are driven at Vcc -0 5 'or a logk: T and 0.45V for a logic '0*. 
Timing measurements are made at V jH min for a logic T and V )L max for a logic '0'. 



Figure 10. AC Testing Input/Output 



VLOAD*"V 



vload 

vload-o.iv 



TIMING 
REFERENCE 
POINTS 



>: 



vqh-o.iv 



V L*01V 



Foxing putposes, a pon * no longer ftoating when a , OOmV change trom toad voltage cecum, 
and begins to float when a 100mV change from the loaded Voh/Vol level occurs. IohOol s ±20mA. 



Figure 1 1 . Float Waveform 




4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 
FREQ AT XTAL1 



Figure 12. I cc vs. FREQ 
Valid only within frequency specifications of the device under t 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



v C c 

u 



(NCI- 
CLOCK SIGNAL - 





VCC 


RST 


PO 




EA" 


XTAL2 




XTAL1 




Vss 



ice 



Voc 



Figure 13. Ice Test Condition, Active Mode 
All other pins are disconnected 




Vcc 



CLOCK SIGNAL - 



It 





Vcc 


RST 






PO 




EA 


XTAL2 




XTALI 




Vss 





11 



Figure 14. Ice Test Condition, Idle Mode 
All other pins are disconnected 





•CLCL 



Figure 15. Clock Signal Waveform for l cc Tests in Active t 
•clch = *chcl = 5ns 





Vcc 


RST 






PO 




EA 


XTAL2 




XTALI 




vss 





suooow 



Figure 16. l C c Test Condition, Power Down Mode 
All other pins are disconnected. V cc = 2V to 5.5V 



1996 Aug 16 



3-184 



Philips Semiconductors Product specification 

CMOS single-chip 8-bit microcontrollers 80C32/87C52 



EPROM CHARACTERISTICS 

The 87C52 is programmed by using a modified Quick-Pulse 
Programming™ algorithm. It differs from older methods in the value 
used for V PP (programming supply voltage) and in the width and 
number of the ALE/PROG pulses. 

The 87C52 contains two signature bytes that can be read and used 
by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87C52 manufactured by 

Table 6 shows the logic levels for reading the signature byte, and for 
programming the program memory, the encryption table, and the 
security bits. The circuit configuration and waveforms for quick-pulse 
programming are shown in Figures 1 7 and 1 8. Figure 1 9 shows the 
circuit configuration for normal program r 



igure 1 9 sho 
verification. 



Quick-Pulse Programming 

The setup for microcontroller quick-pulse programming is shown in 
Figure 1 7. Note that the 87C52 is running with a 4 to 6MHz 
oscillator. The reason the oscillator needs to be running is that the 
device is executing internal address and program data transfers. 

The address of the EPROM location to be programmed is applied to 
ports 1 and 2, as shown in Figure 1 7. The code byte to be 
programmed into that location is applied to port 0. RST, PSEN and 
pins of ports 2 and 3 specified in Table 6 are hel d at the 'Program 
Code Data' levels indicated in Table 6. The ALE/FRU5 is pulsed 
low 25 times as shown in Figure 1 8. 

To program the encryption table, repeat the 25 pulse programming 
sequence for addresses through 1 FH, using the 'Pgm Encryption 
Table' levels. Do not forget that after the encryption table is 
programmed, verification cycles will produce only encrypted data. 

To program the security bits, repeat the 25 pulse programming 
sequence using the 'Pgm Security Bit' levels. After one security bit is 
programmed, further programming of the code memory and 
encryption table is disabled. However, the other security bit can still 
be programmed. 

Note that the EA7V PP pin must not be allowed to go above the 
maximum specified V PP level for any amount of time. Even a narrow 
glitch above that voltage can cause permanent damage to the 
device. The V PP source should be well regulated and free of glitches 
and overshoot. 



Program Verification 

If security bit 2 has not been programmed, the on-chip program 
memory can be read out for program verification. The address of the 
program memory locations to be read is applied to ports 1 and 2 as 
shown in Figure 1 9. The other pins are held at the 'Verify Code Data' 
levels indicated in Table 6. The contents of the address location will 
be emitted on port 0. External pull-ups are required on port for this 
operation. 

If the encryption table has been programmed, the data presented at 
port will be the exclusive NOR of the program byte with one of the 
encryption bytes. The user will have to know the encryption table 
contents in order to correctly decode the verification data. The 
encryption table itself cannot be read out. 

Reading the Signature Bytes 

The signature bytes are read by the same procedure as a normal 
verification of locations 030H and 031 H, except that P3.6 and P3.7 
need to be pulled to a logic low. The values are: 
(030H) = 15H indicates manufactured by Philips 
(031 H) = 97H indicates 87C52 

Program/Verify Algorithms 

Any algorithm in agreement with the conditions listed in Table 6, and 
which satisfies the timing specifications, is suitable. 

Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is exposed to 
light with wavelengths shorter than approximately 4,000 angstroms. 
Since sunlight and fluorescent lighting have wavelengths in this 
range, exposure to these light sources over an extended time (about 
1 week in sunlight, or 3 years in room level fluorescent lighting) 
could cause inadvertent erasure. For this and secondary effects, 
it is recommended that an opaque label be placed over the 
window. For elevated temperature or environments where solvents 
are being used, apply Kapton tape Fluorglas part number 2345-5, or 
equivalent. 

The recommended erasure procedure is exposure to ultraviolet light 
(at 2537 angstroms) to an integrated dose of at least 15W-s/cm 2 . 
Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm 2 rating 
for 20 to 39 minutes, at a distance of about 1 inch, should be 
sufficient. 

Erasure leaves the array in an all 1s state. 



Table 6. EPROM Programming Modes 



MODE 


RST 


PSEN 


ALE/PROG 


ES/Vpp 


P2.7 


P2.6 


P3.7 


P3.6 


Read signature 


1 





1 


1 














Program code data 


1 





0* 


v PP 


1 





1 




Verify code data 


1 





1 


1 








1 


1 


Pgm encryption table 


1 





0* 


V PP 


1 





1 





Pgm security bit 1 


1 





0* 


V PP 


1 


1 


1 


1 


Pgm security bit 2 


1 





0* 


v PP 


1 


1 









NOTES: 

1. '0' = Valid low for that pin, T= valid high for that pin. 

2. V PP = 12.75V +0.25V. 

3. Vcc = 5V±10 % during programming and verification. 

4. "ALE/PROG receives 25 programming pulses while V PP is held at 12.75V. Each programming pulse is low for 100ns (±10(is) and high for a 
minimum of 10ns. 



'"Trademark phrase of Intel Corporation. 



1996 Aug 16 



3-185 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C32/87C52 



AO-A7 



v 



I 2^ 

4-6MHZ □ 



P1 

HST 

P3.6 

P3.7 

XTAL2 

XTAL1 

vss 



vcc 

PO 

ESA/pp 
ALE/PROG 
87C52 F5EN 
P2.7 
P2.6 



P2.0-P2.4 



PGM DATA 



A- 

— +12.75V 

— 25 100ns PULSES TO GROUND 

— 

— 1 

o 

~~ A8-A12 



A~ 



Figure 17. Programming Configuration 



^LTLrLTLrL, ~L_rLru-i_rLr 



10ns MIN 



ALE/PROG: 





n 



— 







Figure 18. PROG Waveform 



AO-A7 



- ■ - 



V 



pi 

RST 
P3.6 
P3.7 
XTAL2 

XTAL1 

vss 



vcc 

PO 

EAWpp 
ALE/PROG 
B7C52 P5EN 



/L 

P2.0-P2.4 



9 





ENABLE 



Figure 19. Program Verification 



1996 Aug 16 



3-186 



Philips Semiconductors 



Product specification 





CMOS single-chip 8-bit microcontrollers 



EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS 

Tamb = 21 °C to +27°C, V cc = 5V±10%, V ss = OV (See Figure 20) 



SYMBOL 


PARAMETER 


MIN 


MAX 


UNIT 


V PP 


Programming supply voltage 


12.5 


13.0 


V 


Ipp 


Programming supply current 




50 


mA 


1/tcLCL 


Oscillator frequency 


4 


6 


MHz 


Wql 


Address setup to PROG low 


48tcLCL 






*GHAX 


Address hold after PROG 


48tcLCL 






<DVGL 


Data setup to PROG low 


48tcLCL 






*GHDX 


Data hold after PROG 


48to LC L 






tEHSH 


P2.7 (ENABLE) high to V PP 


48tcLCL 






*SHGL 


Vp P setup to PROG low 


10 






•ghsl 


V PP hold after PROG 


10 




us 


tGLGH 


PROG width 


90 


110 


Its 


*AVQV 


Address to data valid 




48tcLCL 




<elqz 


ENABLE low to data valid 




48to LCL 




•ehqz 


Data float after ENABLE 





48tcLCL 




*GHGL 


PROG high to PROG low 


10 




US 



P1.0-P1.7 
P2.0-P2.4 



< 



ALE/FW35 



Idvgl 
'avgl 



programming* 



> 



< DATA IN ^ 



*glgh 

'SHGL 



EAWpp 



tEHSH 



< 



VERIFICATION 



> 



<: 



tGHDX 

Ighax 



•ghgl 



Ighsl 



'elqv Y~* 



'avqv 



> 







•ehqz 



NOTE: 

* FOR PROGRAMMING VERIFICATION SEE FIGURE 17. 
FOR VERIFICATION CONDITIONS SEE FIGURE 19. 

Figure 20. EPROM Programming and 



1996 Aug 16 



3-187 



Philips Semiconductors 



Product specification 



lip 8-bit microcontrollers 



DESCRIPTION 

The 80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller is 
manufactured in an advanced CMOS process and is a derivative of 
the 80C51 microcontroller family. The 80C52/80C54/80C58 has the 
same instruction set as the 80C51 . 

This device provides architectural enhancements that make it 
applicable in a variety of applications for general control systems. 
The 80C52 contains 8k x 8 ROM memory, the 80C54 contains 
16k x 8 ROM memory, and 80C58 contains 32k x 8 ROM memory, a 
volatile 256 x 8 read/write data memory, four 8-bit I/O ports, three 
16-bit timer/event counters, a multi-source, four-priority-level, nested 
interrupt structure, an enhanced UART and on-chip oscillator and 
timing circuits. For systems that require extra capability, the 



PIN CONFIGURATIONS 



i logic. 

Its added features make it an even more powerful microcontroller for 
applications that require pulse width modulation, high-speed I/O and 
up/down counting capabilities such as motor control. It also has a 
more versatile serial channel that facilitates multiprocessor 
communications. 

See 87C52/80C32 and 87C54/87C58 data sheets for EPROM and 
ROMIess devices. 



FEATURES 

• 80C51 central processing unit 

• Full static operation 

• 8k x 8 ROM: 80C52; 
16kx8ROM:80C54; 
32k x 8 ROM: 80C58; 

all capable of addressing external memory to 64k bytes 

- Two level program security system 

- 64 byte encryption array 

• 256 x 8 RAM, expandable externally to 64k bytes 

• Speed range up to 33MHz 

• Operating voltage 5V +1 0% 

• Three 16-bit timer/counters 

- T2 is an up/down counter 

• 6 interrupt sources 

• 4 level priority 

• Four 8-bit I/O ports 

• Full-duplex enhanced UART 

- Framing error detection 

- Automatic address recognition 

• Power control modes 

- Idle mode 

- Power-down mode 

• Once (On Circuit Emulation) Mode 

• Five package styles 

• Programmable clock out 

• Low EMI (Inhibit ALE) 

• Second DPTR register 

• Asynchronous port reset 



T2/P1.0[T 
T2EX/P1.l[T 

dig 

P1.3[7 
P1.4[jf 
PI. 5 [6 
P1.6[7 
P1.7[? 

rst[T 

RxD/P3.oQo 
TxD/P3.lQT 
IRTOP3.2Q2 
rFJTT/P3.3[t3 
T(VP3.4[M 
TI/P3.5Q5 
WR7P3.6Q6 
HD7P3.7Q7 
XTAL2Q| 
XTAL1 [li 
V S s[20 



DUAL 
IN-LINE 
PACKAGE 



39] P0.0/AD0 
38] P0.1/AD1 
37] P0.2/AD2 
36] P0.3/AD3 
35] P0.4/AD4 
34] P0.5/ADS 
33] P0.6/AD6 
55] P0.7/AD7 
3l] ES 
3<j] ALE 
29] PEER 
5i] P2.7/A15 
27] P2.6/A14 
26] P2.5/A13 
25] P2.4/A12 
24] P2.3/A11 
23| P2.2/A10 
|i] P2.1/A9 
2l] P2.Q/A8 



1996 Aug 16 



3-188 



853-1470 17196 



Philips Semiconductors 



Product specification 



8-bit microcontrollers 80C52/80C54/80C58 



ORDERING INFORMATION 



ROM 

8k x 8 


ROM 

16kx8 


ROM 

32k x 8 


TEMPERATURE RANGE °C 
AND PACKAGE 


FREQ 
MHz 


DRAWING 
NUMBER 


P80C52EBPN 


P80C54EBPN 


P80C58EBPN 


to +70, Plastic Dual In-line Package 


16 


SOT129-1 


P80C52EBAA 


P80C54EBAA 


P80C58EBAA 


to +70, Plastic Leaded Chip Carrier 


16 


SOT187-2 


P80C52EBBB 


P80C54EBBB 


P80C58EBBB 


to +70, Plastic Quad Flat Pack 


16 


SOT307-2 


P80C52EFP N 


P80C54EFPN 


P80C58EFPN 


-40 to +85, Plastic Dual In-line Package 


16 


SOT129-1 


P80C52EFA A 


P80C54EFA A 


P80C58EFAA 


-40 to +85, Plastic Leaded Chip Carrier 


16 


SOT187-2 


P80C52EFBB 


P80C54EFBB 


P80C58EFBB 


-40 to +85, Plastic Quad Flat Pack 


16 


SOT307-2 


P80C52IBP N 


P80C54IBP N 


P80C58IBP N 


to +70, Plastic Dual In-line Package 


24 


SOT129-1 


P80C52IBA A 


P80C54IBA A 


P80C58IBA A 


to +70, Plastic Leaded Chip Carrier 


24 


SOT187-2 


P80C52IBB B 


P80C54IBB B 


P80C58IBB B 


to +70, Plastic Quad Flat Pack 


24 


SOT307-2 


P80C52IFP N 


P80C54IFP N 


P80C58IFP N 


-40 to +85, Plastic Dual In-line Package 


24 


SOT129-1 


P80C52IFA A 


P80C54IFA A 


P80C58IFA A 


—40 to +85, Plastic Leaded Chip Carrier 


24 


SOT187-2 


P80C52IFB B 


P80C54IFB B 


P80C58IFB B 


-40 to +85, Plastic Quad Flat Pack 


24 


SOT307-2 


P80C52NBAA 


P80C54NBAA 


P80C58NBAA 


to +70, Plastic Leaded Chip Carrier 


33 


SOT 187-2 


P80C52NBPN 


P80C54NBPN 


P80C58NBPN 


to +70, Plastic Dual In-line Package 


33 


SOT129-1 


P80C52NBBB 


P80C54NBBB 


P80C58NBBB 


to +70, Plastic Quad Flat Pack 


33 


SOT307-2 


P80C52NFAA 


P80C54NFAA 


P80C58NFAA 


-40 to +85, Plastic Leaded Chip Carrier 


33 


SOT187-2 


P80C52NFPN 


P80C54NFPN 


P80C58NFPN 


-40 to +85, Plastic Dual In-line Package 


33 


SOT129-1 


P80C52NFBB 


P80C54NFBB 


P80C58NFBB 


-40 to +85, Plastic Quad Flat Pack 


33 


SOT307-2 



LOGIC SYMBOL 




SU00732 



1996 Aug 16 



3-189 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



BLOCK DIAGRAM 



« 



Vss I 



PORTO 
DRIVERS 

7> — 7 



t 



PORT 2 
DRIVERS 



w. i nf. 



RAM ADDR 
REGISTER 

— 7T 



it 



PORT 
LATCH 



K. 3 



REGISTER 



RST — 











O 


d 


TIMING 


E 
o 


IS 


AND 




lO 


CONTROL 


1 


5 

W 






tr 









|_XJAL1 



' — ID) — - 



s 



_iz. 



STACK 
POINTER 




<T <T 



PORT 1 
LATCH 



1 



PORT 1 
DRIVERS 



| 



PROGRAM 
ADDR! 



BUFFER f — 



PC 
INCRE- 
MENTER 



HHtXiHAM A k 

COUNTER v, — ^ 



MULTIPLE 
DPTRs 



PORT 3 
LATCH 



.= — m- — 



— 



^ PORT 3 
"1 DRIVERS 

Iff 



1996 Aug 16 



3-190 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



Table 1 . 80C52/80C54/80C58 Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 

ADDRESS 


BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 
MSB LSB 


RESET 
VALUE 


ACC* 


MULUi I lUlalUi 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


00H 


A I lYQjf 


A i i v i I i a rw 
rsuAiiiai y 


8EH 






_ 


_ 


_ 


_ 


_ 


AO 


xxxxxxxOB 


Ai |YR1# 
nUAtl I # 


Auxiliary 1 


A2H 


_ 


_ 


_ 


_ 


_ 


_ 


_ 


DPS 




b 


B register 


run 


F7 


F6 


F5 


F4 


F3 


F2 


F1 


FO 


00H 


DPTR: 


Data Pointer (2 bytes) 






















DPH 


Data Pointer High 


83H 


















00H 


DPL 


Data Pointer Low 


82H 


















00H 








AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 




IE* 


Interrupt Enable 


A8H 


EA 


EC 


ET2 


ES 


ET1 


EX1 


ETO 


EXO 


00H 








BF 


BE 


BD 


BC 


BB 


BA 


B9 


B8 




IP* 


Interrupt Priority 


B8H 




- 


PT2 


PS 


PT1 


PX1 


PTO 


PXO 


xOOOOOOOB 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




IPH# 


Interrupt Priority High 


B7H 






PT2H 


PSH 


PT1H 


PX1H 


PTOH 


PXOH 


xOOOOOOOB 




Pnrt n 
rOll U 




87 


86 


85 


84 


83 


82 


81 


80 




pn* 
ru 


80H 


AD7 


AD6 


AD5 


AD4 


AD3 


AD2 


AD1 


ADO 


FFH 








97 


96 


95 


94 


93 


92 


91 


90 




pr 


Portl 


90H 














T2EX 


T2 


FFH 






A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 




P2* 


Port 2 


AOH 


AD15 


AD14 


AD13 


AD12 


AD11 


AD10 


AD9 


AD8 


FFH 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




P3* 


Port 3 


BOH 


HD~ 


WR 


* 


TO 


TTCTT 


INTO 


TxD 


RxD 


FFH 












PCON# 1 


Power Control 


87H 


SM0D1 


SMODO 




POF2 


GF1 


GFO 


PD 


IDL 


OOxxOOOOB 








D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 




PSW 


Program Status Word 


DOH 


CY 


AC 


FO 


RS1 | RSO 


OV 




P 


00H 


RACAP2H# 


Timer 2 Capture High 


CBH 


















00H 


RACAP2L# 


Timer 2 Capture Low 


CAH 


















00H 


SADDR# 


Slave Address 


A9H 


















00H 


SADEN# 


Slave Address Mask 


B9H 


















00H 

xxxxxxxxB 


SBUF 


Sprint Data Rnffpr 


99H 
























9F 


9E 


9D 


9C 


9B 


9A 


99 


98 




SCON* 


Rprial Cnntrnl 


98H 


SMO/FE | SM1 


SM2 


REN 


TBS 


RB8 


T ' 


Rl 


00H 


SP 


oiacK r'oinier 


Bin 



















07H 








8F 


8E 


8D 


8C 


8B 


8A 


89 


88 




TCON- 


Timer Control 


88H 


TF1 


TR1 


TFO 


TRO 


IE1 


m 


IE0 j 


ITO 


00H 








CF 


CE 


CD 


CC 


CB 


CA 


C9 


C8 




T2CON* 


Timer 2 Control 


C8H 


TF2 


EXF2 


RCLK 


TCLK 


EXEN2 


TR2 


C/T2 


CP/RES 


00H 


T2MOD# 


Timer 2 Mode Control 


C9H 














T20E 


DCEN 


xxxxxxOOB 


THO 


Timer High 


8CH 


















00H 


TH1 


Timer High 1 


8DH 


















OOH 


TH2# 


Timer High 2 


CDH 


















00H 


TLO 


Timer Low 


8AH 


















OOH 


TL1 


Timer Low 1 


8BH 


















OOH 


TL2# 


Timer Low 2 


CCH 


















OOH 


TMOD 


Timer Mode 


89H 


GATE 


C/T 


M1 


MO 


GATE | 


C/T | 


M1 


MO 


OOH 



• SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 
- Reserved bits. 

1 . Reset value depends on reset source. 

2. Bit will not be affected by Reset. POF is not present in 80C52. 



1996 Aug 16 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS PLASTIC QUAD FLAT PACK PIN FUNCTIONS 




Pin 


Function 


Pin 


Function 


Pin 


Function 


1 


NC- 


16 


P3.«T0 


31 


P2.7/A1S 


2 


P1.0/T2 


17 


P3.5/n 


32 
33 


P5EH 


3 


P1.1/T2EX 


18 


P3.6/WR 


ALE 


4 P1.2 


19 


P3.7/RD 


34 


NC* 


5 


P1.3 


20 


XTAL2 


35 


E7S 


6 


P1.4 


21 


XTAL1 


36 


P0.7/AD7 


7 


P1.5 




v S s 


37 


P0.67AD6 


S 


PI. 6 


23 


NC 


38 


P0.5/AD5 


9 


P1.7 


24 


P2.0/A8 


39 


P0.4/AD4 


10 


RST 


26 


P2.1/A9 


40 


P0.3/AD3 


11 


P3.0/RxD 


26 


P2.2/A10 


41 


P0.2/AD2 


12 


NC 


27 


P2.3/A11 


42 


P0.1/AD1 


13 


P3.1/TxD 


28 


P2.4/A12 


43 


P0.0/AD0 


14 


P3.2/IWTB 


29 


P2.5/A13 


44 


Vcc 


15 


P3.3/INTT 


30 


P2.6/A14 







•DO NOT CONNECT 




Pin 


Function 


Pin 


Function 


1 


P1.5 


16 


Vss 


2 


P1.6 


17 


NC 


3 


P1.7 


18 


P2.0/A8 


4 


RST 


19 


P2.1/A9 


5 


P3.0/RXD 


20 


P2.2/A10 


6 


NC 


21 


P2.3/A11 


7 


P3.1/TXD 


22 


P2.4/A12 


8 


P3.2/IRT0 


23 


P2.6/A13 


9 


P3.3/INTT 


24 


P2.67A14 


10 


P3.4/T0 


25 


P2.7/A15 


11 


P3.57T1 


26 


PSEN 


12 


P3.6/WH 


27 


ALE 


13 


P3.7/RTJ 


26 


NC 


14 


XTAL2 


29 


EA 


15 


XTAL1 


30 


P0.7/AD7 


• DO NOT CONNECT 







— Jj/ 



Pin Function 

31 P0.6/AD6 

32 P0.5/AD5 

33 P0.4/AD4 

34 P0.3/AD3 

35 P0.2/AD2 

36 P0.1/AD1 



37 P0.0/ 

38 Vcc 

39 NC 



40 P1.0/T2 

P1.1/T2EX 



42 P1 

43 P1.3 

44 PI. 4 



PIN DESCRIPTIONS 



MNEMONIC 



PIN NUMBER 



DIP 



LCC QFP 



TYPE 



NAME AND FUNCTION 



Vss 
Vcc 

PO.0-0.7 



P1.0-P1.7 



P2.0-P2.7 



20 
40 



39-32 



1-8 



1 
2 
3 
4 
5 
6 
7 
8 

21-28 



22 
44 



43-36 



2 
3 
4 
5 
6 
7 
8 
9 

24-31 



16 
38 



37-30 



40-44, 
1-3 



40 
41 
42 
43 
44 
1 
2 
3 

18-25 



I/O 



I/O 



I/O 
I 
I 

I/O 
I/O 
I/O 
I/O 
I/O 
I/O 



Ground: 0V reference. 

Power Supply: This is the power supply voltage for normal, idle, and power-down 
operation. 

Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to 
them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data memory. In 
this application, it uses strong internal pull-ups when emitting 1s. Port also outputs the 
code bytes during program verification. External pull-ups are required during program 
verification. 

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 1 pins that are externally pulled low will source current because of the internal pull-ups. 
(See DC Electrical Characteristics: ly. Port 1 also receives the low-order address byte 
during program memory verification. Alternate functions include: 

T2 (P1.0): Timer/Counter 2 external count input/Clockout 

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 



Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1 s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 2 pins that are externally being pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l| L ). Port 2 emits the high-order address byte 
during fetches from external program memory and during accesses to external data memory 
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal 
pull-ups when emitting 1 s. During accesses to external data memory that use 8-bit 
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 



1996 Aug 16 



3-192 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



PIN DESCRIPTIONS (Continued) 





PIN NUMBER 






MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAME AND FUNCTION 


P3.0-P3.7 


10-17 


lit 
13-19 


5, 
7-13 


I/O 


Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s 
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 3 pins that are externally being pulled low will source current because of the pull-ups. 
(See DC Electrical Characteristics: l| L ). Port 3 also serves the special features of the 80C51 
family, as listed below: 




10 


■j-] 


5 


I 


RxD (P3.0): Serial input port 




■]■) 


13 


j 





TxD (P3.1): Serial output port 




12 


14 


8 


1 


INTO (P3.2): External interrupt 




13 


15 


9 


1 


INTT (P3.3): External interrupt 




14 


16 


10 


1 
1 


Tn /DO A\~ Timor fl oularnal inm it 

i u (rd.<ij. i imer u external mpui 




15 


17 


11 


1 


T1 (P3.5): Timer 1 external input 




16 


18 


12 


o 


WR (P3.6): External data memory write strobe 




17 


19 


13 





RTJ (P3.7): External data memory read strobe 


RST 


9 


10 


4 


1 


Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to Vss permits a power-on reset using only an external 
capacitor to Vcc- 


ALE 


30 


33 


27 


o 


Address Latch Enable: Output pulse for latching the low byte of the address during an 
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the 
oscillator freguoncy, and can be used for external timing or clocking. Note that one ALE 
pulse is skipped during each access to external data memory. ALE can be disabled by 
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. 


PSER 


29 


32 


26 


o 


Program Store Enable: The read strobe to external program memory. When the 












80C52/80C54/80C58 is executing code from the externajprogram memory, PSEN is 
activated twice each machine cycle, except that two PSEN activations are skipped during 






















each access to external data memory. PSEN is not activated during fetches from internal 












program memory. 


EA 


31 


35 


29 


1 


External Access Enable: EA" must be externally held low to enable the device to fetch code 
from external program memory locations 0000H and 7FFFH. If EA" is held high, the device 












executes from internal program memory unless the program counter contains an address 
greater than 7FFFH. If security bit 1 is programmed, EA will be internally latched on Reset. 












XTAL1 


19 


21 


15 


1 


Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 


XTAL2 


18 


20 


14 


o 


Crystal 2: Output from the inverting oscillator amplifier. 



NOTE: 

To avoid latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V C c + 0.5V or V ss - 0.5V, respectively. 



1996 Aug 16 



3-193 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



TIMER 2 OPERATION 
Timer 2 

Timer 2 is a 1 6-bit Timer/Counter which can operate as either an 
event timer or an event counter, as selected by C/T2* in the special 
function register T2CON (see Figure 1 ). Timer 2 has three operating 
modes:Capture, Auto-reload (up or down counting) ,and Baud Rate 
Generator, which are selected by bits in the T2CON as shown in 
Table 2. 

Capture Mode 

In the capture mode there are two options which are selected by bit 
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 1 6-bit timer or 
counter (as selected by C/T2* in T2CON) which, upon overflowing 
sets bit TF2, the timer 2 overflow bit. This bit can be used to 
generate an interrupt (by enabling the Timer 2 interrupt bit in the 
IE register/SFR table). If EXEN2= 1 , Timer 2 operates as described 
above, but with the added feature that a 1 - to -0 transition at external 
input T2EX causes the current value in the Timer 2 registers, TL2 
and TH2, to be captured into registers RCAP2L and RCAP2H, 
respectively. In addition, the transition at T2EX causes bit EXF2 in 
T2CON to be set, and EXF2 like TF2 can generate an interrupt 
(which vectors to the same location as Timer 2 overflow interrupt. 
The Timer 2 interrupt service routine can interrogate TF2 and EXF2 
to determine which event caused the interrupt). The capture mode is 
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in 
this mode. Even when a capture event occurs from T2EX, the 
counter keeps on counting T2EX pin transitions or osc/1 2 pulses.). 

Auto-Reload Mode (Up or Down Counter) 

In the 16-bit auto-reload mode, Timer 2 can be configured (as either 
a timer or counter (C/T2* in T2CON)) then programmed to count up 
or down. The counting direction is determined by bit DCEN(Down 
Counter Enable) which is located in the T2MOD register (see 



Figure 3). When reset is applied the DCEN=0 which means Timer 2 
will default to counting up. If DCEN bit is set, Timer 2 can count up 
or down depending on the value of the T2EX pin. 

Figure 4 shows Timer 2 which will count up automatically since 
DCEN=0. In this mode there are two options selected by bit EXEN2 
in T2CON register. If EXEN2=0, then Timer 2 counts up to OFFFFH 
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the 
Timer 2 registers to be reloaded with the 1 6-bit value in RCAP2L 
and RCAP2H. 

The values in RCAP2L and RCAP2H are preset by software means. 
If EXEN2=1 , then a 1 6-bit reload can be triggered either by an 
overflow or by a 1 -to-0 transition at input T2EX. This transition also 
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be 
generated when either TF2 or EXF2 are 1 . 

In Figure 5 DCEN=1 which enables Timer 2 to count up or down. 
This mode allows pin T2EX to control the direction of count. When a 
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will 
overflow at OFFFFH and set the TF2 flag, which can then generate 
an interrupt, if the interrupt is enabled. This timer overflow also 
causes the 16-bit value in RCAP2L and RCAP2H to be reloaded 
into the timer registers TL2 and TH2. 

When a logic is applied at pin T2EX this causes Timer 2 to count 
down. The timer will underflow when TL2 and TH2 become equal to 
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets 
the TF2 flag and causes OFFFFH to be reloaded into the timer 
registers TL2 and TH2. 



The external flag EXF2 toggles when Timer 2 underflows or 
overflows. This EXF2 bit can be used as a 1 7th bit of resolution if 
needed. The EXF2 flag does not generate an interrupt in this mode 
of operation. 



(MSB) 



(LSB) 









TCLK 


EXEN2 


TR2 


C/T2 


CP/RE2 


TF2 


EXF2 


RCLK 



Symbol Position Name and Significance 



TF2 
EXF2 

RCLK 
TCLK 



T2CON.7 
T2CON.6 

T2CON.5 
T2CON.4 



EXEN2 T2CON.3 



TR2 
C/T5 



T2CON.2 
T2CON.1 



CP/RL2 T2CON.0 



Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set 
when either RCLK or TCLK = 1 . 

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and 
EXEN2 = 1 . When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down 
counter mode (DCEN = 1 ). 

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock 

in modes 1 and 3. RCLK = causes Timer 1 overflow to be used for the receive clock. 

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock 

in modes 1 and 3. TCLK = causes Timer 1 overflows to be used for the transmit clock. 

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative 

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = causes Timer 2 to 

ignore events at T2EX. 

Start/stop control for Timer 2. A logic 1 starts the timer. 
Timer or counter select. (Timer 2) 

= Internal timer (OSC/1 2) 

1 = External event counter (falling edge triggered). 

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1 . When 
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when 
EXEN2 = 1 . When either RCLK = 1 or TCLK = 1 , this bit is ignored and the timer is forced to auto-reload 
on Timer 2 overflow. 

SU00728 



Figure 1. Timer/Counter 2 (T2CON) Control Register 



1996 Aug 16 



3-194 



Philips Sen 



Product spQci fic9tion 



microcontrollers 80C52/80C54/80C58 



Table 2. Timer 2 Operating Modes 



RCLK + TCLK 


CP/RC5 


TR2 


MODE 








1 


16-bit Auto-reload 





1 


1 


16-bit Capture 


1 


X 


1 


Baud rate generator 


X 


X 





(off) 



osc 




♦ 12 





<JO-_ m +12 1 



C/T3 = 



TL2 


TH2 


(8-bils) 


(8-b«s) 



SEE? 

A 



11,2 Caplure 



_o--r*o_ 




HCAPZL 


RCAP2H 











» |exr:| 



Figure 2. Timer 2 in Capture Mode 







Address = 0C9H 
Not Bit Addressable 



Reset Value = XXXXXX0OB 















T20E 


DCEN 















Bit 7 
Function 



— Not implemented, reserved for future use.* 

T20E Timer 2 Output Enable bit. See details in Programmable Clock-Out. 

DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. 

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features 
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1 . The value read from a reserved bit is 
indeterminate. 



Figure 3. Timer 2 Mode (T2MOD) Control Register 



1996 Aug 16 



3~1 95 



Philips Semiconductors 



Product specification 



microcontrollers 



34/80C58 




TL2 
(8-BITS) 



TH2 
(8-BITS) 



TRANSITION 
DETECTOR 



-o-^o- 







RCAP2L 


RCAP2H 











EXF2 




TIMER 2 
INTERRUPT 



Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) 


(DOWN COUNTING RELOAD VALUE) 



OSC » | -12 | — J^crt 



C/T5 = 



C/T5 = 1 



An 



4 



RCAP2L 


RCAP2H 







X 



INTERRUPT 



COU IN- 
DIRECTION 
1 - UP 
= DOWN 



(UP COUNTING RELOAD VALUE) 



Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 



1996 Aug 16 



3-196 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 







Timer 1 



i NOTE: OSC. Freq. is divided by 2, not 1 2. 



C/TZ-0 



TL2 


TH2 


(B-bits) 


(8-bils) 











Reload 


RCAP2L 


RCAP2H 






T2EX Pin 



-o — r"o- 



Timer 2 
Interrupt 



L 



Control 
EXEN2 

Note availability of additional external interrupt. 



Figure 6. Timer 2 in Baud Rate Generator Mode 



Table 3. Timer 2 Generated Commonly Used 
Baud Rates 











Baud Rate 


Osc Freq 


Timer 2 


RCAP2H 


RCAP2L 


375K 


12MHz 


FF 


FF 


9.6K 


12MHz 


FF 


D9 


2.8K 


12MHz 


FF 


B2 


2.4K 


12MHz 


FF 


64 


1.2K 


12MHz 


FE 


C8 


300 


12MHz 


FB 


1E 


110 


12MHz 


F2 


AF 


300 


6MHz 


FD 


8F 


110 


6MHz 


F9 


57 



The baud rates in modes 1 and 3 are determined by Timer 2's 
overflow rate given below: 

Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate 

16 

The timer can be configured for either "timer" or "counter" operation. 
In many applications, it is configured for "timer" operation (C/T2*=0). 
Timer operation is different for Timer 2 when it is being used as a 
baud rate generator. 

Usually, as a timer it would increment every machine cycle (i.e., 1/12 
the oscillator frequency). As a baud rate generator, it increments 
every state time (i.e., 1/2 the oscillator frequency). Thus the baud 
rate formula is as follows: 

1 and 3 Baud Rates = 

Oscillator Frequency 



Baud Rate Generator Mode 

Bits TCLK and/or RCLK in T2CON (Table 2) allow the serial port 
transmit and receive baud rates to be derived from either Timer 1 or 
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit 
baud rate generator. When TCLK= 1 , Timer 2 is used as the serial 
port transmit baud rate generator. RCLK has the same effect for the 
serial port receive baud rate. With these two bits, the serial port can 
have different receive and transmit baud rates - one generated by 
Timer 1 , the other by Timer 2. 

Figure 6 shows the Timer 2 in baud rate generation mode. The baud 
rate generation mode is like the auto-reload mode, in that a rollover 
in TH2 causes the Timer 2 registers to be reloaded with the 1 6-bit 
value in registers RCAP2H and RCAP2L, which are preset by 
software. 



[32 x [65536 - (RCAP2H, RCAP2L)]] 

Where: (RCAP2H, RCAP2L)= The content of RCAP2H and 
RCAP2L taken as a 1 6-bit unsigned integer. 

The Timer 2 as a baud rate generator mode shown in Figure 6, is 
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a 
rollover in TH2 does not set TF2, and will not generate an interrupt. 
Thus, the Timer 2 interrupt does not have to be disabled when 
Timer 2 is in the baud rate generator mode. Also if the EXEN2 
(T2 external enable flag) is set, a 1-to-0 transition in T2EX 
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but 
will not cause a reload from (RCAP2H, RCAP2L) to (TH2.TL2). 
Therefore when Timer 2 is in use as a baud rate generator, T2EX 
can be used as an additional external interrupt, if needed. 



1996 Aug 16 



3-197 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



When Timer 2 is in the baud rate generator mode, one should not try 
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is 
incremented every state time (osc/2) or asynchronously from pin T2; 
under these conditions, a read or write of TH2 or TL2 may not be 
accurate. The RCAP2 registers may be read, but should not be 
written to, because a write might overlap a reload and cause write 
and/or reload errors. The timer should be turned off (clear TR2) 
before accessing the Timer 2 or RCAP2 registers. 

Table 3 shows commonly used baud rates and how they can be 
obtained from Timer 2. 

Summary Of Baud Rate Equations 

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked 
through pin T2(P1 .0) the baud rate is: 

Baud Rate = Timer 2 Overflow Rate 
16 

If Timer 2 is being clocked internally, the baud rate is: 



Baud Rate ■■ 



[32 x [65536 
Where fosc= Oscillator Frequency 



( osc 

(RCAP2H, RCAP2L)]] 



To obtain the reload value for RCAP2H and RCAP2L, the above 
equation can be rewritten as: 

RCAP2H, RCAP2L = 65536 - ( 32 x ^ Rate ) 

Timer/Counter 2 Set-up 

Except for the baud rate generator mode, the values given for 
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 
must be set, separately, to turn the timer on. see Table 4 for set-up 
of Timer 2 as a timer. Also see Table 5 for set-up of Timer 2 as a 
counter. 



POWER OFF FLAG 3 

The Power Off Flag (POF) is set by on-chip circuitry when the V C c 
level on the 80C54/80C58 rises from to 5V. The POF bit can be 
set or cleared by software allowing a user to determine if the reset is 
the result of a power-on or a warm start after powerdown. The V cc 
level must remain above 3V for the POF to remain unaffected by the 
V cc level. 



Table 4. Timer 2 as a Timer 



MODE 


T2CON 


INTERNAL CONTROL 
(Note 1) 


EXTERNAL CONTROL 
(Note 2) 


16-bit Auto-Reload 


00H 


08H 


1 6-bit Capture 


01H 


09H 


Baud rate generator receive and transmit same baud rate 


34H 


36H 


Receive only 


24H 


26H 


Transmit only 


14H 


16H 


Table 5. Timer 2 as a Counter 


MODE 


TMOD 


INTERNAL CONTROL 
(Note 1) 


EXTERNAL CONTROL 
(Note 2) 


16-bit 


02H 


OAH 


Auto-Reload 


03H 


OBH 



NOTES: 

1 . Capture/reload occurs only on timer/counter overflow. 

2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate 
generator mode. 

3. POF not present in 80C52. 



1 996 Aug 1 6 



3-198 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 
oscillator. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements 
on the duty cycle of the external clock signal, because the input to 
the internal clock circuitry is through a divide-by-two flip-flop. 
However, minimum and maximum high and low times specified in 
the data sheet must be observed. 

Reset 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-on reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. At power-on, the voltage on 
V cc and RST must come up at the same time for a proper start-up. 
Ports 1 , 2, and 3 will asynchronously be driven to their reset 
condition when a voltage above V 1H 1 (min.) is applied to RESET. 

Idle Mode 

In the idle mode (see Table 6), the CPU puts itself to sleep while all 
of the on-chip peripherals stay active. The instruction to invoke the 
idle mode is the last instruction executed in the normal operating 
mode before the idle mode is activated. The CPU contents, the 
on-chip RAM, and all of the special function registers remain intact 
during this mode. The idle mode can be terminated either by any 
enabled interrupt (at which time the process is picked up at the 
interrupt service routine and continued), or by a hardware reset 
which starts the processor in the same manner as a power-on reset. 

Power-Down Mode 

To save even more power, a Power Down mode (see Table 6) can 
be invoked by software. In this mode, the oscillator is stopped and 
the instruction that invoked Power Down is the last instruction 
executed. The on-chip RAM and Special Function Registers retain 
their values until the Power Down mode is terminated. 

On the 80C52/54/58 either a hardware reset or external interrupt 
can be used to exit from Power Down. Reset redefines all the SFRs 
but does not change the on-chip RAM. An external interrupt allows 
both the SFRs and the on-chip RAM to retain their values. 

To properly terminate Power Down the reset or external interrupt 
should not be executed before Vcc is restored to its normal 
operating level and must be held active long enough for the 
oscillator to restart and stabilize (normally less than 1 0ms). 

With an external interrupt, INTO and INT1 must be enabled and 
configured as level-sensitive. Holding the pin low restarts the 



oscillator but bringing the pin back high completes the exit. Once the 
interrupt is serviced, the next instruction to be executed after RETI 
will be the one following the instruction that put the device into 
Power Down. 

Design Consideration 

• When the idle mode is terminated by a hardware reset, the device 
normally resumes program execution, from where it left off, up to 
two machine cycles before the internal rest algorithm takes 
control. On-chip hardware inhibits access to internal RAM in this 
event, but access to the port pins is not inhibited. To eliminate the 
possibility of an unexpected write when Idle is terminated by reset, 
the instruction following the one that invokes Idle should not be 
one that writes to a port pin or to external memory. 

ONCE™ Mode 

The ONCE ("On-Circuit Emulation") Mode facilitates testing and 
debugging of systems using the 80C52/54/58 without removing the 
device from the circuit. The ONCE Mode is invo ked by : 

1 . Pull ALE low while the device is in reset and PSEN is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in ONCE Mode, the Port pins go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the 80C52/54/58 is 
in this mode, an emulator or test CPU can be used to drive the 
circuit. Normal operation is restored when a normal reset is applied. 

Programmable Clock-Out 

The 80C52/54/58 has a new feature. A 50% duty cycle clock can be 
programmed to come out on P1 .0. This pin, besides being a regular 
I/O pin, has two alternate functions. It can be programmed: 

1 . to input the external clock for Timer/Counter 2, or 

2. to output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 
1 6MHz operating frequency. 

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in 
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit 
TR2 (T2CON.2) also must be set to start the timer. 

The Clock-Out frequency depends on the oscillator frequency and 
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) 
as shown in this equation: 

Oscillator Frequency 

4 x (65536 - RCAP2H, RCAP2L) 

In the Clock-Out mode Timer 2 roll-overs will not generate an 
interrupt. This is similar to when it is used as a baud-rate generator. 
It is possible to use Timer 2 as a baud-rate generator and a clock 
generator simultaneously. Note, however, that the baud-rate and the 
Clock-Out frequency will be the same. 



Table 6. External Pin Status During Idle and Power-Down Mode 



MODE 


PROGRAM 
MEMORY 


ALE 


PSER 


PORT 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Float 


Data 


Data 


Data 



1996 Aug 16 



3-199 



Philips Semiconductors 



Product specification 



microcontrollers 80C52/80C54/80C58 



Enhanced DART 

The UART operates in all of the usual modes that are described in 
the first section of Dafa Handbook IC20, 80C51 -Based 8-Bit 
Microcontrollers. In addition the UART can perform framing error 
detect by looking for missing stop bits, and automatic address 
n. The 80C52/54/58 UART also fully supports 

communication as does the standard 80C51 UART. 

When used for framing error detect the UART looks for missing stop 
bits in the communication. A missing bit will set the FE bit in the 
SCON register. The FE bit shares the SCON.7 bit with SMO and the 
function of SCON.7 is determined by PCON.6 (SMODO) (see 
Figure 7). If SMODO is set then SCON.7 functions as FE. SCON.7 
functions as SMO when SMODO is cleared. When used as FE 
SCON.7 can only be cleared by software. Refer to Figure 8. 

Automatic Address Recognition 

Automatic Address Recognition is a feature which allows the UART 
to recognize certain addresses in the serial bit stream by using 
hardware to make the comparisons. This feature saves a great deal 
of software overhead by eliminating the need for the software to 
examine every serial address which passes by the serial port. This 
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART 
modes, mode 2 and mode 3, the Receive Interrupt flag (Rl) will be 
automatically set when the received byte contains either the "Given" 
address or the "Broadcast" address. The 9 bit mode requires that 
the 9th information bit is a 1 to indicate that the received information 
is an address and not data. Automatic address recognition is shown 
in Figure 9. 

The 8 bit mode is called Mode 1 . In this mode the Rl flag will be set 
if SM2 is enabled and the information received has a valid stop bit 
following the 8 address bits and the information is either a Given or 
Broadcast address. 

Mode is the Shift Register mode and SM2 is ignored. 

Using the Automatic Address Recognition feature allows a master to 
selectively communicate with one or more slaves by invoking the 
Given slave address or addresses. All of the slaves may be 
contacted by using the Broadcast address. Two special Function 
Registers are used to define the slave's address, SADDR, and the 
address mask, SADEN. SADEN is used to define which bits in the 
SADDR are to b used and which bits are "don't care". The SADEN 
mask can be logically ANDed with the SADDR to create the "IGiven" 
address which the master will use for addressing each of the slaves. 
Use of the Given address allows multiple slaves to be recognized 
while excluding others. The following examples will help to show the 
versatility of this scheme: 



Slave 1 



Slave 



SADDR 
SADEN 
Given 



1100 0000 
1111 1101 
1100 00X0 



SADDR 
SADEN 
Given 



1100 0000 
1111 1110 
1100 000X 



In the above example SADDR is the same and the SADEN data is 
used to differentiate between the two slaves. Slave requires a in 
bit and it ignores bit 1 . Slave 1 requires a in bit 1 and bit is 
ignored. A unique address for Slave would be 1100 0010 since 
slave 1 requires a in bit 1 . A unique address for slave 1 would be 
1100 0001 since a 1 in bit will exclude slave 0. Both slaves can be 
selected at the same time by an address which has bit = (for 
slave 0) and bit 1 = (for slave 1 ). Thus, both could be addressed 
with 1100 0000. 

In a more complex system the following could be used to select 
slaves 1 and 2 while excluding slave 0: 



Slave 


SADDR = 


1100 0000 




SADEN = 


1111 1001 




Given 


1100 oxxo 


Slave 1 


SADDR = 


1110 0000 




SADEN = 


1111 1010 




Given 


1110 oxox 


Slave 2 


SADDR = 


1110 0000 




SADEN . 


1111 1100 




Given 


1110 ooxx 



In the above example the differentiation among the 3 slaves is in the 
lower 3 address bits. Slave requires that bit = and it can be 
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = and 
it can be uniquely addressed by 1 1 1 and 01 01 . Slave 2 requires 
that bit 2 = and its unique address is 1 1 1 001 1 . To select Slaves 
and 1 and exclude Slave 2 use address 1110 0100, since it is 
necessary t make bit 2 = 1 to exclude slave 2. 

The Broadcast Address for each slave is created by taking the 
logical OR of SADDR and SADEN. Zeros in this result are teated as 
don't-cares. In most cases, interpreting the don't-cares as ones, the 
broadcast address will be FF hexadecimal. 

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR 
address 0B9H) are leaded with 0s. This produces a given address 
of all "don't cares" as well as a Broadcast address of all "don't 
cares", this effectively disables the Automatic Addressing mode and 
allows the microcontroller to use standard 80C51 type UART drivers 
which do not make use of this feature. 



■ 



1996 Aug 16 



3-200 



Philips Semiconductors 



Product specification 



microcontrollers 



80C52/80C54/80C58 



SCON Address = 98H 
Bit Addressable 



Reset Value = 0000 0000B 





SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


Bit: 


7 


6 


5 


4 


3 


2 


1 






Symbol 



(SMODO = 0/1)* 
Function 



FE 



SMO 
SM1 



Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid 
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. 

Serial Port Mode Bit 0, (SMOD0 must = to access bit SMO) 

Serial Port Mode Bit 1 



SMO 


SM1 


Mode 


Description 


Baud Rate" 











shift register 


fosc/12 





1 


1 


8-bit UART 


variable 


1 





2 


9-bit UART 


fosc/64 or fosc/32 


1 


1 


3 


9-bit UART 


variable 



REN 
TB8 
RB8 

Tl 

Rl 



Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the 
received 9th data bit (RB8) is 1 , indicating an address, and the received byte is a Given or Broadcast Address. 
In Mode 1 , if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a 
Given or Broadcast Address. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In modes 2 and 3, the 9th data bit that was received. In Mode 1 , if SM2 = 0, RB8 is the stop bit that was received. 
In Mode 0, RB8 is not used. 

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the 
other modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in 
the other modes, in any serial reception (except see SM2). Must be cleared by software. 



NOTE: 

•SMODO is located al PCON6. 
"fosc = oscillator frequency 



Figure 7. SCON: Serial Port Control Register 













( DO j{ D1 Z 


2 D3 y 


> D4 > 


C 05 / 


f D6 / 


C 07 / 




















-« » 



SET FE BIT IF STOP BIT IS (FRAMING ERROR) 
SMO TO UART MODE CONTROL 



ONLY IN STOP 
MODE 2, 3 BIT 



SMO/FE 


SM1 


SM2 


REN 


TB8 


RB8 


Tl 


Rl 


SCON 
(98H) 






































SMOD1 


SMODO 




POF 


GF1 


GFO 


PD 


IDL 


PCON 
(87H) 



: SCON.7 = SMO 

1 : SCON.7 = FE 



1996 Aug 16 



3-201 



Philips Semi conductors Product specification 

CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 









SMO 


SM1 


SM2 




TB8 


RB8 


T1 




1 
1 


1 



1 1 X 


' — 





D0TOD7 
PROGRAMMED ADDRESS 



SCON 
(98H) 



COMPARATOR 



IN UART MODE 2 OR MODE 3 AND SM2 = 1 : 

INTERRUPT IF REN=1 . RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" 

- WHEN OWN ADDRESS RECEIVED. CLEAR SM2 TO RECEIVE DATA BYTES 

- WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. 



Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 



Interrupt Priority Structure 

The 80C52/54/58 has a 6-source four-level interrupt structure. There 
are 3 SFRs associated with the interrupts on the 80C52/54/58. They 
are the IE and IP. (See Figures 10 and 11.) In addition, there is the 
IPH (Interrupt Priority High) register that makes the four-level 
interrupt structure possible. The IPH is located at SFR address B7H. 
The structure of the IPH register and a description of its bits is 
shown below: 



| PT2H | PSH | PT1H | PX1H | PTOH | PXOH | 



IPH.O PXOH 

IPH.1 PTOH 

IPH.2 PX1H 

IPH.3 PT1H 

IPH .4 PSH 

IPH.5 PT2H 

IPH.6 — 

IPH.7 — 



External interrupt priority high 
Timer interrupt priority high 
External interrupt 1 priority high 
Timer 1 interrupt priority high 
Serial Port interrupt high 
Timer 2 interrupt priority high 
Not implemented 
Not implemented 



The function of the IPH SFR is simple and when combined with the 
IP SFR determines the priority of each interrupt. The priority of each 
interrupt is determined as shown in the following table: 



able 7. Interrupt Table 



PRIORITY BITS 


INTERRUPT PRIORITY LEVEL 


IPH.x 


IP.x 








Level (lowest priority) 





1 


Level 1 


1 





Level 2 


1 


1 


Level 3 (highest priority) 



The priority scheme for servicing the interrupts is the same as that 
for the 80C51 , except there are four interrupt levels on the 
80C52/54/58 rather than two as on the 80C51 . An interrupt will be 
serviced as long as an interrupt of equal or higher priority is not 
already being serviced. If an interrupt of equal or higher level priority 
is being serviced, the new interrupt will wait until it is finished before 
being serviced. If a lower priority level interrupt is being serviced, it 
will be stopped and the new interrupt serviced. When the new 
interrupt is finished, the lower priority level interrupt that was 
stopped will be completed. 



SOURCE 


POLLING PRIORITY 


REQUEST BITS 


HARDWARE CLEAR? 


VECTOR ADDRESS 


XO 


1 


IE0 


N(L)< Y(T)2 


03H 


TO 


2 


TPO 


Y 


OBH 


X1 


3 


IE1 


N(L) Y(T) 


13H 


T1 


4 


TF1 


Y 


1BH 


SP 


5 


R1.TI 


N 


23H 


T2 


6 


TF2, EXF2 


N 


2BH 


PCA 


7 


CF, CCFn 
n = 0-4 


N 


33H 



NOTES: 

1. L = Level activated 

2. T = Transition activated 



1996 Aug 16 



3-202 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 





7 


6 


5 


4 


3 


2 


1 





IEO (A8H) 


EA 




ET2 


ES 


ET1 


EX1 


ETO 


EXO 



Enable Bit = 1 enables the interrupt. 
Enable Bit = disables it. 



BIT 

IE.7 

IE.6 
IE.5 
IE.4 
IE.3 
IE.2 
IE.1 
IE.0 



SYMBOL FUNCTION 

EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1 , each interrupt can be individually 

enabled or disabled by setting or clearing its enable bit. 



ET2 

ES 

ET1 

EX1 

ETO 

EXO 



Timer 2 interrupt enable bit. 
Serial Port interrupt enable bit. 
Timer 1 interrupt enable bit. 
External interrupt 1 enable bit. 
Timer interrupt enable bit. 
External interrupt enable bit. 



Figure 10. IE Registers 



IPO (B8H) 



7 


6 


5 


4 


3 


2 


1 









PT2 


PS 


PT1 


PX1 


PTO 


PXO 



Priority Bit = 1 assigns high priority 
Priority Bit = assigns low priority 



BIT 

IP.7 

IP.6 — 

IP.5 PT2 

IP.4 PS 

IP.3 PT1 

IP.2 PX1 

IP.1 PTO 

IP.O PXO 



SYMBOL FUNCTION 

— Not implemented, reserved for future use. 



Timer 2 interrupt priority bit. 
Serial Port interrupt priority bit. 
Timer 1 interrupt priority bit. 
External interrupt 1 priority bit. 
Timer interrupt priority bit. 
External interrupt priority bit. 



Figure 11. IP 



1996 Aug 16 



3-203 



Reduced EMI Mode 

The AO bit (AUXR.O) in the AUXR register when set disables the 
ALE output. 

Reduced EMI Mode 

AUXR (8EH) 



1~T 



I - I AO | 



AO: Turns off ALE output. 

Dual Data Pointer Register (DPTR) 

The dual DPTR structure (see Figure 12) is a way by which the 
80C52/54/58 will specify the address of an external data memory 
location. There are two 1 6-bit DPTR registers that address the 
external memory, and a single bit called DPS = AUXR1/bitO that 
allows the program code to switch between them. 

• Register Name: AUXR1# 

• SFR Address: A2H 

• Reset Value: xxxxxxxOB 

7 6 5 4 3 2 1 

| - | - | - I - I - I - I - I OPS I 

Where: 

DPS = AUXRVbitO = Switches between DPTRO and DPTR1 . 



The[ 



Select Re9 
DPTRO 
DPTR1 



DPS 


1 




Figure 12. DPTR Structure 



DPTR Instructions 

The instructions that refer to DPTR refer to the data pointer that is 
currently selected using the AUXR1/bit register. The six 
instructions that use the DPTR are as follows: 



INC DPTR 

MOV DPTR, #data1 6 
MOV A, @ A+DPTR 

MOVX A, @ DPTR 

MOVX @ DPTR , A 

JMP @ A + DPTR 



Increments the data pointer by 1 

Loads the DPTR with a 16-bit constant 

Move code byte relative to DPTR to 
ACC 

Move external RAM (16-bit address) to 
ACC 

Move ACC to external RAM (16-bit 
address) 

Jump indirect relative to DPTR 



s DPS bit status whould be saved by software when switching 
between DPTRO and DPTR1 . 



The data pointer can be accessed on a byte-by-byte basis by 
specifying the Low or High byte in an instruction which accesses the 
SFRs. See application note AN458 for detailed operation 



ABSOLUTE MAXIMUM RATINGS 1 2 3 



PARAMETER 


RATING 


UNIT 


Operating temperature under bias 


Oto+70 or -40 to +85 


°C 


Storage temperature range 


-65 to +150 


°c 


Voltage on EATVpp pin to Vss 


to +13.0 


V 


Voltage on any other pin to Vss 


-0.5 to +6.5 


V 


Maximum Iol per I/O pin 


15 


mA 


Power dissipation (based on package heat transfer limitations, not device power consumption) 


1.5 


W 



NOTES: 



1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vss unless otherwise 
noted. 



1996 Aug 16 



3-204 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



DC ELECTRICAL CHARACTERISTICS 

Tamb = n °C t° +70 o C or -40°C to +85°C, V C c = 5.0V ±10%; V ss = 0V 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 


VlL 


Input low voltage 


4.5V < V cc < 5.5V 


-0.5 




0.2V CC -0.1 


V 


V| H 


Input high voltage (ports 0, 1, 2, 3, EA) 




0.2V CO +0.9 




V cc +0.5 


V 


V SH1 


Innut h/ah voltaae XTAL1 RST 




0.7V C c 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 3 s 


Vrr = 4 5V 
"CC „ 

l 0L = 1.6mA 2 






0.4 


V 


v OL1 


Ontniit Inw unltanfi nnrt AI F PSFN^- ' 


V CC = 4.5V 
Iol = 3.2mA 2 








V 


VOH 


Output high voltage, ports 1 , 2, 3 3 


V cc = 4.5V 

'OH - JU^lrt 


Vcc-0.7 






V 


V H1 


Output high voltage (port in external bus mode), 
ALE 9 , PSEN 3 


V CC = 4.5V 
Iqh = —3.2mA 


Vcc-0.7 






V 


III 


Logical input current, ports 1 , 2, 3 


V IN = 0.4V 


-1 




-50 


HA 


ht. 


Logical 1 -to-0 transition current, ports 1 , 2, 3 s 


V| N = 2.0V 
See note 4 






-650 


MA 




Input leakage current, port 


0.45 < V| N < V C c - 0-3 






±10 


ma 


!CC 


Power supply current (see Figure 20): 
Active mode @ 1 6MHz 5 
Idle mode @ 16MHz 5 


See note 5 






16 
4 












mA 
mA 




Power-down mode 


Tamb = to +70°C 
Tamb = -40 to +85°C 




3 


50 
75 


fA 
ItA 


r rst 






40 








Internal reset pull-down resistor 




225 


kn 


Cio 


Pin capacitance 10 (except ES) 








15 


PF 



NOTES: 



1 . Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

2. Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the Vols of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1 -to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I l can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs exceed the test conditions. 

3. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the (V cc -0.7) specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 

5. See Figures 21 through 24 for l C c test conditions. 

Active Mode: Ice = 0.9 x FREQ + 1.1; 

Idle Mode: l C c = 0.18 x FREQ +1.0; See Figure 20. 

6. This value applies to T^ = 0°C to +7 0°C. Fo r T amb = -40°C to +85°C, l TL = -750|iA. 

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

8. Under steady state (non-transient) conditions, I l must be externally limited as follows: 

Maximum I l per port pin: 1 5mA ("NOTE: This is 85°C specification.) 

Maximum I l per 8-bit port: 26mA 

Maximum total I l for all outputs: 71 mA 
If Iol exceeds the test condition, V l may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

9. ALE is tested to V m , except when ALE is off then V h is the voltage specification. 

10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF 
(except EA" it is 25pF). 



1996 Aug 16 



3-205 



Philips Ssm [conductors 



Product specification 



it microcontrollers 



80C52/80C54/80C58 









0.2VCC+0.9 


VLOHD^V ^ timing , \vrjH-0.1V 

VLOAD < ^ R ™ CE d > 

Vi nAn-0.1V H TOINTS ^ X Vm +0.1V 




NOTE: 

AC inputs during testing are driven at Vcc -0.5 for a logic ' 1 ' and 0.45V for a logic '0'. 
Timing measurements are made at Vih min (or a logic '1' and Vil max tor a logic '0*. 

SU00717 


NOTE: 




For timing purposes, a port is no longer floating when a 100mV change from 
load voltage occurs, and begins to float when a tOOmV change from the loaded 
VcWVol level occurs. lotVot * ±20mA. 

SU007fa 



Figure 18. AC Testing Input/Output 



Figure 19. Float Waveform 








4MHz 8MH2 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz 
FREQ AT XTAL1 



Figure 20. Ice vs. FREQ 
Valid only within frequency specifications of the device under test 



SU00766 



1996 Aug 16 



3-210 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0"C to +70°C or -40°C to +85°C, V CC = 5V ±1 0%, V S S = 0V 1 ■ 2 ' 3 



SYMBOL 


FIGURE 


PARAMETER 


24MHz CLOCK 


VARIABLE CLOCK 4 


33MHz CLOCK 


UNIT 


MIN 


MAX 


MIN 


MAX 


MIN 


MAX 


1/tci_CL 


13 


Oscillator frequency 

Speed versions : 1 (24MHz) 
: N (33MHz) 


3.5 


24 


3.5 


33 


3.5 


33 


MHz 


t|_HLL 


13 


ALE pulse width 


43 




2tCLCl^»° 




21 




ns 


tAVLL 


13 


Address valid to ALE low 


17 




tCLCL -25 




5 




ns 


•llax 


13 


Address hold after ALE low 


17 




•cLCL-25 








ns 


tLLIV 


13 


ALE low to valid instruction in 




102 




4tcLCL-65 




55 


ns 


<LLPL 


13 


ALE low to PSEN low 


17 




tCLCL- 25 




5 




ns 


tpLPH 


13 


PSEN pulse width 


80 




3tcLCL^t5 




45 




ns 


tpLIV 


13 


PSEN low to valid instruction in 




65 




3tcLCL-60 




30 


ns 


tpxix 


13 


Input instruction hold after PSEN 

















ns 




.' / 


13 


Input instruction float after PSEN 




17 




tCLCL-25 




5 


ns 


'aviv 


13 


Address to valid instruction in 




128 




5tcLCL-80 




70 


ns 


tpLAZ 


13 


PSEN low to address float 




10 




10 




10 


ns 


Data Memory 


tRLRH 


14, 15 


ED pulse width 


150 




6tcLCL-100 




82 




ns 


twLWH 


14, 15 


WR pulse width 


150 




6tc LCL -100 




82 




ns 






ED low to valid data in 




118 




5tcLCL-90 




60 




tRLDV 


14, 15 








ns 


Irhdx 


14, 15 


Data hold after ED 

















ns 


tRHDZ 


14, 15 


Data float after ED 




55 




2tcLCL-28 




32 


ns 








t[_LDV 


14, 15 


ALE low to valid data in 




183 




8tcLCL-150 




90 


ns 


tAVDV 


14, 15 


Address to valid data in 




210 




9tcLCL~ 1 65 




105 


ns 


tLLWL 


14, 15 


ALE low to ED or WE low 


75 


175 


3tcLCL-50 


3tCLCL+50 


40 


140 


ns 


tAVWL 


14, 15 


Address valid to WE low or ED low 


92 




4t0LCL-75 




45 




ns 


tQVWX 


14, 15 


Data valid to WE transition 


12 




tCLCL-30 









ns 


twHQX 


14, 15 


Data hold after WE 


17 




tCLCL- 25 




5 




ns 


tQVWH 


15 


Data valid to WE high 


162 




7tci_CL-130 




80 




ns 


tRLAZ 


14, 15 


ED low to address float 

















ns 


twHLH 


14, 15 


ED or WR high to ALE high 


17 


67 


tCLCL-25 


tCLCL+25 


5 


55 


ns 


External Clock 




tcHCX 


17 


High time 


17 




17 


tCLCL-tcLCX 






ns 


tdCX 


17 


Low time 


17 




17 


tcLCL-tcHCX 






ns 


tCLCH 


17 


Rise time 




5 




5 






ns 


tcHCL 


17 


Fall time 




5 




5 






ns 


Shift Register 


txLXL 


16 


Serial port clock cycle time 


505 




1 2tcLCL 




360 




ns 


tQVXH 


16 


Output data setup to clock rising edge 


283 




10tcLCL-133 




167 




ns 


txHQX 


16 


Output data hold after clock rising edge 


3 




2tcLCL-80 








ns 


txHDX 


16 


Input data hold after clock rising edge 

















ns 


tXHDV 


16 


Clock rising edge to input data valid 




283 




10tcLCL-133 




167 


ns 



NOTES: 

1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. Variable clock is specified for oscillator frequencies greater than 1 6MHz to 33MHz. For frequencies equal or less ttian 1 6MHz, see 1 6MHz 
"AC Electrial Characteristics", page 3-206. 



1936 Aug 16 



3-207 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



AC ELECTRICAL CHARACTERISTICS 



SYMBOL 


FIGURE 


DA D A UCTCD 


16MHz CLOCK 


VARIABLE CLOCK 


UNIT 


MIN 


MAX 


MIN 


MAX 


t'tcLCL 


13 


Oscillator frequency 

Speed versions : E 






3.5 


16 


MHz 


tLHLL 


13 


ALE pulse width 


85 




2tcLCL"^0 




ns 


Wll 


13 


Address valid to ALE low 


22 




toLOL-40 




ns 


t|_LAX 


13 


Address hold after ALE low 


32 




tCLCL-30 




ns 


*LLIV 


13 


ALE low to valid instruction in 




150 




4tc LCL -100 


ns 


<LLPL 


13 


ALE low to PSEN low 


32 




tcLCL-30 




ns 




13 


PSEN pulse width 


142 




3tcLCL"^5 




ns 


tpLPH 






tpLIV 


13 


PSEN low to valid instruction in 4 




82 




3t C LCL-105 


ns 


tpxix 


13 


Input instruction hold after PSEN 












ns 


tpxiz 


13 


Input instruction float after PSEN 




37 




tCLCL-25 


ns 


WlV 


13 


Address to valid instruction in 4 




207 




5tcLCL-105 


ns 


tpLAZ 


13 


PSEN low to address float 




10 




10 


ns 


Data Memory 


tRLRH 


14, 15 


RD pulse width 


275 




6tcLCL-1°° 




ns 


'WLWH 


14, 15 


WR pulse width 


275 




6tcLCL-100 




ns 


tRLDV 


14, 15 


RD low to valid data in 




147 




5tcLCL-165 


ns 


tRHDX 


14, 15 


Data hold after RD 












ns 


tRHDZ 


14, 15 


Data float after RD 




65 




2t C LCL-60 


ns 


*LLDV 


14, 15 


ALE low to valid data in 




350 




8t OLCL -150 


ns 


tAVDV 


14, 15 


Address to valid data in 




397 




9tCLCL-165 


ns 


'llwl 


14, 15 


ALE low to RD or WR low 


137 


239 


3tcLCL-S0 


3tcLCL+50 


ns 


Iavwl 


14, 15 


Address valid to WR low or RD low 


122 




4tcLCL-130 




ns 


tQVWX 


14, 15 


Data valid to WR transition 


13 




tcLCL-50 




ns 


tWHQX 


14, 15 


Data hold after WR 


13 




tCLCL-50 




ns 


'qvwh 


15 


Data valid to WR high 


287 




7t C LCL-150 




ns 


tRLAZ 


14, 15 


RD low to address float 












ns 


•wHLH 


14, 15 


RD or WR high to ALE high 


23 


103 


tCLCL-^tO 


•CLCL +40 


ns 


External Clock 


♦CHCX 


17 


High time 


20 




20 


tcLCL-tcLCX 


ns 


tCLOX 


17 


Low time 


20 




20 


'CLCL-tCHCX 


ns 


*CLCH 


17 


Rise time 




20 




20 


ns 


tcHCL 


17 


Fall time 




20 




20 


ns 


Shift Register 


*XLXL 


16 


Serial port clock cycle time 


750 




12t CLCL 




ns 


tQVXH 


16 


Output data setup to clock rising edge 


492 




10t O LCL-133 




ns 


tXHQX 


16 


Output data hold after clock rising edge 


8 




2tCLCL-H7 




ns 


txHDX 


16 


Input data hold after clock rising edge 












ns ' 


tXHDV 


16 


Clock rising edge to input data valid 




492 




10tcLCL-133 


ns 



NOTES: 

1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 
drivers. 

4. See application note AN457 for external memory interfacing. 



1996 Aug 16 



3-206 



Philips Semiconductors 




Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



E -/ ^ 



•avll 



tuWL 



•llax 



\ 



twLWH 



tQVWX 



*WHLH 



s \ / 

\ / 



"" \ / ' A0-A7 V v ' 

? \ FROMRIORDPL /S 

zx 



'avwl 



tQVWH 



•WHQX 



P2.0-P2.7 OR A6-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 15. External Data Memory Write Cycle 



INSTRUCTION 



ALE 



| | , | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 

JIJLJIJIJLJLJTJLJIJLTUI^ 

\*~ 'XLXL "*) 



i_r~L 



OUTPUT DATA . 



WRITE TO SBUF 



CLEAR Rl 



"H h" *XHQX I 
tQVXH \* »\ | 

'XHDV |* *] ^ |*" XHD>< SET Tl 



t 

SET Rl 



Figure 16. Shift Register Mode Timing 



tCHCL- 



*-tCHCX-* 
tCLCH 



tcLCL 



Figure 17. External Clock Drive 



1996 Aug 16 



3-209 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 
T (= time). The other characters, depending on their positions, 
indicate the name of a signal or the logical status of that signal. The 
designations are: 
A - Address 
C - Clock 
D - Input data 
H - Logic level high 
I - Instruction (program memory 
L - Logic level low, or ALE 



P - F5EN 
Q- Output data 
R - RT3 signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: Iavll = Time for address valid to ALE low. 
tu.PL =Time for ALE low to PS EN low. 




*LHLL 



KUKI U 



>: 



Iavll 



y v 



— 



t[.LPL 



tpLPH 



<LLAX 



tLLIV > 

< t PLIV > 



tpLAZ 



^ { AO-A7 N ) ^ INSTRIN ^ ^ ^ 



'AVIV 



tpxix " 



- tpxiz- 



X 



Figure 13. External Program Memory Read Cycle 



Iavll 



Xt 

:5c 



/ 



LI 



'WHLH 



' 'LLDV ' 



tLLWL 



tLLAX 



AO-A7 
FROM Rl OR DPL 



1 



«' RLA2 > 



tAVWL " 



tRLRH 



tRLDV 



'AVDV 



y 



Irhdx ' 



X / 







•rhdz. 



< ; DATA IN 



AO-A7 FROM PCL 



X. 



P2.0-P2.7 OR AB-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 14. External Data Memory Read Cycle 



1996 Aug 16 



3-208 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 







CLOCK SIGNAL - 



RST 

XTAL2 
XTAL1 
V SS 



PO 



Vcc 



Vcc 



Vcc 



(NO- 



CLOCK SIGNAL - 





Vcc 


RST 






PO 








EA 


XTAL2 




XTAL1 




Vss 









ice 

u 



Figure 21 . Ice Test Condition, Active Mode 
All other pins are disconnected 



Figure 22. Ice Test Condition, Idle Mode 
All other pins are disconnected 



tCHCL— * 



y 



■"-tcLCX - * 

tCLCL 



tCHCX* 
-tCLCH 



Figure 23. Clock Signal Waveform for l cc T< 
tCLCH = tCHCL = 5i 



Tests in Active and Idle Modes 

ins 



lcc 



(NC)- 





Vcc 


A. 






RST 


PO 


Vcc 






ES 








XTAL2 










XTAL1 










vss 











Figure 24. I cc Test Condition, Power Down Mode 
All other pins are disconnected. V cc = 2V to 5.5V 



1996 Aug 16 



3-211 



Philips Semiconductors 



Product specification 



CMOS single-chip 8-bit microcontrollers 80C52/80C54/80C58 



Security Bits 

With none of the security bits programmed the code in the program 
memory can be verified. If the encryption table is programmed, the 
code will be encrypted when verified. When only security bit 1 (see 
Table 8) is programmed, MOVC instructions executed from external 
program memory are disabled from fetching code bytes from the 

Table 8. Program Security Bits 



internal memory, ES is latched on Reset and all further programming 
of the EPROM is disabled. When security bits 1 and 2 are 
programmed, in addition to the above, verify mode is disabled. 

Encryption Array 

64 bytes of encryption array are initially unprogrammed (all 1s). 



PROGRAM LOCK BITS 1 ' 2 


I 1 

PROTECTION DESCRIPTION 




SB1 


SB2 


1 


U 


U 


No Program Security features enabled. 

(Code verify will still be encrypted by the Encryption Array if programmed.) 


2 


P 


u 


MOVC instructions executed from external program memory are disabled from fetching code bytes from 
internal memory, EA" is sampled and latched on Reset, and further programming of the EPROM is disabled. 



NOTES: 

1 . P - programmed. U - unprogrammed. 

2. Any other combination of the security bits is not defined. 



80C52 ROM CODE SUBMISSION 

When submitting ROM code for the 80C52, the following must be specified: 

1 . 8k byte user ROM data 

2. 64 byte ROM encryption key 

3. ROM security bits. 



ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


OOOOHtolFFFH 


DATA 


7:0 


User ROM Data 


2000Hto201FH 


KEY 


7:0 


ROM Encryption Key 
FFH = no encryption 


2020H 


SEC 





ROM Security Bit 1 

= enable security 

1 = disable security 


2020H 


SEC 


1 


ROM Security Bit 2 

= enable security 

1 = disable security 



Security Bit 1 : When programmed, this bit has two effects on masked ROM parts: 

1 . External MOVC is disabled, and 

2. EA is latched on Reset. 



Security Bit 2: When pi 



this bit inhibits Verify User ROM. 



If the ROM Code file does not include the options, the following information must be included with the ROM code. 
For each of the following, check the appropriate box, and send to Philips along with the code: 

Security Bit #1: □ Enabled □ Disabled 

Security Bit #2: □ Enabled □ Disabled 

Encryption: □ No □ Yes If Yes, must send key file. 



1996 Aug 16 



3-212 



PrnHi if t cnocifi nation 



80C54 ROM CODE SUBMISSION 

When submitting ROM code for the 80C54, the following must be specified: 

1 . 16k byte user ROM data 

2. 64 byte ROM encryption key 



3. ROM security bits. 



ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


0000H to 3FFFH 


DATA 


7:0 


User ROM Data 


4000H to 401 FH 


KEY 


7:0 


ROM Encryption Key 






FFH = no encryption 


4020H 


SEC 





ROM Security Bit 1 

= enable security 

1 = disable security 


4020H 


SEC 




ROM Security Bit 2 

= enable security 

1 = disable security 



Security Bit 1 : When programmed, this bit has two effects on masked ROM parts: 

1. External MOVC is disabled, and 

2. EA" is latched on Reset. 

Security Bit 2: When programmed, this bit inhibits Verify User ROM. 



If the ROM Code file does not include the options, the following information must be included with the ROM code. 
For each of the following, check the appropriate box, and send to Philips along with the code: 

Security Bit #1: □ Enabled □ Disabled 

Security Bit #2: □ Enabled □ Disabled 

Encryption: □ No □ Yes If Yes, must send key file. 



1996 Aug 16 



3-213 



Philips Semiconductors 



Product specification 



microcontrollers 



80C58 ROM CODE SUBMISSION 

When submitting ROM code for the 80C58, the following must be specified: 

1. 32k byte user ROM data 

2. 64 byte ROM encryption key 

3. ROM security bits. 



f 



If submitting a file, the format is as f< 


>llows: 






ADDRESS 


CONTENT 


BIT(S) 


COMMENT 


0000H to 7FFFH 


DATA 




User ROM Data 


7:0 




8000Hto801FH 


KEY 


7:0 


ROM Encryption Key 
FFH = no encryption 










8020H 


SEC 





ROM Security Bit 1 

= enable security 

1 = disable security 








8020H 


SEC 


1 


ROM Security Bit 2 

= enable security 

1 = disable security 









Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 

1 . External MOVC is disabled, and 

2. EA" is latched on Reset. 

Security Bit 2: When programmed, this bit inhibits Verify User ROM. 



If the ROM code file does not include the options, the following information must be included with the ROM code. 
For each of the following check the appropriate box and send to Philips along with the code: 

Security Bit #1: □ Enabled □ Disabled 

Security Bit #2: □ Enabled □ Disabled 

Encryption: □ No □ Yes If Yes, must send key file. 



1996 Aug 16 



3-214 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



DESCRIPTION 

The 87C54/87C58 Single-Chip 8-Bit Microcontroller is manufactured 
in an advanced CMOS process and is a derivative of the 80C51 
microcontroller family. The 87C54/87C58 has the same instruction 
set as the 80C51. 

This device provides architectural enhancements that make it 
applicable in a variety of applications for general control systems. 
The 87C58 contains 32k x 8 EPROM memory, and the 87C54 
contains 1 6k x 8 EPROM memory, a volatile 256 x 8 read/write data 
memory, four 8-bit I/O ports, three 1 6-bit timer/event counters, a 
multi-source, two-priority-level, nested interrupt structure, an 
enhanced UART and on-chip oscillator and timing circuits. For 
systems that require extra capability, the 87C54/87C58 can be 
expanded using standard TTL compatible memories and logic. 

Its added features make it an even more powerful microcontroller for 
applications that require pulse width modulation, high-speed I/O and 
up/down counting capabilities such as motor control. It also has a 
more versatile serial channel that facilitates multiprocessor 
communications. 

See 80C52/54/58 datasheet for ROM device specification. 
FEATURES 



PIN CONFIGURATIONS 



• 80C51 central processing ui 

• 16kx8EPROMexp 

• 1 6k x 8 EPROM 




to 64k bytes (87C54) 

32k x 8 EPROM expandable externally to 64k bytes (87C58) 

- Improved Quick Pulse programming algorithm 

- Two level program security system 

- 32 byte encryption array 

• 256 x 8 RAM, expandable externally to 64k bytes 

• Three 1 6-bit timer/counters 

- T2 is an up/down counter 

• Four 8-bit I/O ports 

• Full-duplex enhanced UART 

- Framing error detection 

- Automatic address recognition 

• Power control modes 

- Idle mode 

- Power-down mode 

• Once (On Circuit Emulation) Mode 

• Five package styles 

• OTP package available 

• Programmable clock out 

• 6 interrupt sources 

• 2 level priority 



T2/P1.0 QT 
T2EX/P1.1 Q£ 
P1.2 (T 
PI .3 [4 
P1.4 |T 
P1.5 [J 
P1.6 [7 
P1.7 (T 
RST (T 
FUD/P3.0 Qo 
TXD/P3.1 QT 
rNT07P3.2 Qi 
WTT/P3.3 Q5 
T0/P3.4 Q4 
T1/P3.5 Qi 
WR7P3.6 Qi 
HB/P3.7 Q7 
XTAL2 Qi 
XTAL1 Qi 
Vss [2° 



DUAL 
IN-LINE 
PACKAGE 



40] V CC 

39] PO.O/ADO 

38] P0.1/AD1 

37| P0.2/AD2 

36] P0.3/AD3 

35] P0.4/AD4 

34] P0.5/AD5 

33] P0.6/AD6 

32] P0.7/AD7 

|T| EAWpp 

30] ALE/PROG 

29] PSEN 

28] P2.7/A15 

27] P2.6/A14 

26] P2.5/A13 

26] P2.4/A12 

24] P2.3/A11 

23] P2.2/A10 

22] P2.1/A9 

2l| P2.0/A8 



1996 Aug 16 



3-215 



Philips Semiconductors 



Preliminary specification 



8-bit microcontrollers 



87C54/87C58 







ORDERING INFORMATION 



16k x 8 
EPROM 1 


32k x 8 
EPROM 1 




TFMPFR ATURF RANGE °C AND PACKAGE 



FREQUENCY 

int. \ji u t n i 


DRAWING 
NUMBER 


P87C54EBP N 


P87C58EBP N 


OTP 


to +70, 40-Pin Plastic Dual In-line Package 


16MHz 


SOT129-1 


P87C54EBF FA 


P87C58EBF FA 


UV 


to +70, 40-Pin Ceramic Dual In-line Package wAWindow 


16MHz 


0590B 


P87C54EBA A 


P87C58EBA A 


OTP 


to +70, 44-Pin Plastic Leaded Chip Carrier 


16MHz 


SOT187-2 


P87C54EBL KA 


P87C58EBL KA 


UV 


to +70, 44-Pin Ceramic Leaded Chip Carrier wAWindow 


16MHz 


1472 A 


P87C54EBB B 


P87C58EBB B 


OTP 


to +70, 44-Pin Plastic Quad Flat Pack 


16MHz 


SOT307-2 


P87C54EFP N 


P87C58EFP N 


OTP 


-40 to +85, 40-Pin Plastic Dual In-line Package 


16MHz 


SOT129-1 


P87C54EFF FA 


P87C58EFF FA 


UV 


-40 to +85, 40-Pin Ceramic Dual In-line Package wA/Vindow 


16MHz 


0590B 


P87C54EFA A 


P87C58EFA A 


OTP 


-AO to +85, 44-Pin Plastic Leaded Chip Carrier 


16MHz 


SOT 187-2 


P87C54EFB B 


P87C58EFB B 


OTP 


-40 to +85, 44-Pin Plastic Quad Fiat Pack 


16MHz 


SOT307-2 


P87C54IBP N 


P87C58IBP N 


OTP 


to +70, 40-Pin Plastic Dual In-line Package 


24MHz 


SOT129-1 


P87C54IBF FA 


P87C58IBF FA 


UV 


to +70, 40-Pin Ceramic Dual In-line Package w/Window 


24MHz 


0590B 


P87C54IBA A 


P87C58IBA A 


OTP 


to +70. 44-Pin Plastic Leaded Chip Carrier 


24MHz 


SOT187-2 


P87C54IBL KA 


P87C58IBL KA 


UV 


to +70, 44-Pin Ceramic Leaded Chip Carrier wA/Vindow 


24MHz 


1472A 


P87C54IBB B 


P87C58IBB B 


OTP 


to +70, 44-Pin Plastic Quad Rat Pack 


24MHz 


SOT307-2 


P87C54IFP N 


P87C58IFP N 


OTP 


-40 to +85, 40-Pin Plastic Dual In-line Package 


24MHz 


SOT129-1 


P87C54IFF FA 


P87C58IFF FA 


UV 


-40 to +85, 40-Pin Ceramic Dual In-line Package wAVindow 


24MHz 


0590B 


P87C54IFA A 


P87C58IFA A 


OTP 


-40 to +85, 44-Pin Plastic Leaded Chip Carrier 


24MHz 


SOT187-2 


P87C54IFB B 


P87C58IFB B 


OTP 


-40 to +85, 44-Pin Plastic Quad Flat Pack 


24MHz 


SOT307-2 



NOTE: 

1 OTP = One Time Programmable EPROM. UV = Erasable EPROM. 



LOGIC SYMBOL 



T 

X 



RST 



09 




ALE 


z 
o 


RxD ► 




§ 


JxD< 




z 

=1 


INTO — »• 




Ek 


INTT — 




> 


TO — 


CE - 

O 


| 




-'. 




WR< — 






i RTJ< — 




OS 







Vss 



ADDRESS AND 
DATA BUS 



- T2 
T2EX 



ADDRESS BUS 



■ 



1996 Aug 16 



3-216 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 



BLOCK DIAGRAM 



i 

vcc! 



P0.0-P0.7 P2.0-P2.7 



PORT 
DRIVERS 



7Y 



vssl 



1 



t 



PORT 2 
DRIVERS 



RAM ADDR 
REGISTER 


N 


RAM 




PORTO 
LATCH 





V 



I 



ROM/EPROM 



in i 



B 




ACC 


REGISTER 





1 



I 





STACK 




POINTER 



-V ALU <^T_ 









PSW 



P5ER»-I— 
ALE/PR05«-l-« 
EAWpp 
RST" 



TIMING 
AND 
CONTROL 



9 cr 

i 1 
i i 



it it 



SFRs 
TIMERS 



7% 7T 



[xTAL 



HDr— 



PORT 1 
LATCH 



I 



PORT 1 
DRIVERS 



PROGRAM 
ADDRESS 



INCRE- C— !) 
MENTER 



PROGRAM 
COUNTER 



J> DPTR 



PORT 3 
LATCH 



--—in 



JL 



PORT 3 
A DRIVERS 



— " llf 



1996 Aug 16 



3-217 



Philips Semiconductors 



Preliminary specification 




i 8-bit microcontrollers 87C54/87C58 



Table 1 . 87C54/87C58 Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 
MSB LSB 


RESET 
VALUE 


ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


00H 


Al IYD# 
HUAnff 


Auxiliary 


8EH 




| - 


| - 


I - 


| - 


I - 
J 


I - 

J 


AO 
J — 


xxxxxxxOB 




B register 


run 


F7 


F6 


F5 


F4 


F3 


F2 


F1 


FO 


UUn 


DPTR: 
DPH 
DPL 


Data Pointer (2 bytes) 
Data Pointer High 
Data Pointer Low 


83H 
82H 


AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 


00H 
00H 


IE* 


Interrupt Enable 


A8H 


EA 




| ET2 


ES 


I ET1 


| EX1 




| EXO 


00H 








BF 






BC 


















BE 


BD 


BB 


BA 


B9 


B8 
























IP* 


Interrupt Priority 


B8H 






| PT2 


PS 


PT1 


PX1 


| PTO 


| PXO 


XOO00O00B 








87 


86 


85 


84 


83 


82 


81 


80 




PO* 


PortO 


80H 


AD7 


| AD6 


| AD5 


| AD4 


| AD3 


| AD2 


| AD1 


| ADO 


FFH 








97 


96 


95 






92 


91 


90 










94 


93 




P1* 


Portl 


90H 






| " 




| " 


| " 


| T2EX 




FFH 








A7 


A6 


A5 


A4 


A3 


A2 


A1 


AO 




P2* 


rort 2 


AOH 


AD15 


| AD14 


| AD13 


| AD12 


AD11 


AD10 


| AD9 


| AD8 


FFH 








B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 




P3* 


Port 3 


BOH 


RTJ 


WR 


I Ti 


TO 


INTT 


INTO 


| TxD 


| RxD 


FFH 












PCON# 


Power Control 


87H 


SM0D1 


SMODO 


I " 


| POF 1 


GF1 


GFO 


| PD 


IDL 


OOxxxxOOB 








D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 




PSW* 


Program Status Word 


DOH 


CY 


AC 


I ™ 


RS1 


RSO 


OV 


I " 


I P 


00H 


RCAP2H# 
RCAP2L# 
SADDR# 
SADEN# 


Timer 2 Capture High 
Timer 2 Capture Low 
Slave Address 
Slave Address Mask 


CBH 
CAH 
A9H 
B9H 


















00H 
00H 
00H 
00H 


SBUF 


Serial Data Buffer 


99H 


9F 


9E 


9D 


9C 


9B 


9A 


99 


98 


xxxxxxxxB 


SCON* 


Serial Control 


98H 


SMO 


SM1 


SM2 


REN 


TBS 


RB8 




I ™ 


00H 


SP 


Stack Pointer 


81 H 


8F 


8E 


8D 


8C 


8B 


8A 


89 


88 


07H 


TCON* 


Timer Control 


88H 


TF1 


TR1 


TFO 


TRO 


IE1 


IT, 


IE0 


ITO 


00H 








CF 


CE 


CD 


cc 


CB 


CA 


C9 


C8 




T2CON#* 


Timer 2 Control 


C8H 


TF2 


EXF2 


RCLK 


TCLK 


EXEN2 


TR2 


C/T5 


CP7RE2 


00H 


THO 

TH1 

TH2# 

TLO 

TL1 

TL2# 


Timer High 
Timer High 1 
Timer High 2 
Timer Low 
Timer Low 1 
Timer Low 2 


8CH 
8DH 
CDH 
8AH 
8BH 
CCH 


C7 


C6 


C5 


C4 


C3 


C2 


C1 


CO 


00H 
00H 
00H 
00H 
00H 
00H 


TMOD 


Timer Mode 


89H 


GATE 


C/T 


M1 


MO 


GATE 


err 


M1 


MO 


00H 


T2MOD#* 


Timer 2 Mode Control 


C9H 














T20E 


DCEN 


xxxxxxOOB 



* SFRs are bit addressable. 

# SFRs are modified from or added to the 80C51 SFRs. 
1 . Reset value depends on reset source. 



1996 Aug 16 



3~21 8 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 



87C54/87C58 



CERAMIC AND PLASTIC LEADED CHIP CARRIER 
PIN FUNCTIONS 



PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 



JJ Q 

o 



LCC 



□ 2 9 







u 


u 








18 


28 






Pin 


Function 


Pin 


Function 


Pin 


Function 


1 


NC" 


16 


T0/P3.4 


31 


P2.7/A15 


2 


T2/P1.0 


17 


T1/P3.5 


32 


PSER 


3 


T2EX/P1.1 


18 


WR7P3.6 


33 


ALE/PROG 


4 


P1.2 


19 


RTJ/P3.7 


34 


NC" 


5 


P1.3 


20 


XTAL2 


35 


EAWpp 


6 


P1.4 


21 


XTAL1 


36 


P0.7/AD7 


7 


P1.5 


22 


Vss 


37 


P0.6/AD6 


8 


PI .6 


23 


NC" 


38 


P0.5/AD5 


9 


P1.7 


24 


P2.0/A8 


39 


P0.4/AD4 


10 


RST 


25 


P2.1/A9 


40 


P0.3/AD3 


11 


RxD/P3.0 


26 


P2.2/A10 


41 


P0.2/AD2 


12 


NC- 


27 


P2.3/A11 


42 


PO.I/AD1 


13 


TxD/P3.1 


28 


P2.4/A12 


43 


P0.O/ADO 


14 


INT67P3.2 


29 


P2.5/A13 


44 


Voo 


15 


1NTT/P3.3 


30 


P2.6/A14 







• DO NOT CONNECT 



13 
14 
15 



"DO NOT CONNECT 






Function 

P0.6/AD6 


Pin 

31 


32 


P0.5/AD5 


33 


P0.4/AD4 


34 


P0.3/AD3 


35 


P0.2/AO2 


36 


P0.1/AD1 


37 


POO/ADO 


38 


Vcc 


39 


NC* 


40 


T2/P1.0 


41 


T2EX/P1.1 


42 


P1.2 


43 


P1.3 


44 


P1.4 



P0.7/AD7 




1996 Aug 16 



3-219 



PIN DESCRIPTIONS 





PIN NUMBER 






MNEMONIC 


DIP 


LCC 


QFP 


TYPE 


NAME AND FUNCTION 


Vss 


20 


22 


16 


I 


Ground: 0V reference. 


Vcc 


40 


44 


38 


1 


Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 


PO.0-0.7 


39-32 


43-36 


37-30 


I/O 


Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written to them 










float and can be used as high-impedance inputs. Port is also the multiplexed low-order 
address and data bus during accesses to external program and data memory. In this 
application, it uses strong internal pull-ups when emitting 1s. Port also outputs the code 
bytes during program verification and receives code bytes during EPROM programming. 
External pull-ups are required during program verification. 


P1.0-P1.7 


1-8 


2-9 


40-44, 
1-3 


I/O 


Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1 .6 and P1 .7 
which are open drain. Port 1 pins that have 1 s written to them are pulled high by the internal 
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will 
source current because of the internal pull-ups. (See DC Electrical Characteristics: l||_). 
Port 1 also receives the low-order address byte during program memory verification. 
Alternate functions include: 




1 


2 


40 


1 


T2 (P1 .0): Timer/Counter 2 external count input/Clockout 




2 


3 


41 


1 


T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 


P2.0-P2.7 


21-28 


24-31 


18-25 


I/O 


n nr t 1. Dr,rf O io on R hit hirtirnntinnal I/O nnrt with internal nilll-linQ Port 9 nine that hflVP 1^ 
fori r on tZ lo dri o Oil u lull ecu Ul Idl pul I Willi II lief I idl pun Ufja. run £ pnio uiai nave 13 

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 
port 2 pins that are externally being pulled low will source current because of the internal 
pull-ups. (See DC Electrical Characteristics: l||_). Port 2 emits the high-order address byte 
during fetches from external program memory and during accesses to external data memory 
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups 
when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV 
@Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive 
the high order address bits during EPROM programming and verification. 


P3.0-P3.7 


10—1 7 




5 


I/O 


Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1 s 






13-19 


7-13 




written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, 

nnrt O nine thql nrn avIamGlll, Kainn m llIdH Vlfill c/ll irt-n m irrOnt hfl^ai ICO <"lf ttlO Ol lll-l 

port o pins mai are exiernany Deing puiiea low win suuice cuneiii uutdu^H ui me pun uua. 
(See DC Electrical Characteristics: l|ij. Port 3 also serves the special features of the 80C51 
family, as listed below: 




10 


11 


5 


1 


RxD (P3.0): Serial input port 




11 


13 


7 


o 


TxD (P3.1): Serial output port 




12 


14 


8 


1 


INTO (P3.2): External interrupt 




13 


15 


9 


1 


INTT (P3.3): External interrupt 




14 


16 


10 


1 


TO (P3.4): Timer external input 




1 5 


17 


■)-| 


1 


T1 (P3.5): Timer 1 external input 




16 


18 


12 





WR (P3.6): External data memory write strobe 




17 


19 


13 


o 


RD (P3.7): External data memory read strobe 


RST 


9 


10 


4 


1 


Reset: A high on this pin for two machine cycles while the oscillator is running, resets the 
device. An internal diffused resistor to V S s permits a power-on reset using only an external 
capacitor to Vcc- 


ALE/PROG 


30 


33 


27 


I/O 


Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the 
address during an access to external memory. In normal operation, ALE is emitted at a 
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. 












Note that one ALE pulse is skipped during each access to external data memory. This pin is 
also the program pulse input (PROG) during EPROM programming. ALE can be disabled by 






















setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. 


PSEN 


29 


32 


26 


O 


Program Store Enable: The read strobe to external program memory. When the 8XC58 Is 
executing code from the external program memory, PSEN is activated twice each machine 












cycle, except that two PSEN activations are skipped during each access to external data 
memory. PSEN is not activated during fetches from internal program memory. 












EAWpp 


31 


35 


29 


1 


External Access Enable/Programming Supply Voltage: EA must be externally held low to 
enable the device to fetch code from external program memory locations 0000H and 7FFFH. 
If EA is held high, the device executes from internal program memory unless the program 
counter contains an address greater than 7FFFH. This pin also receives the 12.75V 
programming supply voltage (V PP ) during EPROM programming. If security bit 1 is 
programmed, EA will be internally latched on Reset. 


XTAL1 


19 


21 


15 


1 


Crystal 1 : Input to the inverting oscillator amplifier and input to the internal clock generator 
circuits. 


XTAL2 


18 


20 


14 


o 


Crystal 2: Output from the inverting oscillator amplifier. 



NOTE: 

To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V cc + 0.5V or V ss - 0.5V, respectively. 



1996 Aug 16 3-220 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



TIMER 2 

This is a 1 6-bit up or down counter, which can be operated as either 
a timer or event counter. It can be operated in one of three different 
modes (autoreload. capture or as the baud rate generator for the 
UART). 

In the autoreload mode the Timer can be set to count up or down by 
setting or clearing the bit DCEN in the T2CON Special Function 
Register. The SFR's RCAP2H and RCAP2L are used to reload the 
Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1). 

In the Capture mode Timer 2 can either set TF2 and generate an 
interrupt or capture its value. To capture Timer 2 in response to a 
1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON 
must be set. Timer 2 is then captured in SFR's RCAP2H and 
RCAP2L. 

As the baud rate generator, Timer 2 is selected by setting TCLK 
and/or RCLK in T2CON. As the baud rate generator Timer 2 is 
incremented at V 2 the oscillator frequency. 

POWER OFF FLAG 

The Power Off Flag (POF) is set by on-chip circuitry when the V cc 
level on the 8XC58 rises from to 5V. The POF bit can be set or 
cleared by software allowing a user to determine if the reset is the 
result of a power-on or a warm start after powerdown. The V c c level 
must remain above 3V for the POF to remain unaffected by the Vcc 



OSCILLATOR CHARACTERISTICS 

XTAL1 and XTAL2 are the input and output, respectively, of an 
inverting amplifier. The pins can be configured for use as an on-chip 
oscillator. 

To drive the device from an external clock source, XTAL1 should be 
driven while XTAL2 is left unconnected. There are no requirements on 
the duty cycle of the external clock signal, because the input to the 
internal clock circuitry is through a divide-by-two flip-flop. However, 
minimum and maximum high and low times specified in the data 
sheet must be observed. 

Reset 

A reset is accomplished by holding the RST pin high for at least two 
machine cycles (24 oscillator periods), while the oscillator is running. 
To insure a good power-on reset, the RST pin must be high long 
enough to allow the oscillator time to start up (normally a few 
milliseconds) plus two machine cycles. At power-on, the voltage on 
V C c ancl R ST must come up at the same time for a proper start-up. 
Ports 1,2, and 3 will asynchronously be driven to their reset 
condition when a voltage above V| H1 is applied to RESET. 

Idle Mode 

In the idle mode, the CPU puts itself to sleep while all of the on-chip 
peripherals stay active. The instruction to invoke the idle mode is the 
last instruction executed in the normal operating mode before the 



idle mode is activated. The CPU contents, the on-chip RAM, and all 
of the special function registers remain intact during this mode. The 
idle mode can be terminated either by any enabled interrupt (at 
which time the process is picked up at the interrupt service routine 
and continued), or by a hardware reset which starts the processor in 
the same manner as a power-on reset. 

Power-Down Mode 

To save even more power, a Power Down mode can be invoked by 
software. In this mode, the oscillator is stopped and the instruction 
that invoked Power Down is the last instruction executed. The 
on-chip RAM and Special Function Registers retain their values until 
the Power Down mode is terminated. 

On the 8XC58 either a hardware reset or external interrupt can use 
an exit from Power Down. Reset redefines all the SFRs but does not 
change the on-chip RAM. An external interrupt allows both the SFRs 
and the on-chip RAM to retain their values. 

To properly terminate Power Down the reset or external interrupt 
should not be executed before Vcc is restored to its normal 
operating level and must be held active long enough for the 
oscillator to restart and stabilize (normally less than 10ms). 

With an external interrupt, INTO and INT1 must be enabled and 
configured as level-sensitive. Holding the pin low restarts the 
oscillator but bringing the pin back high completes the exit. Once the 
interrupt is serviced, the next instruction to be executed after RETI 
will be the one following the instruction that put the device into 
Power Down. 

Design Consideration 

• When the idle mode is terminated by a hardware reset, the device 
normally resumes program execution, from where it left off, up to 
two machine cycles before the internal rest algorithm takes 
control. On-chip hardware inhibits access to internal RAM in this 
event, but access to the port pins is not inhibited. To eliminate the 
possibility of an unexpected write when Idle is terminated by reset, 
the instruction following the one that invokes Idle should not be 
one that writes to a port pin or to external memory. 

• The windowed parts must be covered with an opaque label to 
assure proper chip operation. 

ONCE™ Mode 

The ONCE ("On-Circuit Emulation") Mode facilitates testing and 
debugging of systems using the 8XC58 without the 8XC58 having to 
be removed from the circuit. The ONCE Mode is invoked by: 

1 . Pull ALE low while the device is in reset and PSEN is high; 

2. Hold ALE low as RST is deactivated. 

While the device is in ONCE Mode, the Port pins go into a float 
state, and the other port pins and ALE and PSEN are weakly pulled 
high. The oscillator circuit remains active. While the 8XC58 is in this 
mode, an emulator or test CPU can be used to drive the circuit. 
Normal operation is restored when a normal reset is applied. 



Table 2. External Pin Status During Idle and Power-Down Mode 



MODE 


PROGRAM 
MEMORY 


ALE 


P5FJJ 


PORTO 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Float 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Float 


Data 


Data 


Data 



1996 Aug 16 



3-221 



Philips Semiconductors 



Preliminary specification 



8-bit microcontrollers 



Programmable Clock-Out 

The 87C54/87C58 has a new feature. A 50% duty cycle clock can 
be programmed to come out on P1 .0. This pin, besides being a 
regular I/O pin, has two alternate functions. It can be programmed 
(1 ) to input the external clock for Timer/Counter 2 or (2) to output a 
50% duty cycle clock ranging from 61 Hz to 4MHz at a 16MHz 
operating frequency. 

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in 
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit 
TR2 (T2CON.2) also must be set to start the timer. 

The Clock-Out frequency depends on the oscillator frequency and 
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) 
as shown in this equation: 

Oscillatoi Frequency 



4 x (65536 - RCAP2H, RCAP2L) 

In the Clock-Out mode Timer 2 roll-overs will not generate an 
interrupt. This is similar to when it is used as a baud-rate generator. 
It is possible to use Timer 2 as a baud-rate generator and a clock 
generator simultaneously. Note, however, that the baud-rate and the 
Clock-Out frequency will be the same. 

Enhanced UART 

The UART operates in all of the usual modes that are described in 
the first section of this book for the 80C51 . In addition the UART can 
perform framing error detect by looking for missing stop bits, and 
automatic address recognition. The 87C54/87C58 UART also fully 
supports multiprocessor communication as does the standard 
80C51 UART. 

When used for framing error detect the UART looks for missing stop 
bits in the communication. A missing bit will set the FE bit in the 
SCON register. The FE bit shares the SCON.7 bit with SMO and the 
function of SCON.7 is determined by PCON.6 (SMOD0) (see 
Figure 1). If SMOD0 is set then SCON.7 functions as FE. SCON.7 
functions as SMO when SMOD0 is cleared. When used as FE 
SCON.7 can only be cleared by software. Refer to Figure 2. 

Automatic Address Recognition 

Automatic Address Recognition is a feature which allows the UART 
to recognize certain addresses in the serial bit stream by using 
hardware to make the comparisons. This feature saves a great deal 
of software overhead by eliminating the need for the software to 
examine every serial address which passes by the serial port. This 
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART 
modes, mode 2 and mode 3, the Receive Interrupt flag (Rl) will be 
automatically set when the received byte contains either the "Given" 
address or the "Broadcast" address. The 9 bit mode requires that 
the 9th information bit is a 1 to indicate that the received information 
is an address and not data. Automatic address recognition is shown 
in Figure 3. 

The 8 bit mode is called Mode 1 . In this mode the Rl flag will be set 
if SM2 is enabled and the information received has a valid stop bit 
following the 8 address bits and the information is either a Given or 
Broadcast address. 

Mode is the Shift Register mode and SM2 is ignored. 

Using the Automatic Address Recognition feature allows a master to 
selectively communicate with one or more slaves by invoking the 
Given slave address or addresses. All of the slaves may be 
contacted by using the Broadcast address. Two special Function 
Registers are used to define the slave's address, SADDR, and the 
address mask, SADEN. SADEN is used to define which bits in the 
SADDR are to b used and which bits are "don't care". The SADEN 
mask can be logically ANDed with the SADDR to create the "IGiven" 



address which the master will use for addressing each of the slaves. 
Use of the Given address allows multiple slaves to be recognized 
while excluding others. The following examples will help to show the 
versatility of this scheme: 



Slave 


SADDR = 


1100 0000 




SADEN = 


1111 1101 




Given 


1100 00X0 


Slave 1 


SADDR = 


1100 0000 




SADEN = 


1111 1110 




Given = 


1100 ooox 



In the above example SADDR is the same and the SADEN data is 
used to differentiate between the two slaves. Slave requires a in 
bit and it ignores bit 1 . Slave 1 requires a in bit 1 and bit is 
ignored. A unique address for Slave would be 1100 0010 since 
slave 1 requires a in bit 1 . A unique address for slave 1 would be 
1 1 00 0001 since a 1 in bit will exclude slave 0. Both slaves can be 
selected at the same time by an address which has bit = (for 
slave 0) and bit 1 = (for slave 1 ). Thus, both could be addressed 
whh 1100 0000. 

In a more complex system the following could be used to select 
slaves 1 and 2 while excluding slave 0: 



Slave 


SADDR 


= 


1100 0000 






SADEN 




1111 1001 






Given 




1100 oxxo 




Slave 1 


SADDR 




1110 0000 






SADEN 




1111 1010 






Given 


= 


1110 oxox 












Slave 2 


SADDR 




1110 0000 






SADEN 




1111 1100 






Given 




1110 ooxx 





In the above example the differentiation among the 3 slaves is in the 
lower 3 address bits. Slave requires that bit = and it can be 
uniquely addressed by 11100110. Slave 1 requires that bit 1 = and 
it can be uniquely addressed by 1110 and 0101 . Slave 2 requires 
that bit 2 = and its unique address is 1110 0011 . To select Slaves 
and 1 and exclude Slave 2 use address 1110 0100, since it is 
necessary t make bit 2 = 1 to exclude slave 2. 

The Broadcast Address for each slave is created by taking the 
logical OR of SADDR and SADEN. Zeros in this result are teated as 
don't-cares. In most cases, interpreting the don't-cares as ones, the 
broadcast address will be FF hexadecimal. 

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR 
address 0B9H) are loaded with 0s. This produces a given address 
of all "don't cares" as well as a Broadcast address of all "don't 
cares", this effectively disables the Automatic Addressing mode and 
allows the microcontroller to use standard 80C51 type UART drivers 
which do not make use of this feature. 

Reduced EMI Mode 

The AO bit (AUXR.0) in the AUXR register, when set, disables the 
ALE output. 

8XC58 Reduced EMI Mode 
AUXR (0X8E) 

_7 6 5 4 3 2 1 

I - I - I - I - I - I - I - ~T~AO~~l 



AO: Turns off ALE output. 



1996 Aug 16 



3-222 



Philips Semiconductors 



Preliminary s| 



CMOS 



lip 8-bit microcontrollers 87C54/87C58 



Interrupt Priority Structure 

The 87C54/87C58 has a 6-source two-level interrupt structure. 
There are 3 SFRs associated with the interrupts. They are the IE 
and IP which are identical in function to those on the 80C51 . 

The priority scheme for servicing the interrupts is the same as that 
for the 80C51 . An interrupt will be serviced as long as an interrupt of 



equal or higher priority is not already being serviced. If an interrupt 
of equal or higher level priority is being serviced, the new interrupt 
will wait until it is finished before being serviced. If a lower priority 
level interrupt is being serviced, it will be stopped and the new 
interrupt serviced. When the new interrupt is finished, the lower 
priority level interrupt that was stopped will be completed. 



Table 3. Interrupt Table 



SOURCE 


POLLING PRIORITY 


REQUEST BITS 


HARDWARE CLEAR? 


VECTOR ADDRESS 


xo 


1 


IE0 


N (L) Y (T) 


03H 


TO 


2 


TPO 


Y 


OB 


X1 


3 


IE1 


N (L) Y (T) 


13 


T1 


4 


TF1 


Y 


1B 


SP 


5 


R1.TI 


N 


23 


T2 


6 


TF2, EXF2 


N 


2B 



SMO 
SM1 



REN 
TBS 
RB8 

Tl 

Rl 



SCON Address = 
Bit Addressable 



98H 



Reset Value = 0000 0000B 



Bit: 



SMO/FE 


SM1 


SM2 


REN 

I 


TB8 


RB8 


Tl 


Rl 


7 


6 


5 


4 


3 


2 


1 






(SMODO = 0/1 )* 
Symbol Function 



Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid 
frames but should be cleared by software. The SMODO bit must be set to enable access to the FE bit. 

Serial Port Mode Bit 0, (SMODO must = to access bit SMO) 



Serial Port Mode Bit 1 
SMO SM1 



Description 

shift register 

8- bit UART 

9- bit UART 
9-bit UART 



Baud Rate" 

f0Sc/12 
variable 



variable 



Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the 
received 9th data bit (RB8) is 1 , indicating an address, and the received byte is a Given or Broadcast Address. 
In Mode 1 , if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a 
Given or Broadcast Address. In Mode 0, SM2 should be 0. 

Enables serial reception. Set by software to enable reception. Clear by software to disable reception. 

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. 

In modes 2 and 3, the 9th data bit that was received. In Mode 1 , if SM2 = 0, RB8 is the stop bit that was received. 
In Mode 0, RB8 is not used. 

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the 
other modes, in any serial transmission. Must be cleared by software. 

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in 
the other modes, in any serial reception (except see SM2). Must be cleared by software. 



NOTE: 

•SMODO is located at PCON6. 
" f osc = oscillator frequency 



Figure 1. SCON: Serial Port Control Register 



1996 Aug 16 



3-223 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 

















<-> 


r 


h / 


















START 
BIT 






DATA BYTE 








ONLY IN 
MODE 2, 3 


STOP 
BIT 



SET FE BIT IF STOP BIT IS (FRAMING ERROR) 
SMO TO UART MODE CONTROL 



SMO/FE 




SM2 


RFIM 


TBS 


RB8 


Tl 


Rl 













SCON 
(98H) 













GFO | GF1 


,r,, 1 PCON 


SMODI 


SMODO 


OSF 


POF 


LVF 


| (87H) 



: SCON.7 = SMO 

1 : SCON.7 = FE 



Figure 2. UART Framing Error Detection 




3 DO TO D7 
PROGRAMMED ADDRESS 



IN UART MODE 2 OR MODE 3 AND SM2 . 1: 

INTERRUPT IF REN=1. RB8=I AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" 

- WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES 

- WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. 



Figure 3. UART Multiprocessor Communication, Automatic Address Recognition 



ABSOLUTE MAXIMUM RATINGS 12 3 



PARAMETER 


RATING 


UNIT 


Operating temperature under bias 


to +70 or -40 to +85 




Storage temperature range 


-65 to +150 


°c 


Voltage on EAWpp pin to Vss 


to +13.0 


V 


Voltage on any other pin to Vss 


-0.5 to +6.5 


V 


Maximum Iol P er 1^0 P' n 


15 


mA 


Power dissipation 

(based on package heat transfer limitations, not device power consumption) 


1.5 


W 



NOTES: 



1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V S s unless otherwise 
noted. 



1996 Aug 16 



3-224 



Preliminary specification 



CMOS J 



lip 8-bit microcontrollers 



87C54/87C58 



DC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C, V C c = 5V±10%, V ss = OV 



SYMBOL 


PARAMETER 


TEST 
CONDITIONS 


LIMITS 


UNIT 


MIN 


TYP 1 


MAX 


V|L 


Input low voltage, except EA~ 




-0.5 




0.2V CC -0.1 


V 


Vy 


Input low voltage to EA" 









0.2Vcc-0.3 


V 


Vim 


Input high voltage, XTAL1 , RST 




0.7V CC 




Vcc+0.5 


V 


Vol 


Output low voltage, ports 1 , 2, 3 7 


l 0L = 1.6mA 2 






0.45 


V 


Voli 


Output low voltage, port 0, ALE, PSEN' 


lot » 3.2mA 2 






0.45 


V 


Voh 


Output high voltage, ports 1 , 2, 3 3 


l 0H = -30uA 


Vcc-0.7 






V 


Vohi 


Output high voltage (port in external bus mode), 


Ioh = -3.2mA 


Vcc-0.7 






V 




ALE 8 , PSEN 3 










IlL 


Logical input current, ports 1 , 2, 3 


V| N = 0.4V 






-50 


HA 


TO. 


Logical 1 -to-0 transition current, ports 1 , 2, 3 5 


See note 4 






-650 


HA 


lu 


Input leakage current, port 


0.45 V IN <V CO -0.3 






±10 


HA 


Ice 


Power supply current (See Figure 11 ): 
Active mode @ 16MHz 
Idle mode @ 16MHz 

Power-down mode T amb = to +70°C 
T amb = -40to + 85°C 


See note 10 




15 
3 
10 


32 
5 
75 
100 


mA 
mA 
uA 
HA 


R RST 


Internal reset pull-down resistor 




40 




225 


kQ 




Pin capacitance 9 (except EA") 








15 


pF 



NOTES 

1 

2 



Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 

Capacitive loading on ports and 2 may cause spurious noise to be superimposed on the V lS of ALE and ports 1 and 3. The noise is due 
to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the 
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify 
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I l can exceed these conditions provided that no 
single output sinks more than 5mA and no more than two outputs exceed the test conditions. 

3. Capacitive loading on ports and 2 may cause the V h on ALE and PSEN to momentarily fall below the 0.9V CC specification when the 
address bits are stabilizing. 

4. Pins of ports 1 , 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its 
maximum value when V| N is approximately 2V. 

5. This value applies to T^ = 0°C to +7 0°C, Fo r T amb = -40°C to 85°C, l TL = -750uA 

6. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

7. Under steady state (non-transient) conditions, I l must be externally limited as follows: 

Maximum I l per port pin: 1 5mA 

Maximum let per 8-bit port: 26mA 

Maximum total Iol 'or all outputs: 71 mA 
If Iol exceeds the test condition, V l may exceed the related specification. Pins are not guaranteed to sink current greater than the listed 
test conditions. 

ALE is tested to V OH1 , except when ALE is off then V h is the voltage specification. 

9. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 1 5pF 
(except ES it is 25pF). 

1 0. See Figures 1 2 through 1 5 for l C c test condition. 



8 



1996 Aug 16 



3-225 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70°C or -40°C to + 85»C, V cc = 5V ±1 0%, V SS = 0V 1 ■ 2 - 3 



SYMBOL 


FIGURE 


PARAMETER 


16MHz CLOCK 


VARIABLE CLOCK 


UNIT 


MIN 


MAX 


MIN 


MAX 


1/tcLCL 


4 


Oscillator frequency 

Speed versions : E 






3.5 


16 


MHz 






M.HLL 


4 


ALE pulse width 


85 




2tcLCL-40 




ns 


*AVLL 


4 


Address valid to ALE low 


22 




tcLCL-40 




ns 


Illax 


4 


Address hold after ALE low 


32 




tCLCL-30 




ns 


'lLIV 


4 


ALE low to valid instruction in 




150 




4 tCLCL- 1 0° 


ns 


'llpl 


4 


ALE low to PSEN low 


32 




tcLCL-30 




ns 


tpLPH 


4 


PSEN pulse width 


142 




3tCLCL-<t5 




ns 


tpLIV 


4 


PSEN low to valid instruction in 




82 




3tCLCL-1°5 


ns 


tpxix 


4 


Input instruction hold after PSEN 












ns 


tpxiz 


4 


Input instruction float after PSEN 




37 




tci_CL-25 


ns 


Iaviv 


4 


Address to valid instruction in 




207 




5tcLCL-105 


ns 


'PLAZ 


4 


PSEN low to address float 




10 




10 


ns 


Data Memory 


Irlrh 


5,6 


RD pulse width 


275 




6tCLCL-100 




ns 


'WLWH 


5,6 


WR pulse width 


275 




6tcLCL-100 




ns 


Irldv 


5,6 


RD low to valid data in 




147 




5tciCL-165 


ns 


(rhdx 


5, 6 


Data hold after RD 











ns 


*RHDZ 


5, 6 


Data float after RD 




65 




2tcLCl-60 


ns 


l LLDV 


5, 6 


ALE low to valid data in 




350 




8tcLCL-150 


ns 


*AVDV 


5,6 


Address to valid data in 




397 




9t0LCL-165 


ns 


•llwl 


5, 6 


ALE low to RD or WR low 


137 


239 


3tCLCL-50 


3tcLCL+50 


ns 


*AVWL 


5,6 


Address valid to WR low or RD low 


122 




4ICLCL-130 




ns 


tQVWX 


5,6 


Data valid to WR transition 


13 




tcLCL-50 




ns 


IWHQX 


5,6 


Data hold after WR 


13 




tcLCL-50 




ns 


•qvwh 


6 


Data valid to WR high 


287 




7tcLCL-150 




ns 


tRLAZ 


5, 6 


RD low to address float 












ns 


'WHLH 


5, 6 


RD or WR high to ALE high 


23 


103 


tcLCL-*0 


tcLCL+4" 


ns 


External Clock 


tcHCX 


8 


High time 


20 




20 


tCLCL+tcLCX 


ns 


tCLCX 


8 


Low time 


20 




20 


'CLCL+tCHCX 


ns 


'OLCH 


8 


Rise time 




20 




20 


ns 


'CHCL 


8 


Fall time 




20 




20 


ns 


Shift Register 


'XLXL 


7 


Serial port clock cycle time 


750 




12t CLCL 




ns 


Iqvxh 


7 


Output data setup to clock rising edge 


492 




10tcLCL-133 




ns 


txHQX 


7 


Output data hold after clock rising edge 


8 




2ICLCL-117 




ns 


•XHDX 


7 


Input data hold after clock rising edge 












ns 


l XHDV 


7 | Clock rising edge to input data valid 




492 




10tc L CL-133 | ns 



1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other outputs = 80pF. 

3. Interfacing the 8XC58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port drivers. 



1996 Aug 16 



3-226 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



AC ELECTRICAL CHARACTERISTICS 

Tamb = 0°C to +70-C or -40°C to +85°C, V cc = 5V ±1 0%, V SS = OV 1 ■ 2 ' 3 









24MHz CLOCK 


VARIABLE CLOCK 4 




SYMBOL 


FIGURE 


PARAMETER 


MIN 


MAX 


MIN 


MAX 


UNIT 


1 /tcLCL 


4 


Oscillator frequency 

Speed versions : I 






3.5 




MHz 


'lhu 


4 


ALE pulse width 


43 




2tcLCL-^0 




ns 


*AVLL 


4 


Address valid to ALE low 


17 




tcLCL- 25 




ns 


•llax 


4 


Address hold after ALE low 


17 




tcLCL-25 




ns 


'luv 


4 


ALE low to valid instruction in 
ALE low to F5EN low 


17 


102 




4 tcLCL-65 


ns 


'llpl 

tpLPH 


4 
4 


PSEN pulse width 


80 




toLCL-25 
3*CLCL-45 




ns 
ns 


tpLIV 


4 


PSEN low to valid instruction in 




65 




3tcLCL~60 


ns 


tpxix 


4 


Input instruction hold after PSEN 












ns 


f PXI2 


4 


Input instruction float after PSEN 




17 




tcLCL-25 


ns 


Wiv 


4 


Address to valid instruction in 




128 




5tcLCL-80 


ns 


tpLAZ 


4 


PSER low to address float 




10 




10 


ns 


Data Memory 


•rlrh 


5,6 


RD pulse width 


150 




6tCLCL-100 




ns 


*WLWH 


5,6 


WR pulse width 


150 




6tcLCL- 100 




ns 


tRLDV 


5, 6 


RD low to valid data in 




118 




5tcLCL"90 


ns 


*RHDX 


5,6 


Data hold after RD 












ns 


*RHDZ 


5, 6 


Data float after RD 




55 




2t C LCL-28 


ns 


tLLOV 


5,6 


ALE low to valid data in 




183 




8tciXL-150 


ns 


<AVDV 


5,6 


Address to valid data in 




210 




9tcLCL-165 


ns 


'llwl 


5,6 


ALE low to RD or WR low 


75 


175 


3tCLCL-50 


3tcLCL+50 


ns 


Uvwl 


5,6 


Address valid to WR low or RD low 


92 




4tcLCL-75 




ns 


tQVWX 


5,6 


Data valid to WR transition 


12 




tcLCL- 30 




ns 


twHQX 


5,6 


Data hold after WR 


17 




•cLCL-25 




ns 


<QVWH 


6 


Data valid to WR high 


162 




7tci_CL-130 




ns 


tRLAZ 


5, 6 


RD low to address float 












ns 


•WHLH 


5,6 


RD or WR high to ALE high 


17 


67 


to|_CL-25 


*CLCL+25 


ns 


External Clock 


*CHCX 


8 


High time 


17 




17 


tCLCL-tCLCX 


ns 


tCLCX 


8 


Low time 


17 




17 


*CLCL-tCHCX 


ns 


'CLCH 


8 


Rise time 




5 




5 


ns 


*CHCL 


8 


Fall time 




5 




5 


ns 


Shift Register 


'XLXL 


7 


Serial port clock cycle time 


505 




12tcLCL 




ns 


tQVXH 


7 


Output data setup to clock rising edge 


283 




10tcLCL-133 




ns 


*XHQX 


7 


Output data hold after clock rising edge 


3 




2tcLCL-«0 




ns 


•XHDX 


7 


Input data hold after clock rising edge 












ns 


*XHDV 


7 


Clock rising edge to input data valid 








IOtcLCL-133 






283 
1 




ns 



,«vy ■ to. 

1 . Parameters are valid over operating te mpera ture range unless otherwise specified. 

2. Load capacitance for port 0, ALE, and PSEN = 1 0OpF, load capacitance for all other output 

3. Interfacing the 87C58 to devices with float times up to 45ns is permitted. This limited bi- - 

4. Variable clock is specified for oscillator frequencies greater than 1 6MHz to 24MHz. For 
"AC Electrial Characteristics", page 3-226. 



:s = 80pF. 



ntion will not cause damage to Port drivers, 
equal or less than 1 6MHz, see 1 6MHz 



1996 Aug 16 



3-227 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



EXPLANATION OF THE AC SYMBOLS 

Each timing symbol has five characters. The first character is always 
f (= time). The other characters, depending on their positions, 
indicate the name of a signal or the logical status of that signal. The 
designations are: 
A - Address 
C - Clock 
D- Input data 
H - Logic level high 

I - Instruction (program memory contents) 
L - Logic evel low, or ALE 



P - P5ER 
Q - Output data 
R - RD signal 
t - Time 
V - Valid 
W- WR signal 

X - No longer a valid logic level 
Z - Float 

Examples: t AVLL = Time for address vali d to AL E low. 

t|_LPL =Time for ALE low to PS EN low. 



'lhll 




PORT 2 



>*5 



*AVLL 



y v_ 



*LLPL 



tpLPH 



*LLIV ' 

tpLIV, 



'llax 



" tpLAZ 



Wiv 



tpxix " 



> ( INSTR IN 



- tpxiz- 



X 



SU00006\ 



Figure 4. External Program Memory Read Cycle 




8 



1996 Aug 16 



3-228 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



PSER yf~ 



Wll 



port o \ t\„..?a?i.J'y / ~ 

y V FROMHIORDPL A\ 



X 



*~ >WHLH 



•llax 



tAVWL 



\ 



tWLWH 



tQVWX 



"X / 



/ 



tQVWH 



DATA OUT 



*~ twHQX 



XX 



A0-A7 FROM PCL 



>x 



P2.0-P2.7 OR A8-A15 FROM DPF 



X 



A0-A15 FROM PCH 



Figure 6. External Data Memory Write Cycle 



NSTRUCTION 
ALE 



I » I ' I * I j | 4 | 5 | 6 | 7 | . | 

JLJIJIJIJIJIJIJIJIJIJ^^ 

\*~ tXLXL -*| 

~i_r 



OUTPUT DATA . 



tQVXH 



~H h" *XHQX 



WRITE TO SBUF 



txHDvH^^ ,XHDX 



t 

SETT1 



t 

CLEAR Rl 



t 

SET Rl 



Figure 7. Shift Register Mode Timing 



vcc-o-5 ■ 

"* X 0.7V CC 

0.45V r 0.2VCC-01 

•CHCL— *■ 



y 



*-t C LCX-*' 

tCLCL 



«-tCHCX-»- 
*CLCH 



Figure 8. External Clock Drive 



1996 Aug 16 



Preliminary specification 



lip 8-bit microcontrollers 87C54/87C58 





NOTE: 

AC inputs during testing are driven at V c c -0-5 for a togic T and 0.45V for a logic '0'. 
Timing measurements are made at V| H min lor a logic 'V and V !L max for a logic '0'. 



VloaD+0' 



VLOAD - 



VLOAD-01V 



K 

iv V_ 



TIMING jf 
REFERENCE ^ 
POINTS 



>: 



VOH-01V 
V O L*0 1V 



NOTE: 

For timing purposes, a port is no longer floating when a 100mV change from 
load voltage occurs, and begins to float when a 100mV change from the loaded 
Voh/Vol level occurs. Ioh/'ol ^ ±2umA. 

SU00718 



Figure 9. AC Testing Input/Output 



Figure 10. Float Waveform 



ICC m A 



10 




Figure 11. I cc vs. Frequency 



MAX ACTIVE MODE 
ICCMAX=' 50 X FREQ. - 



TYP ACTIVE MODE 
0.9 X FREQ. ♦ 2.5 



MAX IDLE MODE 
TYP IDLE MODE 



1996 Aug 16 



3-230 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 



Vcc 



Vcc 

HST 



(NO- 



CLOCK SIGNAL - 



\l 



XTAL2 
XTAL1 
Vss 



ES « 1 



(NO- 
CLOCK SIGNAL - 



11 







Vcc 

PO 



XTAU 
XTAL1 

v ss 



Ice 

I 



SU00720 



Figure 12. Ice Test Condition, Active 
All other pins are disconnected 




Figure 13. I cc Test Condition, Idle Mode 
All other pins are disconnected 




■ 

vcc-o-5 - 



i — r 



0.7VCC 
0.2VCC-0. . 

rteHgr* 

tCHCL— ► |«-tcLCX-»j f« — toLCH 



•CLCL 







I Waveform for l^c Tests in Active and idle 
tcLCH = tcHCL = 5ns 







Vcc 



tec 



(NO- 





Vcc 




RST 






PO 






XTAL2 




XTAL1 




vss 





Vcc 



Figure 15. Icc Test Condition, Power Down Mode 
All other pins are disconnected. V cc = 2V to 5.5V 



1996 Aug 16 



3-231 



Philips Semiconductors 



Preliminary specification 



CMOS single-chip 8-bit microcontrollers 87C54/87C58 



EPROM CHARACTERISTICS 

The 87C58 is programmed by using a modified Improved 
Quick-Pulse Programming™ algorithm. It differs from older methods 
in the value used for V PP (programming supply voltage) and in the 
width and number of the ALE 



le 87C58 contains two signature bytes that can be read and used 
by an EPROM programming system to identify the device. The 
signature bytes identify the device as an 87C58 manufactured by 
Philips. 

Table 4 shows the logic levels for reading the signature byte, and for 
programming the program memory, the encryption table, and the 
security bits. The circuit configuration and waveforms for quick-pulse 
programming are shown in Figures 16 and 17. Figure 18 shows the 
circuit configuration for normal program memory verification. 

Quick-Pulse Programming 

The setup for microcontroller quick-pulse programming is shown in 
Figure 16. Note that the 87C58 is running with a 4 to 6MHz 
oscillator. The reason the oscillator needs to be running is that the 
device is executing internal address and program data transfers. 

The address of the EPROM location to be programmed is applied to 
ports 1 and 2. as shown in Figure 1 6. The code byte to be 
programmed into that location is applied to port 0. RST, PSEN and 
pins of ports 2 and 3 specified in Table 4 are held at the 'Program 
Code Data' levels indicated in Table 4. The ALE/PROG is pulsed 
low 5 times as shown in Figure 17. 

To program the encryption table, repeat the 25 pulse programming 
sequence for addresses through 1 FH, using the 'Pgm Encryption 
Table' levels. Do not forget that after the encryption table is 
programmed, verification cycles will produce only encrypted data. 

To program the security bits, repeat the 25 pulse programming 
sequence using the 'Pgm Security Bit' levels. After one security bit is 
programmed, further programming of the code memory and 
encryption table is disabled. However, the other security bit can still 
be programmed. 

Note that the EA7V PP pin must not be allowed to go above the 
maximum specified V PP level for any amount of time. Even a narrow 
glitch above that voltage can cause permanent damage to the 
device. The V PP source should be well regulated and free of glitches 
and overshoot. 

Program Verification 

If security bit 2 has not been programmed, the on-chip program 
memory can be read out for program verification. The address of the 
program memory locations to be read is applied to ports 1 and 2 as 



low the 
s verification 



shown in Figure 18. The other pins are held at the 'Verify Code Data' 
levels indicated in Table 4. The contents of the address location will 
be emitted on port 0. External pull-ups are required on port for this 
operation. 

If the 32 byte encryption table has been programmed, the data 
presented at port will be the exclusive NOR of the program byte 
with one of the encryption bytes. The user will have to know the 
encryption table contents in order to correctly decode the v 
data. The encryption table itself cannot be read out. 

Program/Verify Algorithms 

Any algorithm in agreement with the conditions listed in Table 4, and 
which satisfies the timing specifications, is suitable. 

Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is exposed to 
light with wavelengths shorter than approximately 4,000 angstroms. 
Since sunlight and fluorescent lighting have wavelengths in this 
range, exposure to these light sources over an extended time (about 
1 week in sunlight, or 3 years in room level fluorescent lighting) 
could cause inadvertent erasure. For this and secondary effects, 
it is recommended that an opaque label be placed over the 
window. For elevated temperature or environments where solvents 
are being used, apply Kapton tape Fluorglas part number 2345-5, 
equivalent. 

The recommended erasure procedure is exposure to ultraviolet light 
(at 2537 angstroms) to an integrated dose of at least 15W-s/cm 2 . 
Exposing the EPROM to an ultraviolet lamp of 12,000|iW/cm 2 rating 
for 20 to 39 minutes, at a distance of about 1 inch, should be 
sufficient. 

Erasure leaves the array in an all 1s state. 
Security Bits 

With none of the security bits programmed the code in the program 
memory can be verified, if the encryption table is programmed, the 
code will be encrypted when verified. When only security bit 1 (see 
Table 5) is programmed, MOVC instructions executed from external 
program memory are disabled from fetching code bytes from the 
internal memory, EA is latched on Reset and all further programming 
of the EPROM is disabled. When security bits 1 and 2 are 
programmed, in addition to the above, verify mode is disabled. 
When all three security bits are programmed, all of the conditions 
above apply and all externa] program memory execution is disabled. 



its 

,or 



Encryption Array 

32 bytes of encryption array are initially unprogrammed (all 1s). 



""Trademark phrase of Intel Corporation. 
1996 Aug 16 



3-232 



Philips Semiconductors 



Preliminary specification 



Table 4. EPROM Programming Modes 



MODE 


RST 


P5EN 


ALE/PROG 


EWVpp 


P2.7 


P2.6 


P3.7 


P3.6 


P3.3 


Read signature 


1 





1 


1 

















Program code data 


, 1 





0* 


V PP 


1 





1 


1 


1 


Verify code data 


1 





1 


1 








1 


1 





Pgm encryption table 


1 





0* 


Vpp 


1 





1 





1 


Pgm security bit 1 


1 





0* 


Vpp 


1 


1 


1 


1 


1 


Pgm security bit 2 


1 





0* 


Vpp 


1 


1 








1 



NOTES: 

1 . '0' = Valid low for that pin, T = valid high for that pin. 

2. Vpp = 12.75V ±0.25V. 

3. V oc = 5V±1 0% during programming and verification. 

* ALE/PROG receives 5 programming pulses (only for user array; 25 pulses for encryption or security bits) while Vpp is held at 12.75V. Each 
programming pulse is low for 100ns (±10us) and high for a minimum of 10ns. 



Table 5. Program Security Bits 



PROGRAM LOCK BITS 1 ' 2 


PROTECTION DESCRIPTION 




SB1 


SB2 


1 


U 


U 


No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if 
programmed.) 


2 


P 


u 


MOVC instructions executed from external program memory are disabled from fetching code bytes from 
internal memory, EA" is sampled and latched on Reset, and further programming of the EPROM is disabled. 


3 


P 


P 


Same as 2, also verify is disabled. 



NOTES: 

1 . P - programmed. U - unprogrammed. 

2. Any other combination of the security bits is not defined. 



1996 Aug 16 



3-233 



Philips Semiconductors 



i 8-bit microcontrollers 87C54/87C58 



A0-A7 

1 
1 
1 



pi 

RST 
P3.6 
P3.7 
P3.3 
XTAL2 



vcc 

PO 

EAWpp 
ALE/PHOG 
PSEFI 

P2.7 
P2.6 
P2.0-P2.5 



V 



♦12.75V 

5 100tlsPULSESTOGROL 



V 



A6-A13 
A14 



Figure 16. Programming Configuration 



ALDPHOG: 




Figure 17. PROG Waveform 



-N 
V 



RST 

P3.6 
P3.7 
P3.3 



87C54 
87C58 



Vcc 

PO 

EWpp 
ALE/PROG 

P5EH 

P2.7 
P2.6 
P2.0-P2.5 
P3.4 



> 



V 



AS-A13 
A14 



Figure 18. Program Verification 



1996 Aug 16 



3-234 



Philips Semiconductors 



Preliminary specification 




CMOS single-chip 8-bit microcontrollers 



87C54/87C58 



EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS 

\mb = 21 °C to +27°C, V cc = 5V±1 0%, V ss = 0V (See Figure 1 9) 



SYMBUL 


DA D A UCTCD 

KAnAMt 1 tn 


MIPJ 


MAA 


1 IKJIT 


V PP 


Programming supply voltage 


1 2.5 


13.0 


V 


lp P 


Programming supply current 




cn 1 


mA 


ItCLCL 




Oscillator frequency 


4 


6 


MHz 


tAVGL 


Address setup to PROG low 


48tci_cL 






Ighax 


Address hold after PROG 


4 8tcL_CL 






tovGL 


Data setup to PROG low 


48tc LCL 






tGHDX 


Data hold after PROG 


48tci_CL 






'ehsh 


P2.7 (ENABLE) high to V PP 


48t CL CL 






tsHGL 


V P p setup to PROG low 


10 




MS 


tGHSL 


V PP hold after PROG 


10 




lis 


tGLGH 


PROG width 


90 


110 


US 


*AVQV 


Address to data valid 




4StcLCL 




tELQZ 


ENABLE low to data valid 




48tcLCL 




( EHQZ 


Data float after ENABLE 





48tci_CL 




f GHGL 


PROG high to PROG low 


10 




lis 



NOTE: 

1. Not tested. 



P1.0-P1.7 
P2.0-P2.5 
P3.4 
(A0-A14) 



PORTO 
P0.0-P0.7 
(DO-D7) 



ALE/PROG 



— c 





'dvgl 
'avgl 



PROGRAMMING 



ADDRESS 



> 



< 



*GLGH 
'SHGL 



EAWpp - 



tEHSH 



> 



VERIFICATION 



< 



> 



tGHDX 
t&HAX 



tGHGL 



tGHSL 



LOGIC 1 



'elqv 



Wqv 



> 



LOGIC 1 



FOR PROGRAMMING VERIFICATION SEE FIGURE 16. 
FOR VERIFICATION CONDITIONS SEE FIGURE 18. 

Figure 19. EPROM Programming and Verification 



1996 Aug 16 



3-235 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video 



83C145; 83C845 
83C055; 87C055 



1 FEATURES 

• Masked ROM sizes: 

- 8 kbytes (83C845) 

- 12 kbytes (83C1 45) 

- 16 kbytes (83C055) 

- 16 kbytes OTP (87C055) 

• RAM: 256 bytes 

• On Screen Display (OSD) controller 

• Three digital video outputs 

• Multiplexer/mixer and background intensity controls 

• Flexible formatting with OSD New Line option 

• 128 x 1 bits display RAM 

• Designed for reduced Radio Frequency Interference 
(RFI) 

• Character generator ROM: 

- character format 1 8 lines x 1 4 dots 

- 60 visible characters 

- 4 special characters 

• Eight text shadowing modes 

• Text colour selectable per character 

• Background colour selectable per word 

• Background colour versus video selectable per 
character 

• Eight 6-bit Pulse Width Modulators (PWM) for analog 
voltage integration 

4 ORDERING INFORMATION 



• One 14-bit PWM for high-precision voltage integration 

• Digital-to-analog converter and comparator with 3 inputs 
multiplexer 

• Nine dedicated l/Os plus 28 port bits (15 port bits with 
alternative uses) 

• 4 high current open-drain port outputs 

• 12 high voltage (+12 V) open-drain outputs 

• Programmable video input and output polarities 

• 80C51 instruction set 

• No external memory capability 

Plastic shrink dual in-line package (0.07 inch centre 



pins) 

• High-speed CMOS technology 

• Power supply: 5 V ±1 0%. 

2 DESCRIPTION 



The 83C055, Microcontroller for Television and Video 
(MTV) applications, is a derivative of Philips' industry 
standard 80C51 microcontroller. 

The 83C055 is intended for use as the central control 
mechanism in a television receiver or tuner. 



3 APPLICATIONS 

Providing tuner functions and an OSD facility, it represents 
a next generation replacement for the currently available 
parts. 



TYPE NUMBER 


PACKAGE 


TEMP. 
RANGE 

<°C) 


FREQ. 
(MHz) 


NAME 


DESCRIPTION 


VERSION 


P83C055BBP 
P87C055BBP 
P83C145BBP 
P83C845BBP 


SDIP42 


plastic shrink dual in-line package; 42 leads (600 mil) 


SOT270-1 


to +70 


3.5 to 12 



1996 Mar 22 3-236 



Philips Semiconductors Product specification 



Microcontrollers for TV and video (MTV) 




83C145; 83C845 
83C055; 87C055 


5 BLOCK DIAGRAM 



V DD" 

XTAL1_ 
(IN) 



XTAL2 
(OUT) - 



TO INT1 



INT1 INTO 



8-BIT 
TIMER / 
EVENT 
COUNTER 



80C51 
core 
excluding 
ROM / RAM 



BF VID1 VCTRL VCLK1 HSYNC 
VID2I VIDO I VCLK2 I VSYNC 
I | | 



ROM 
(1) 



31 



RAM 
256 bytes 



DISPLAY 

RAM 
128 x 10 



CHARACTER 
GENERATOR 

ROM 
60x18x14 



ffi B-bit ii 



PARALLEL 
I/O 
PORTS 



VV<> O 

P3 P2 P1 PO 



8 x 6-BIT PWM 



7> 



14-BIT 
PWM 



V 

PWMO to PWM7 



SOFTWARE 
CONTROL 
ADC 



7% 



ADI2 to ADIO 



(1) ROM sizes: see Table 1 . 

Fig.1 Block diagram. 


5.1 Part options 



Table 1 Differences between the types 



MEMORY 


TYPES 


83C845 


83C145 


83C055 


87C055 


ROM 


8 kbytes 


12 kbytes 


16 kbytes 




EPROM (OTP) 








16 kbytes 



1996 Mar 22 



3-237 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



6 PINNING INFORMATION 
6.1 Pinning 



Vpp/TDAC/PO.O [T 
PROQ/PWM1/P0.1 |T 
ASEL/PWM2/P0.2 (T 
PWM3/P0.3 [T 
PWM4/P0.4 [T 
PWM5/P0.5 \T 
PWM6/P0.6 |T 
PWM7/P0.7 |T 
ADI0/P1.0 [T 
ADI1/P1.1 [lO 
ADI2/P1.2 QT 
PWM0/P1.3 [l2 
P2.7 Q3 
P2.6 [l4 
P2.5 Qi 
P2.4 [l6 
P2.3 Q7 
P2.2 [l8 
P2.1 [l9 
P2.0 [M 

v ss[ll 



83C145 
83C845 
83C055 
87C055 



H V DD 

41]P3.7 

401p3.6 

39lP3.5 

38|P3.4 

37] P3.3/INT0 

36| P3.2/T0 

35]P3.1/INT1 

34]P3.0 

33]rST 

32|xTAL2 

3?|XTAL1 

3o1bF 

29]VCLK2 

28]VCLK1 

27|VSYNC 

26] HSYNC 

25] VCTRL 

24]VID2 

23]vlD1 

22]VID0 



Fig.2 Pin configuration (SOT270-1). 



1996 Mar 22 



3-238 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



6.2 Pin description 






Table 2 Pin description SDIP42 (SOT270-1) 




SYMBOL 


PIN 


DESCRIPTION 




Port (notes 1 , 2 and 4) 






PO.O/TDAC/Vpp 


1 


P0.0: open-drain bidirectional port line; 

TDAC: output for the 14-bit high-precision PWM; 

V PP : 12 V programming supply voltage during EPROM programming. 


P0.1/PWM1/PROG 


2 


P0.1 : open-drain bidirectional port line; 

PWM1 : output for the 6-bit lower-precision PWM; 

PROG: input for EPROM programming pulses. 




P0.2/PWM2/ASEL 


3 


P0.2: open-drain bidirectional port line; 






PWM2: output for the 6-bit lower-precision PWM; 

ASEL: input indicating the EPROM address bits that are applied to Port 2. 


P0.3/PWM3 
to 


4t0 8 


P0.3 to P0.7: 5 open-drain bidirectional port lines; 

PWM3 to PWM7: 5 outputs for the 6-bit lower-precision PWM. 




P0.7/PWM7 








Port 1 (notes 1 , 2 and 5) 






P1.0/ADI0 
to 


9 to 11 


P1.0 to P1.2: 3 open-drain bidirectional port lines; 

ADIO to ADI2: inputs for the software analog-to-digital facility. 




P1.2/ADI2 








P1.3/PWM0 


12 


P1.3: open-drain bidirectional port line; PWMO: output for the 6-bit lower-precision 
PWM. PWMO can be externally pulled up as high as +12 V ±5% 


Port 2 


P2.7 to P2.0 


13 to 20 


Port 2; 8-bit open-drain bidirectional port; P2.3 to P2.0 have high current capability 
(1 mA at 0.5 V) for driving LEDs. Port 2 pins that have logic 1 s written to them float, 
and in that state can be used as high-impedance inputs. Any of the Port 2 pins are 
driven LOW if the port register bit is written as a logic 0. The state of the pin can 
always be read from the port register by the program. 


Port 3 (note 1 and 3) 






P3.0 


34 


P3.0: open-drain bidirectional port line. 


P3.1/INT1 


35 


P3.1 : open-drain bidirectional port line; INT1 : External interrupt 1 . 


P3.2/T0 


36 


P3.2: open-drain bidirectional port line; TO: Timer external input. 


P3.3/INT0 


37 


P3.3: open-drain bidirectional port line; INTO: External interrupt 0. 


P3.4 to P3.7 


38 to 41 


P3.4 to P3.7: 4 open-drain bidirectional port lines. 




General 


Vss 


21 


Ground: V reference. 


VID2to VIDO 


22 to 24 


Digital Video bus: Three totem-pole outputs comprising digital RGB (or other colour 
encoding) from the OSD facility. The polarity of these outputs is controlled by a 
programmable register bit (register OSCON; bit Po). 


VCTRL 


25 


Video Control: A totem-pole output indicating whether the OSD facility is currently 
presenting active video on the VID2 to VIDO outputs. Signal is used to control an 
external multiplexer (mixer) between normal video and the video derived from VID2 to 
VIDO. The polarity of this output is controlled by a programmable register bit (register 
OSCON; bit Pc). 



1996 Mar 22 



3-239 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



SYMBOL 


PIN 


DESCRIPTION 


HSYNC 


26 


Horizontal Sync: A dedicated input for a TTL-level version of the horizontal sync 
pulse. The polarity of this pulse is programmable; its trailing edge is used by the OSD 
facility as the reference for horizontal positioning. 


VSYNC 


27 


Vertical Sync: A dedicated input for a TTL-level version of the vertical sync pulse. The 
polarity of this pulse is programmable, and either edge can serve as the reference for 
vertical timing. 


VCLK1 


28 


VCLK1 : Video Clock 1 ; input for the horizontal timing reference for the OSD facility. 


VCLK2 


29 


VCLK2: Video Clock 2; output from the on-chip video oscillator. VCLK1 and VCLK2 
are intended to be used with an external LC circuit to provide an on-chip oscillator. The 
period of the video clock is determined such that the width of a pixel in the OSD is 
equal to the inter-line separation of the raster. 


BF 


30 


Background/Foreground: A totem-pole output which, when VCTRL is active, 
indicates whether the current video data represents a Foreground (LOW) or 
Background (HIGH) dot in a character. This signal can be used to reduce the intensity 
of the background colour and thus emphasize the text. 


XTAL1 


31 


XTAL1 : Input to the inverting (oscillator) amplifier and clock generator circuit that 
provides the timing reference for all 83C055 logic other than the OSD facility. 
XTAL2: Oscillator output terminal for system clock. XTAL1 and XTAL2 can be used 
with a quartz crystal or ceramic resonator to provide an on-chip oscillator. Alternatively, 
XTAL1 can be connected to an external clock, and XTAL2 left unconnected. 


XTAL2 


32 


RST 


33 


Reset: If this pin is HIGH for two machine cycles (24 oscillator periods) while the 
oscillator is running, the MTV is reset. This pin is also used as a serial input to enter a 
test or EPROM programming mode, as on the 87C751. 


V DD 


42 


Power supply: for normal and Power-down operation. 



Notes 

1 . Port 0, Port 1 , and Port 3 pins that have logic 1 s written to them float, and in that state can be used i 
high-impedance inputs. 



5. 



The state of the pin can always be read from the port register by the program. 

P3.0, P3.4, and P3.7 can be externally pulled up as high as +12 V ±5%; while P3.5 and P3.6 have 10 mA drive 
capability. 

For each PWM block, a register bit (register PWMn; bit PWnE; n = to 7) controls whether the corresponding pin 
controlled by the block or by Port 0; Port controls the pin immediately after a reset. Regardless of how each pin 
controlled, it can be externally pulled up as high as +12 V ±5%. 

Any of the Port 1 pins are driven LOW if the corresponding port register bit is written as a logic 0, or for P1 .3 only, 
the TDAC module presents a logic 0. 



1996 Mar 22 



3-240 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
3C055; 87C055 



7 DESCRIPTION OF STANDARD FUNCTIONS 

For a description of the standard functions please refer to 
the "Data Handbook IC20; Section 2: 80C51 Technical 
Description". 

8 INPUT/OUTPUT (I/O) 

The I/O structure of the 83C055 is similar to the standard 
I/O structure in the 80C51 , except for the points described 
in Table 5. 

■ 

9 DESCRIPTION OF DERIVATIVE FUNCTIONS 
9.1 General description 

Although the 83C055 is specifically referred to throughout 
this data sheet, the information applies to all the devices. 
The differences to 80C51 features and the derivative 
functions are described in the following Sections and 
Chapters. 

Figure 1 shows the block diagram of the 83C055. 
9.1.1 Not implemented functions 



• The IP register is not used, and the IE register (address 
A8H) is similar to that on the 80C51 ;see Table 36. 

• The VSYNC input used by the OSD facility can generate 
an interrupt. The active polarity of the pulse is 
programmable (see Section 13.7); interrupt occurs at 
the leading edge of the pulse. 

• Since there is no serial port, there are no interrupts nor 
control bits relating to this interrupt. The interrupts and 
their vector addresses are shown in Table 3. 

• External Interrupt 1 is modified so that an interrupt is 
generated when the input switches are in either direction 
(on the 80C51 , there is a programmable choice between 
interrupt on a negative edge or a LOW level on INT1). 
This facility allows for software pulse-width 
measurement handling of a remote control. 

Table 3 Program Memory address 



I that are not implemented 



Standard fum 
in the 83C055: 

• As Data and Program Memory are not externally 
expan dable on the 83C055, the ALE, EA, and 
PSEN signals are not implemented. 

• Idle mode. 

• Power-down mode. 



EVENT 


PROGRAM MEMORY ADDRESS 


Reset 


000H 


External INTO 


003H 


Timer 


OOBH 


External INT1 


01 3H 


Timer 1 


01 BH 


VSync Start 


023H 



9.1 .3 PCON Register difference 

The PCON register format is shown in Table 4. Bits GF1 
and GFO are general purpose flag bits. 



9.1.2 



Interrupt facilities differences 



Table 4 PCON I 



The interrupt f 
the 80C51 as follows: 



nat (address 87H) 



i differ from those of 








5 






3 


2 


1 





7 


6 












— - — 


— 

I 




GF1 


GFO 







9.1.4 l/OF 
Table 5 I/O ports differences 



I/O 


STANDARD 80C51 


83C055 


PortO 


external memory expansion 


8-bit open-drain bidirectional port; and includes: 
alternative use for PWM outputs 


Port 1 


8-bit general purpose quasi-bidirectional 


4-bit open-drain port, and includes alternative uses 
for analog inputs and a PWM output 


Port 2 


quasi-bidirectional and can be used for external 
memory expansion 


open-drain and general purpose 


Port 3 


quasi-bidirectional; all eight bits have alternate uses 


3 port bits have some of the same alternative uses 
as on the 80C51 but not necessarily on the same 
pins; 5 pins are open-drain and general purpose 



1996 Mar 22 



3-241 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



10 6-BIT PWM DACS 

Figure 3 shows the 6-bit PWM DAC logic circuit, consisting 
of 8 PWMn modules. 

The basic MCU clock is divided by 4 to get a waveform that 
clocks a 14-bit counter which is common to all the PWMs 
(including the 14-bit PWM). This divided clock is hereafter 
called the PWM clock. 

As illustrated in Fig.3, the lower-precision (6-bit) PWMs 
use the least significant part of the 14-bit counter. 

Figure 4 shows the circuit diagram of a 6-bit PWM module. 
Each PWM module has a Special Function Register 
PWMn; n = to 7. The register form at is shown in Table 6. 

■ 

10.1 PWM DAC operation 

Value field PVn5 to PVnO of each PWMn register 
(n = to 7) is compared to the 6 LSBs of the common 
counter (14-bit counter). 



When the value matches, the output flip-flop is cleared, so 
that the output pin is driven LOW. 

When the value rolls over to zero, the output flip-flop is set, 
so that the output pin is released. Thus the output 
waveform has a fixed period of 64 PWM clock cycles; its 
duty cycle is determined by contents of PWMn.5 to 
PWMn.O (PVn5 to PVnO). 

Three of the nine total PWM modules (8 PWMn and the 
14-bit PWM DAC) operate as previously described; for 
three others, both the rising and falling edges of the ( 
are delayed by one PWM clock; for the remaining three, 
both edges are delayed by two PWM clocks. This feature 
reduces the radio-frequency emission that would 
otherwise occur when the counter rolled over to zero and 
all nine open-drain outputs were released. 



10.2 Special Function Register PWMn (n = to 7) 

Table 6 Special Function Register PWMn (n = to 7; addresses D4H to DFH) 



7 


6 


5 


4 


3 


2 


1 





PWnE 


- 


PVn5 


PVn4 


PVn3 


PVn2 


PVn1 


PVnO 



Table 7 Description of PWMn bits 



BIT 


SYMBOL 


DESCRIPTION 


7 


PWnE 


PWM module enable bit. If for a particular PWM block (n) the bit: 
PWnE = 1 , then the block is active and controls its assigned port pin. 
PWnE = 0, the corresponding port pin is controlled by the port. 


6 




Reserved. 


5 toO 


PVn5 to PVnO 




Value field for PWMn register. 



1996 Mar 22 



3-242 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video 



83C145; 83C845 
83C055; 87C055 







■ 




ZERO 



1st PWM MODULE (n = 0) 







2nd PWM MODULE (n = 1) 



■ P0.1 



PWM1/P0.1 



3 



3rd to 7th PWM MODULE (n = 2 to 6) 



P0.2to P0.6 
PWM2/P0.2 



g PWM6/P0.6 



J < / > 



6 

LS 6-bits 



14-BIT COUNTER 



8th PWM MODULE <n = 7) 



PWM7/P0.7 



JO: 



*4 



, 14-BIT PWM 

xtal DAC BLOCK 



intern* bus 



Fig.3 6-bit PWM DAC logic circuit. 







PWM module (n) 







ZERO 



> 




6-bit 
COMPARATOR 



6-bits (PVnO to PVn5) 



0) 



PVnO 


PVn1 


PVn2 


PVn3 


PVn4 


PVn5 




PWnE 



internal bus 



(2) 



PWM clock 



I/O port 



PWMn 
I/O pin 



(1) This flip-flop occurs in 5 of the 8 PWMn modules. 

(2) This flip-flop occurs in 3 of the 8 PWMn modules. 



Fig.4 A 6-bit PWM module. 



1996 Mar 22 



3-243 



11.1 14-bit counter 

The 14-bit counter was already mentioned in Section 10. 
The nature of the counter is such that it can achieve a 
stable output value through its MSB, and the value can 
propagate through logic like that shown in Fig.5. The logic 
output can be stable within: 

• one period of the PWM clock (e.g. 250 ns) if 
edge-triggered logic is used to capture the logic output, 
or 

• one phase of the PWM clock (e.g. 125 ns) if a phase of 
the PWM clock is used to capture the logic output. 

The 14-bit (TDAC) counter is a ripple counter (cost and 
die-size reasons). 

The 14-bit PWM DAC is controlled by two special function 
registers TDACL and TDACH. 

1 1 .2 1 4-bit DAC operation 



11.2.2 High precision operation 



hen software wishes to change the 1 4-bit value 
(TDO to TD13), it should first write to TDACL and then 
write to TDACH. Alternatively, if the required precision of 
the duty cycle is satisfied by 6 bits or less, software can 
simply write to TDACH (TD8 to TD13). 

11.2.1 LOW PRECISION OPERATION 

Figure 5 shows that this block includes an 'extra' 14-bit 
latch between TDACL - TDACH and the comparator and 
other logic. The programmed value is clocked into the 
operative latch when the 7 low-order bits of the counter roll 
over to zero, provided that the software is not in the midst 
of loading a new 14-bit value, i.e. it is not between writing 
TDACL and writing TDACH. 

In a similar fashion to the lower-precision PWMs, this 
facility has an output flip-flop that is set when the lower 
7 bits of the counter overflow/wrap. The more significant 
7 bits of the operative latch's programmed value are 
compared for equality against the less significant 7 bits of 
the counter, and the output FF is cleared when they match. 
Thus this output has a fixed period of 128 PWM clock 
cycles, and the duty cycle is determined by the 
programmed value. 



For the higher-precision aspect of this feature, the 7 MSBs 
of the counter are used in a logic block with the 7 LSBs of 
the programmed value. 

The 7 th LSB (binary value 64) of the programmed value is 
ANDed with the 7* MSB (128) of the counter, the 6 th LSB 
of the value is ANDed with the counter's 6 th and 7* MSBs 
being 1 0, and so on through the LSB of the programmed 
value being ANDed with the counter's 7 MSBs being 
1 00000. Then these 7 ANDed terms are ORed. If the 
result is true (logic 1 ) at the time the 7 LSBs of the counter 
match the MSBs of the programmed value, the output is 
forced high for 1 (additional) PWM clock cycle. 

The result is that, if the value-64 bit of the 14-bit value is 
programmed to a logic 1 , every other cycle of 1 28 PWM 
counter clocks has its duty cycle stretched by one counter 
clock; if the value-32 bit is programmed to logic 1 , every 
4 th cycle is stretched, and so on through, if the value-1 bit 
is programmed to logic 1 , one cycle out of each 128 is 
stretched. 

1 1 .2.3 1 4-bit DAC OUTPUT 

Assuming the external integrator can handle all this, the 
net effect is a PWM DAC that has the period of a 7-bit 
design (which makes the integrator easier and more 
feasible to design) with the accuracy of a 14-bit one. 

An obvious prerequisite for such precision is that the load 
on the voltage must be very light, like a single op-amp or 
comparator. 

11.2.3.1 Note 

The TDAC feature differs from the corresponding features 
of predecessor parts in several ways: 

1 . The 14-bit value is functionally composed of major and 
minor portions of 7 bits each. 

2. The 14-bit value is programmed as a contiguous 
multi-register value that can be manipulated 
straight-forwardly via arithmetic instructions. 

3. As discussed for the 6-bit DACs, both of the preceding 
parts had a feature whereby the PWM output could be 
inverted, redundantly with complementing the 14-bit 
value. This feature has been eliminated. 



■ 



1996 Mar 22 



3-244 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



1 1 .3 Special Function Register TDACL 

Table 8 Special Function Register TDACL format (address D2H) 



7 


6 


5 


4 


3 


2 


1 





TD7 


TDO 


TD1 


TD2 


TD3 


TD4 


TD5 


TD6 


Table 9 Description of TDACL bits 


BIT 


SYMBOL 


DESCRIPTION 


7 tOO 


TD7, TDO to TD6 


8 LSBs of the 14-bit value. 


1 1 .4 Special Function Register TDACH 

Table 10 Special Function Register TDACH format (address D3H) 


7 


6 


5 


4 


3 


2 


1 





TDE 




TD13 




TD12 


TD11 


TD10 


TD9 


TD8 


Table 11 Description of TDACH bits 




BIT 


SYMBOL 


DESCRIPTION 


7 


TDE 


Enable bit. 


6 




Reserved. 


5 tOO 


TD13 to TD8 


6 MSBsofthe 14-bit value. 



1996 Mar 22 



3-245 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 







1 



INTERNAL BUS 



TDACL 



3 



14-BIT LATCH 



3E 



7-BIT COMPARATOR 



7> 



14-BIT COUNTER 




Fig.5 14-bit PWM logic circuit. 



1996 Mar 22 



3-246 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and ' 



(MTV) 



83C145; 83C845 
83C055; 87C055 



12 SOFTWARE ANALOG-TO-DIGITAL FACILITY 

Figure 6 shows the software analog-to-digital facility block diagram. The block includes Special Function Register SAD. 

12.1 Special Function Register SAD 

Table 12 Special Function Register SAD format (address D8H) 



7 


6 


5 


4 


3 


2 


1 





VHi 


cm 


CHO 


St 


SAD3 


SAD2 


SAD1 


SADO 



Table 13 Description of SAD I 



BIT 


SYMBOL 


DESCRIPTION 


7 


VHi 


The comparator output bit; bit addressable. 


6 


cm 


The channel field controls which pin, if any, is connected to this facility; see Table 14. 


5 


CHO 


4 


St 


The St bit should be written as a logic 1 in order to initiate a voltage comparison. 


3 toO 


SAD3 to SADO 


4 LSBs of the SAD register. 



12.2 Software ADC operation 

Port pins P1 .0/ADIO to P1 .2/ADI2 can be alternately 
selected as inputs of a linear voltage comparator. The 
other input of the comparator is connected to a 4-bit DAC. 

This DAC is controlled by bits SAD3 to SADO and 
produces a reference voltage: 

nominally 0.1 5625 to 4.84375 V in increments of 

0.3125 V. 

The output of the comparator (HIGH or LOW) can be read 
by the program as the MSB of the SAD register i.e. bit VHi. 

After writing St = 1 , the program should include intervening 
instructions totalling at least 6 machine cycles (72 clock 
periods or 6 us at 12 MHz), before the instruction that 
accesses and tests VHi. 



Table 14 Pin selection: Pl.n/ADIn 



CH1 


CHO 


P1.n/ADIn< 1 > 








none 





1 


P1. 0/ADIO 


1 





P1.1/ADI1 


1 


1 


P1.2/ADI2 



Note 

1 . Port 1 has open-drain drivers which will not materially 
affect an analog voltage as long as any and all pins 
used for software analog-to-digital measurement have 
corresponding logic 1s in the port register; n = 0, 1, 2. 



1996 Mar 22 



3-247 



Philips Semiconductors 



Product specification 



n-w /UTlA 83C145; 83C845 

rs for TV and video (MTV) 83C055" 87C055 



P1.0/ADI0 



I/O PORT 



P1.1/ADI1 



I/O PORT 
— I— 



P1.2/ADI2 



I/O PORT 
1 



ANALOG 
MUX 



internal bus 



VOLTAGE 
COMPARATOR 



>1 



4-BIT 
DAC 



V 



Fig.6 Software analog-to-digital facility. 







■ 



1996 Mar 22 



3-248 



Philips Semiconductors Product specification 

., % -rv/ a -a AnM 83C145; 83C845 

Microcontrollers for TV and video (MTV) 83C055' 87C055 



13 ON SCREEN DISPLAY (OSD) 

Figure 7 shows the OSD block diagram. It shows the CPU 
writing into the 1 28 x 1 display RAM .which is dual-ported 
to allow the CPU to write into it at any time, Including when 
it is being read out by the OSD logic. The 1 0-bit wide data 
coming out of the display RAM is used to access the 
appropriate character in the Character Generator memory 
(6-bits) and to specffy character and display control 
functions (4-bits). 

Timing for the OSD is controlled by the HSYNC, VSYNC, 
and dot clock input VCLK1 . 

13.1 OSD features 

The 83C055 features an advanced OSD function with 
some unique features as described in Sections 13.1.1 to 
13.1.10. 

13.1 .1 User-definable display format 

The OSD does not restrict the user to a fixed number of 
lines with a fixed number of characters per line: 

• Using a fixed number of lines restricts the generation of 
displays that can be differentiated from others that use 
the same chip and places limits on screen content. 

• Using a fixed number of characters per line wastes 
display RAM if a line has less than the full number of 
displayable characters (it has to be padded with 
non-visible characters). 

The OSD on the 83C055 defines a control character: 

• New Line, that has the same function as a Carriage 
Return and Line Feed. 

When the OSD circuitry fetches this character from display 
RAM it stops displaying further characters, waits for the 
next horizontal scan line, and starts displaying the next 
character in display RAM after the New Line character was 
received. 

The number of lines is thus up to the user, within the limits 
of the display and memory, as are the number of 
characters per line. This allows far better control of the 
appearance of the OSD. 

1 3. 1 .2 Colours selectable by character 

Characters can be displayed on a background of the base 
video or a programmable background colour. 
The background colour is selectable by word and the 
choice of background (base video/user programmed 
colour) by character. 



13.1.3 Dual-Ported Display RAM 

The OSD has a true display RAM instead of a character 
line buffer. This display RAM is dual-ported to allow 
updating the display RAM at any time instead of having to 
wait for a vertical retrace. 

Vertical Sync (VSYNC) interrupts are supported if 
flicker-free updates are required. 

1 3. 1 .4 Programmable character size 

• Normal characters are displayed as 18 x 14 bit maps. 

• In an interlaced display: 

- 2 fields are displayed so that one actually sees a 
36 x 1 4 pixel size character. 

- The part has a double height and width mode which 
displays 36 x 28 pixel size bit maps per field. 

• For use in non-interlaced systems, the part has a double 
height mode so that the displayed characters have the 
same pixel size (36 x 14) as on an interlaced display. 

13.1.5 Character shadowing 

When characters are displayed overlaid on a background 
of base video, a black border around the characters makes 
them highly legible. This feature is called shadowing. The 
83C055 has 8 shadowing modes to allow the user to select 
various partial shadow modes as well as full surround 
shadow; see Fig.8 and Table 28. 

13.1.6 Programmable polarities 

Inputs to and outputs from the OSD can be programmed 
to be recognized as active LOW or HIGH. In conjunction 
with the 1 2 V outputs, this allows direct interfacing to most 
video signal processing circuits. 

13.1.7 Character Generator memory in EPROM 

On the 87C055, the Character Generator memory is in 
EPROM. This feature allows quick and inexpensive font 
development and refinement against the alternative of 
creating a masked ROM version to see how the final fonts 
will appear. 

13.1 .8 HSYNC LOCKED DOT CLOCK OSCILLATOR 

The 83C055 is designed to use an LC oscillator circuit that 
is started at the trailing edge of HSYNC and stopped at its 
leading edge. In practice, this gives a highly consistent 
delay from HSYNC to oscillator start and is stable from 
scan line to scan line so that no left margin effects are 
seen. 



1996 Mar 22 



3-249 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



13.1.9 Short Rows 

This mode only displays 4 horizontal lines and is used for 
generating underlines. 

13.1.10 Programmable horizontal and vertical 
positions 

Bit pairs HS4 to HSO and VS2 to VSO in register OSORG 
(Table 30) define the starting point of the display. 

13.2 General description of the OSD module 

This block is the largest of the additions that are specific to 
this product. Its basic function is to superimpose text on 
the television video image, to indicate various parameters 
and settings of the receiver or tuner. External circuitry 
handles the mixing (multiplexing) of the text and the TV 
video. The OSD block has 4 input pins: 

• Two for a video clock: VCLK1 and VCLK2 

• Horizontal sync signal: HSYNC 

• Vertical sync signal: VSYNC. 
The block has 4 outputs: 

• 3 colour video signals 

• a control signal. 

Since this block is the major feature of the part, its main 
inputs and outputs are dedicated pins, without alternate 
port bits. The OSD of the 83C055 differs from that in 
preceding devices in one major way: 

• It does not fix the number and size of displayed rows of 
text. 

Several predecessor parts allowed two displayed rows of 
1 6 characters each. The 83C055 sim ply has 1 28 locations 
of Display RAM, each of which can contain: 

• a displayed character, or 

• a New Line character that indicates the end of a row. 
A variant of the New Line character is used to indicate 
the end of displayed data. 

A number of changes in the OSD architecture have 
reduced the number of other Special Function Registers 
involved in the feature, below the number needed with 
predecessor devices: 

1 . The elimination of certain options such as 4, 6, or 
8 x character sizes and alternate use of two of the 
video outputs. 

2. The moving of certain other options from central 
registers to Display RAM, such as foreground colour 
codes (Fcolor) and background (B) selection. 



Figure 7 shows the 3 major elements of the OSD facility: 

• OSD logic 

• Display RAM 

lor ROM. 



13.3 OSD logic 



For a standard NTSC TV signal with an HSYNC frequency 
of 1 5.750 kHz and a VSYNC frequency of nominally 

'ne H ava?a e bl are "° "* * h ° riZ ° nta ' 



A typical pixel clock frequency is 8 MHz, and therefore 
roughly 400 pixels of resolution can be obtained. At 
14 dots per character, this means 28 character per 
horizontal scan line. If the 12 dot per character display 
mode is used, that means 33 character per horizontal scan 
line. Allowing for edge effects, 26 characters (1 4 across) or 
31 characters (12 across) can be displayed. 

Note that VGA rates and higher can be used. The 
minimum character dot size will be a function of the VGA 
frequency used. For a 640 x 480 display, running at 
33 kHz, the equivalent 83C055 pixel resolution is about 
160 across (because of the 8 MHz clock and allowing for 
overscan). This means that status and diagnostic 
information can be displayed on video monitors. 

1 3.3. 1 ON-CHIP VIDEO OSCILLATOR 

The video clock pins (VCLK1 and VCLK2) are used to 
connect a LC circuit to an on-chip video oscillator that is 
independent of the normal MCU clock. 

The L and C values are chosen so that a video pulse, of a 
duration equal to the VCLK period, will produce a 
more-or-less square dot on the screen, that is, a dot having 
a width approximately equal to the vertical distance 
between consecutive scan lines. 

The video oscillator is stopped (with VCLK2 = LOW) while: 

• HSYNC (Horizontal Sync) is maintained, and 

• is released to operate at the trailing edge of HSYNC. 

This technique helps provide uniform horizontal 
positioning of characters/dots from one scan line to the 
next. 



1996 Mar 22 



3-250 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



13.4 Character Generator ROM 

Character Generator ROM. Containing 60 displayable bit 
maps, i.e. 64 minus 4, comprising: 

• One for each of new line: New Line, and 

• Three space characters: 

- Space 

- BSpace 

- SplitBSpace. 

Each bit map includes 1 8 scan lines by 14 dots. 

The Character Generator ROM is maskable or 
programmable along with the Program ROM to allow for 
various character sets and languages. 



13.5 Display RAM organization 

Each Display RAM location includes: 

• 6 data bits, and 

• 4 attribute bits. 

The 6 data bits from Display RAM, along with a 
line-within-row count, act as addresses into the Character 
Generator ROM. Except in special test modes that are 
beyond the scope of this data sheet, Display RAM cannot 
be read by the MCU program. 



HSYNC- 
VSYNC- 



OSD LOGIC 



internal 
bus 



OSD RAM 
128 x 10 



ATTRIBUTE 
CONTROL 



.-T6 

Az 



CHARACTER 
GENERATOR 
ADDRESS LOGIC 



CHARACTER 
GENERATOR 
60 x 18x 14 



- VCLK2 
-VCLK1 



Fig.7 OSD block diagram. 







3 



3 



— 



RGB 
DIGITAL 
VIDEO OUT 



-VCTRL 



-VID2 



-VID1 



1996 Mar 22 



3-251 



PhiliDS Semiconductors 

13.6 OSD Special Function Registers 

The programming interface to Display RAM is provided by 
three Special Function Registers as shown in Tables 1 5, 
17 and 20. 

Writing OSAT simply latches the attribute bits into a 
register, while writing OSDT causes the data bus 
information, plus the contents of the OSAT register, to be 
written into display RAM. 

Thus, for a given Display RAM location, OSAT should be 
written before OSDT. If successive characters are to be 
written into Display RAM with the same attributes, OSAT 



Product specification 

need not be rewritten for each character, only prior to 
writing OSDT for the first character with those particular 
attributes. 

The OSAT attribute bits associated with the BSpace, 
SplitBSpace and New Line characters (see Table 19) are 
interpreted differently from those that accompany other 
data characters. With BSpace and SplitBSpace, B is 
interpreted as described above, but the 3 colour bits 
specify the background colour (Bcolor) for subsequent 
characters. For BSpace, a change in B and Bcolor 
becomes effective at the left edge of the character's bit 
map. 



13.6.1 Special Function Register OSAD 

Table 15 Special Function Register OSAD (On Screen ADdress; address 9AH) 



7 


6 


5 


4 


3 


2 


1 







OSAD6 


OSAD5 


OSAD4 


OSAD3 


OSAD2 


OSAD1 


OSADO 


Table 16 Desc 


ription of OSA 


} bits 












BIT 


SYMBOL 


DESCRIPTION 


7 






Reserved. 


6 to 


OSAD6 to OSADO 


These 7-bits hold the Display RAM address into which data will be 
loaded. OSAD is automatically incremented by one each time OSDT and 
Display RAM are written to. 



13.6.2 Special Function Register OSDT 

Writing OSDT causes the data bus information, plus the contents of the OSAT register, to be written into display RAM. 
Table 17 Special Function Register OSDT (On Screen DaTa; address 99H) 



7 


6 


5 


4 


3 


2 


1 









OSDT5 


OSDT4 


OSDT3 


OSDT2 


OSDT1 


OSDTO 



Table 18 Description of OSDT bits 



BIT 


SYMBOL 


DESCRIPTION 


7 to 6 




Reserved. 


5 toO 


OSDT5 to OSDTO 


Character data; see Table 19. In reality, there is a potential conflict 
between the timing of a write to OSDT and an access to display RAM by 
the OSD logic for data display. This is resolved by the use of a true 
dual-ported RAM for display memory. 



1996 Mar 22 



3-252 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



Table 19 Special characters related to OSDT register 



SPECIAL CHARACTER 


OSDT5 


OSDT4 


OSDT3 


OSDT2 


OSDT1 


OSDTO 


New Line 


1 


1 


1 


1 





1 


Space (normal) 


1 


1 


1 


1 








BSpace 


1 


1 


1 


1 


1 





SplitBspace 


1 


1 


1 


1 


1 


1 



1 3.6.3 Special function register OSAT 

Table 20 Special Function Register OSAT ( On Screen ATtributes; address 98H) 



WITH OSDT = 


7 


6 


5 


4 


3 


2 


1 





New Line 








E 




SR 


D 


Sh 


BSpace 








B 




BC2 


BC1 


BCO 


SplitBSpace 








B 




BC2 


BC1 


BCO 


Any other character 








B 




FC2 


FC1 


FCO 



tion 



BIT 


SYMBOL 




7 to 5, 3 




Reserved. 


With OSDT = New Line; note 1 


4 


E 


End; If the E bit is 1 , no further rows are displayed on the screen. 


2 


SR 


Short row; If E = and SR = 1 , the next row is a 'short row', i.e. it is only 4 or 8 scan lines high 
rather than 1 8 or 36. Short rows can be used for underlined text. 


1 


D 


Double height; If E = and D = 1 , all of the characters in the following row are displayed with 
'double height and width'. 





Sh 


Shadowing; If E = and Sh = 1 , all of the characters in the following row are displayed with 
'shadowing'; see Section 13.8. 


With OSDT = BSpace or SplitBspace; note 2 


4 


B 


Background; B indicates whether 'background pixels' should show the current background 
colour (B = 1), or television video (B = 0). 


2 toO 


BC2 to BCO 


Bcolor: Background colour (notes 3 and 4; see Table 22). 


With OSDT = Any other character 


4 


B 


Background; B indicates whether 'background pixels' should show the current background 
colour (B = 1), or television video (B = 0). 


2 toO 


FC2 to FCO 


Fcolor: Foreground colour. Fcolor indicates the colour of foreground pixels' in the ROM bit 
map for this character (see Table 22). 



1996 Mar 22 



3-253 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



Notes to the description of OSAT bits 



1. 



The latches in which the E,SR, D, and Sh bits are captured are cleared to zero at the start of each vertical scan. This 
means that if the first text line on the screen is a short row, or if it contains either double size or shadowing, the text 
must be preceded by a New Line character. Like all such characters, this initial New Line advances the vertical 
screen position; the VStart value (see register OSORG; Section 13.9) should take this fact into account. 

For SplitBSpace, a change in B and Bcolor occurs halfway through the character horizontally. 

The normal Space character has no effect on the Bcolor value. 

The Bcolor value is not cleared between vertical scans, so that if a single background colour is all that is needed in 
an application, it can be set via a single BSpace character during program initialization, and never changed 
thereafter. In order for such a BSpace to actually affect the 83C055 internal Bcolor register the Mode field of the 
OSMOD register must be set to '01 B' (or higher) so that the OSD hardware is operating (see register OSMOD; 
Section 13.8). 



Table 22 OSD outputs related to character bit map value, Fcolor, Bcolor and B bits 



CHARACTER BIT MAP VALUE 


OSD OUTPUTS (notes 1 and 2) 


VID2 


VID1 


VIDO 


VCTRL 


logic 1 


FC2 


FC1 


FCO 


driven active 


logic 


BC2 


BC1 


BCO 


B 


Notes 











Bcolor (BC2.BC1 ,BC0) values '000' and '1 1 1 ' minimize the occurrence of transient states among the VID2 to VIDO 
outputs. 

The background colour defined by the most recently encountered BSpace or SplitBSpace character is maintained 
on the VID2 to VIDO pins except at the following times: 

a) During the active time of HSYNC. 

b) During the active time of VSYNC. 

c) During those pixels of an active character that correspond to a logic 1 in the character's bit map. 

d) During a 'shadow' bit. 



1996 Mar 22 



3-254 



Philips Semiconductors Product specification 

-rw /MTlft 83C145; 83C845 

Microcontrollers for TV and video (MTV) 83C055" 87C055 



13.7 OSD Control Register OSCON 

Table 23 OSD Control Register OSCON (address COH) 



7 


6 


5 


4 


3 


2 


1 





IV 


Pv 


Lv 


Ph 


Pc 


Po 


DH 


BFe 







BIT 


SYMBOL 


DESCRIPTION 


7 


IV 


Interrupt flag for the OSD feature. Bit IV is set by the leading edge of the VSYNC pulse, 
and is cleared by the hardware when the VSYNC interrupt routine is vectored to. It can 
also be set or cleared by software writing a logic 1 or logic to this bit. 


6 


Pv 


Pv defines the active VSYNC input polarity. If Pv = 0, then VSYNC input is active HIGH; 
if Pv = 1 , then VSYNC input is active LOW. 

One effect of bit Pv is that the VI D2 to VI DO and VCTRL outputs are blocked (held at 
black/inactive) during the active time of VSYNC. The IV bit is set on the leading edge of 
the VSYNC pulse; thus Pv controls whether the OSD interrupt occurs in response to a 
HIGH-to-LOW or LOW-to-HIGH transition on VSYNC. 


5 


Lv 


Lv defines the active edge of VSYNC. The active edge (leading or trailing) of VSYNC 
(as defined by Pv), clears the state counter which determines the vertical start of on 
screen data. Time reference for the video field is the leading edge of VSYNC, if Lv = 0, 
or the trailing edge of VSYNC, if Lv = 1 . 


4 


Ph 


Ph defines the active HSYNC input polarity. If Ph = 0, then HSYNC input is active HIGH; 
if Ph = 1, then HSYNC input is active LOW. 


3 


Pc 


Pc defines the active VCTRL output polarity; VCTRL output active means: show the 
colour on VID2 to VIDO. If Pc = 0, then VCTRL output is active HIGH; If Pc = 1 , then 
VCTRL output is active LOW. 


2 


Po 


Po defines the VI D2 to VIDO outputs polarity; bit is needed only because the Shadowing 
feature needs to generate black pixels without reference to a register value. Internally, 
the 3-bit code '000B' always designates black. 

If Po = 0, a logic internal to the 83C055 corresponds to a LOW on one of the 
VID2toVID0 pins. 

If Po = 1 , a logic 1 internal to the 83C055 corresponds to a LOW on one of the 
VID2 to VIDO pins. 


1 


DH 


If DH = 1 , character sizes are doubled vertically but not horizontally. This feature allows 
the 83C055 to be used in 'improved definition' systems that are not interlaced. 
The vertical doubling imposed by DH does not affect the VStart logic as described in 
Table 30; it operates in HSync units regardless of DH or D. 





BFe 


Background/Foreground enable; output BF. If BFe = 1 , then the BF output tracks 
whether each bit in displayed characters is a Foreground bit (LOW), or a Background bit 
(HIGH). If BFe = 0, then the BF pin remains HIGH. 


Note 



It is theoretically possible that a VSYNC interrupt could be missed, or an extra one generated, if OSCON is read, 
then modified internally (e.g. in ACC), and the result written back to OSCON. However, none of the other bits in 
OSCON are reasonable candidates for dynamic change. Special provisions are included in the 83C055 logic so that 
IV will not be changed by a single 'read-modify-write' instruction such as SETB or CLR, unless the instruction 

cno<-ifif alPv rtmnoc l\/ 



specifically changes IV. 



1996 Mar 22 



3-255 



13.8 OSD Control Register OSMOD 

Under some conditions writing to OSMOD while the display is active can cause a temporary flicker during that display 
field. This can be avoided by only writing to OSMOD during the vertical sync interval. 



Table 25 OSD Control Register OSMOD (address C1 H) 



7 


6 


5 


4 


3 


2 


1 





WC 




Model 


Modeo 




SHM2 


SHM1 


SHMO 



Table 26 Description of OSMOD bits (see note ) 



BIT 


SYMBOL 


DESCRIPTION 


7 


Wc 


If Wc = 1 , then each displayed character is horizontally terminated after 
1 2 bits have been output, as opposed to after 1 4 bits if Wc = 0. This 
allows text to be 'packed' more tightly so that more characters can be 
displayed per line. In effect, the 2 bits out of the display ROM, which 
would otherwise be the rightmost 2 of the 1 4, are ignored when Wc is 1 . 
Clearly, if this feature is to be used, it must be accounted for in the design 
of the bit maps in the display ROM. 


6 




Reserved. 


5 


Model 


Display mode select bits; see Table 27. 


4 


ModeO 


3 




Reserved. 


2 toO 


SHM2 to SHMO 


Shadowing mode (ShMode); determines how characters are shadowed 
in rows for which the row attribute Sh = 1 (register OSAT; see Table 21); 
for the shadowing modes see Fig.8 and Table 28. 



Table 27 Selection of Display Modes 



Model 


ModeO 


I 1 

DISPLAY MODE 








Mode The OSD feature is disabled. VCLK oscillator is disabled, VID2 to VIDO are set to black, and 
VCTRL is held inactive.This is the mode to which the 83C055 OSD logic is reset; note 1, 





1 


Mode 1 The VCLK oscillator is enabled and the OSD logic operates normally internally, but 
VID2 to VIDO are set to black and VCTRL is held inactive; note 2. 


1 





Mode 2 Normal OSD operation. Active characters can be shown against TV video (for characters 
with B = 0) or (for characters with B = 1) against a background of the colour defined as an 
attribute of BSpace and SplitBSpace characters. 


1 


1 


Mode 3 Characters can be displayed but all of the receiver's normal video is inhibited by holding 
VCTRL asserted throughout the active portion of each scan line; see note 3. 


Notes 







1 . A direct transition from this mode to 'active display' (Model , ModeO = 1X) would result in undefined operation and 
visual effects for the duration of the current video field (until the next VSYNC). 



2. The OSD feature can be toggled between this state and 'active display' as desired to achieve real-time special effects 
such as 'vertical wiping'. 

3. Since VID2 to VIDO are driven with the current background colour during this time, except during the foreground 
portion of displayed characters, this produces text against a solid background. This mode is useful for extensive 
displays that require user concentration. 



1996 Mar 22 



3-256 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and 



(MTV) 



83C145; 83C845 
83C055; 87C055 



Table 28 Shadowing modes determined by bits SHM2 to SHMO (register OSMOD) and Sh (register OSAT) 



SHM2 


oHMI 




Ch 
oil 


ONAUUWINU MUUt ' 













South-west 








1 




West 





1 







North-west 





1 


1 






North 


1 










North-east 


1 





1 




East 


1 


1 







South-east 


1 


1 


1 




Full surround 


X 


X 


x 





No Shadowing 



Note 

1 . The mode names are based on the position of an apparent light source, ranging from the lower left (South-west) 
clockwise to the lower right (South-east); see Fig.8. 

13.9 OSD Control Register OSORG 

Table 29 OSD Control Register OSORG (address C2H) 



7 


6 


5 


4 


3 


2 


1 





HS4 


HS3 


HS2 


HS1 


HSO 


VS2 


VS1 


vso 



Table 30 Description of OSORG bits (note 1) 



BIT 


SYMBOL 


1 

DESCRIPTION 


7 to 3 


HS4 to HSO 


HStart field; defines the horizontal start position of all the on-screen character rows, as 
approximately a multiple of 4 VCLK clock cycles. Active display begins after the trailing 
edge of HSYNC at the position: 

HP = [4x (HStart) +1] x VCLK clock cycle + (one single-sized character width) 
Where (HStart) is the decimal value of bits (HS4 to HSO); note 2. 


2 toO 


VS2 to VSO 


VStart field; defines the vertical start position of the first on-screen character row, as 
approximately a multiple of 4 HSYNC pulses. Active display begins after the field's time 
reference point (a range of 3 to 3l)at the position: 

VP = [4 x (VStart) - 1] x HSYNC pulses 

Where (VStart) is the decimal value of bits (VS2 to VSO); note 3. 



Notes 
1 



Neither the Hstart nor Vstart parameter is affected by the D line attribute that is used to display double-sized 
characters. 

Counting variations in Wc, there may be 1 7 to 1 43 VCLK clock cycles from the end of HSYNC to the start of the first 
character of each row. 

Subsequent character rows occur directly below the first, such that the last scan line of one row is directly followed 
by the first scan line of the next row. Successive New Line characters (with or without the Short Row designation) 
can be used to vertically separate text rows on the screen. 



1996 Mar 22 



3-257 



Philips Semiconductors 



Product specification 



,. mA 83C145; 83C845 

Microcontrollers for TV and video (MTV) 83C055' 87C055 




ShMode = 010 ShMode = 011 



ShMode = 001 No Shadowing 




ShMode - 100 



ShMode = 101 




source 

L 



ShMode = 000 ShMode=111 ShMode = 110 



Fig.8 Effect of shadowing on the letter 'E'. 



1996 Mar 22 



3-258 



Philips Semiconductors 



Product specification 



Microcontrollers for TV i 



(MTV) 



83C145; 83C845 
83C055; 87C055 



14 PROGRAMMING CONSIDERATIONS 
14.1 EPROM Characteristics 

The 87C055 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices 
such as the 87C751 . It differs from these devices in that a serial data stream is used to place the 87C055 in the 
programming mode. 

Figure 9 shows a block diagram of the programming configuration for the 87C055. 
Table 31 Pin usage for Programming 



PIN 


USAGE 


XTAL1 


Oscillator input and receives the master system clock. This clock should be between 
1.2 and 6 MHz. 


RESET 


Used to accept the serial data stream that places the 87C055 into various programming modes. 
This pattern consists of a 1 0-bit code with the LSB sent first. Each bit is synchronized to the 
clock input, XTAL1. 


Porto 




Vpp/TDAC/PO.O 


Used as the programming voltage supply input (V PP signal). 


PROG/PWM1/P0 1 


Used as the program PROG signal. This pin is used for the 25 programming pulses. 


Port 2 




P2.7tO P2.0 


Address input for the byte to be programmed and accepts both the high- and low-order 
components of the 1 1-bit address; note 1. 


Port 3 




P3.7 to P3.0 


Used as a bidirectional data bus during programming and verify operations. During programming 
mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the 
EPROM location specified by the address which has been supplied to Port 2. 



Note 

1 . Multiplexing of these address components is performed using the ASEL input: 

a) ASEL input is driven HIGH and then drive Port 2 with the high-order bits of the address. ASEL should remain 
HIGH for at least 13 clock cycles. 

b) ASEL may then be driven LOW which latches the high-order bits of the address internally. The high-order address 
should remain on Port 2 for at least 2 clock cycles after ASEL is driven LOW. 

c) Port 2 may then be driven with the low byte of the address. The low-order address will be internally stable 1 3 clock 
cycles later. The address will remain stable provided that the low byte placed on Port 2 is held stable and ASEL 
is kept LOW. 

d) ASEL needs to be pulsed HIGH only to change the high byte of the address. 



1996 Mar 22 



3-259 



Philips Semiconductors 



Product specification 



>ntrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



14.2 Programming operation 

Figures 1 and 1 1 show the timing diagrams for the 
Program/Verify cycle. Programming operation: 

1 . RST should initially be held HIGH for at least 

2 machine cycles. P0.1 (PROG) and PO.O (V PP ) will be 
at V H as a result of the RST operation. At this point, 
these pins function as normal quasi-bidirectional I/O 
ports and the programming equipment may pull these 
lines LOW. However, prior to sending the 10-bit code 
on the RST pin, the programming equipment should 
drive these pins HIGH (V| H ). 

2. The RST pin may now be used as the serial data input 
for the data stream which places the 87C055 in the 
Programming Mode. Data bits are sampled during the 
clock HIGH time and thus should only change during 
the time that the clock is LOW. Following transmission 
of the last data bit, the RST pin should be held LOW. 

3. Next the address information for the location to be 
programmed is placed on Port 2 and ASEL is used to 
perform the address multiplexing, as previously 
described (see Table 31 ; note 1). 

a) At this time, Port 1 functions as an output. 

b) A high voltage V PP level is then applied to the V PP 
input (PO.O). This sets Port 1 as an input port. 

c) The data to be programmed into the EPROM array 
is then placed on Port 3. This is followed by a 
series of programming pulses applied to the PROG 
pin (P0.1). These pulses are created by driving 
P0.1 LOW and then HIGH. This pulse is repeated 
until a total of 25 programming pulses have 
occurred. At the conclusion of the last pulse, the 
PROG signal should remain HIGH. 

4. The V PP signal may now be driven to the V h level, 
placing the 87C055 in the Verify Mode; Port 3 is now 
used as an output port. After four machine cycles 
(48 clock periods), the contents of the addressed 
location in the EPROM array will appear on Port 3. 

5. The next programming cycle may now be initiated by: 

a) Placing the address information at the inputs of the 
multiplexed buffers. 

b) Driving the V PP pin to the V PP voltage level. 

c) Providing the byte to be programmed to Port 3 and 
issuing the 26 programming pulses on the PROG 
pin. 

d) Bringing V PP back down to the Vqh level and 



14.3 Erasure Characteristics 

Erasure of the EPROM begins to occur when the chip is 
exposed to light with wavelengths shorter than 
approximately 4000 Angstroms. Since sunlight and 
fluorescent lighting have wavelengths in this range, 
exposure to these light sources over an extended time 
(about 1 week in sunlight, or 3 years in room level 
fluorescent lighting) could cause inadvertent erasure. 

For this and secondary effects, it is recommended that an 
opaque label be placed over the window. For elevated 
temperature or environments where solvents are being 
used, apply Kapton tape Fluorless (part num ber f~ ' 
equivalent. 

The recommended erasure procedure is exposure to 
ultraviolet light (at 2537 Angstroms) to an integrated dose 
ofatleast15Ws/cm 2 . 

Exposing the EPROM to an ultraviolet lamp of 
1 2000 nW/cm 2 rating for 20 to 39 minutes, at a distance of 
about 1 inch, should be sufficient. Erasure leaves the array 
in an all logic 1s state. 



14.4 Reading Signature Bytes 



The Signature Bytes are read by the same procedure as a 
normal verify of locations 30H and 31 H (the values are 
shown in Table 32) , except that the serial code indicated in 
Table 33 for reading signature bytes should be used. 

Table 32 Programming and Verification codes 



ADDRESS 


CONTENT 


INDICATION 


30H 


15H 


manufactured by Philips 


31 H 


4BH 


87C055 



Table 33 Implementing Program/Verify Modes 



OPERATION 


SERIAL 


P0.1 


P0.0 




CODE 


(PROG) 


(Vpp) 


Program user EPROM 


286H 


_(1> 


Vpp 


Verify user EPROM 


286H 


V| H 


V|H 


Read Signature Bytes 


280H 


V,H 


V| H 



Note 

1 . Pulsed from V !H to V, L and returned to V| H . 



1996 Mar 22 



3-260 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 







A0-A15 

ADDRESS STROBE - 



PROGRAMMING 
PULSES " 

VppA/.H VOLTAGE 
PP ' H SOURCE ■ 

CLK SOURCE - 



RESET 
CONTROL 
LOGIC 



P2.0-2.7 

P0.2/ASEL 

P0.1 

87C055 

POO 

I 

XTAL1 



RESET 



a .8 
<, / DATA BUS 



Fig.9 Programming Configuration. 







XTAL1 



RESET 



J 



min 2 machine 
cycles 



10-bit serial code 



' BITO | BIT 1 | BIT2 | BIT 3 | BIT4 | BITS | BIT 6 | BIT 7 | BIT 8 | BIT9 



] 



undefined | 



Fig.10 Entry into Program/Verify Modes. 



1996 Mar 22 



3-261 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



14.5 EPROM Programming and Verification 

V DD = 5 V ±1 0%; V ss = V; T^t, = 21 to 27 °C. 



SYMBOL 


PARAMETER 


MIN. 


MAX. 


UNIT 


1/tcLCL 


Osrillator/clock freauencv 


1.2 


6 


MHz 


l AVGL 


Addrpss "?Ptuo to PO 1 (PROG1 LOW 








Ighax 


Addrp<;<5 hold after PO 1 (PROG^ HIGH 

nUUI coo I l<JI<J CHIC I I \J. I nvUj 1 1 1 VJI 1 


4Rt^i 






*DVQL 




OOlcLCL 






tGHDX 


Rata hnlrl after Pn 1 (PROG* HIGH 


OOlcLCL 






tsHGL 




l \J 




(IS 


^GHSL 




Vdd hold after PO 1 fPROG} HIGH 

1 Jwlvl C4I L\^l 1 Vs» 1 11 1 « V__J 1 III \JI I 


10 






tGLGH 


P0.1 (PROG) width 


90 


1 1 


|XS 


tAVQV (1) 


Vpp (V DD ) LOW to data valid 




48t CL CL 


(iS 


Ighgl 


P0.1 (PROG) HIGH to P0.1 (PROG) LOW 


10 




(iS 


tsYNL 


PO.O (sync pulse) LOW 


4t C LCL 




[tS 


tSYNH 


PO.O (sync pulse) HIGH 


StcLCL 




us 


tMASEL 


ASEL HIGH time 


13tcLCL 




us 


Ihahld 


Address hold time 


2tCLCL 




(IS 


Ihaset 


Address setup to ASEL 


13tcLCL 




(IS 


tADSTA 


Low address to address stable 


13*CLCL 




(IS 



Note 

1 . Address should be valid at least 24t CLCL before the rising edge of PO.O (V PP ). 



12.75 V 



po.o ry (p-p)j : 



/ 



P0.1 (PROG) 







—I I— "SHGL -J U-feHSL 

25 PULSES 



-*-| 'masel p- 

P0.2 (ASEL) _J 

'haset 



■ TL_n:3ij 

'glgh U- -J -J U- 'ghgl 

98|isMIN 10|isMIN 



r ^ r ' 1 

! )( HIGH ADDRESS ) ^ 







DVGL 



'GHDX 





ADSTA 


r - 


r n 


• 'avqv * 




PORT 3 


INVALID DATA 


)( VALID DATA )( 


DATA TO BE > 
PROGRAMMED j 


f INVALID DATA Y 


VALID DATA 




a verify mode » 




L verify mode ■> 



Fig. 11 PrograrrWerify cycle. 



1996 Mar 22 



3-262 



Philips Semiconductors Product specification 

83C145; 83C845 



M 



icrocontrollers for TV and video (MTV) 83C055; Q?CQ55 



Each character is 1 4 bits wide by 1 8 lines high.A character 
is split about a vertical axis into two sections UPPER and 
LOWER as illustrated in Table 34: 

• Each section contains 7 bits of the character, such that: 

- the LOWER section contains bits 7 to 1 , and 

- the UPPER section contains bits 14 to 8. 

• The LOWER section of the character is programmed 
when the LSB of the program address equals a logic 0, 
and the UPPER section when the LSB equals a logic 1 . 

During Programming and Verification, each section is 
programmed using bytes of program data. The MSB of the 
program data is not used; however, the MSB location 
physically exists, and so will Program and Verify. 



15.3 OSD EPROM bit map 

The mapping for the full OSD EPROM is shown in Table 35. To program the example character into the first character 
location of the OSD EPROM would require the data at the address as shown in Table 34. 



Table 34 Example of an OSD Character Bit Map (note 1) 





LINE 


CHARACTER BIT MAP 


PROGRAM DATA 


ADDRESS (HEX) 


UPPER 
(BIT 14 TO 8) 


LOWER 
(BIT 7 TO 1) 


UPPER 


LOWER 


UPPER 


LOWER 


Line 1 


0000000 


0000000 


xooooooo 


xooooooo 


C001 


cooo 


Line 2 


0000000 


0000000 


xooooooo 


xooooooo 


C003 


C002 


Line 3 


0011110 


0001100 


X001 1110 


X0001100 


C005 


C004 


Line 4 


0011110 


0001100 


X0011110 


X0001100 


C007 


C006 


Line 5 


0011110 


0001100 


X0011110 


X0001100 


C009 


C008 


Line 6 


0011110 


0001100 


X001 1110 


X0001100 


COOB 


COOA 


Line 7 


0011110 


0001100 


X0011110 


X0001100 


COOD 


COOC 


Line 8 


0011110 


0001100 


X0011110 


X0001100 


COOF 


COOE 


Line 9 


001 1 1 1 1 


1111100 


X001 1111 


X1 1 1 1 1 00 


C011 


C010 


Line 1 


001 1 1 1 1 


1111100 


X001 1111 


X1 1 1 1 1 00 


C013 


C012 


Linen 


001 1 1 1 1 


1111100 


X001 1111 


X1111100 


C015 


C014 


Line 12 


0011110 


0001100 


X001 1110 


X0001100 


C017 


C016 


Line 13 


0011110 


0001100 


X001 1110 


X0001100 


C019 


C018 


Line 14 


0011110 


0001100 


X0011110 


X0001100 


C01B 


C01A 


Line 1 5 


001 1110 


0001100 


X0011110 


X0001100 


C01D 


C01C 


Line 1 6 


0011110 


0001100 


X001 1110 


X0001100 


C01F 


C01E 


Line 17 


0000000 


0000000 


xooooooo 


xooooooo 


C021 


C020 


Line 18 


0000000 


0000000 


xooooooo 


xooooooo 


C023 


C022 



Note 

1 . X can be a logic or logic 1 , and will Program and Verify correctly. 



15 PROGRAMMING THE OSD EPROM 

15.1 Overview 

The OSD EPROM space starts at location C000H and 
ends at location CFFFH. However, due to the addressing 
scheme of the OSD, not all locations within this space are 
used.The start location of the next character can be 
calculated by adding 40H to the start location of the 
previous character. For example, character 1 starts at 
C000H; then characters 2, 3, and 4 start at C040H, 
C080H, and COCOH, respectively. 

15.2 Character description and programming 

An example of an OSD character bit map, and the program 
data to obtain that character is shown in Table 34. 



1996 Mar 22 



3-263 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



Table 35 OSD EPROM Bit Map 



CHARACTER NO. 


ADDRESS (HEX) 


CHARACTER LINE NO. 


LOWER BYTE 


UPPER BYTE 





cooo 


C001 





C002 


C003 




2 


C004 


C005 


3 


C006 


C007 


4 


C008 


C009 


5 


COOA 


COOB 


6 


COOC 


COOD 


7 


COOE 


COOF 


8 


C010 


C011 


9 


C012 


C013 


10 


0014 


C015 


11 


C016 


C017 


12 


C018 


C019 


13 


C01A 


C01B 


14 


C01C 


C01D 


15 










C01E 


C01F 


16 


C020 


C021 


17 


C022 


C023 


18 




C024 to C03F 


not used 


KD 


C040 to C063 




1 to 18 


C064 to C07F 


not used 


2<D 


C080 to C0A3 


_ 

1 to 18 


C0A4 to COBF 


not used 


3 to 59< 1 > 






60< 2 > 


CFOO to CF23 


1 to 18 


CF24 to CF3F 




not used 


61(2) 




CF40 to CF63 


1 to 18 




CF64 to CF7F 


not used 


62<2) 




CF80 to CFA3 


1 to 18 




CFA4 to CFBF 


not used 


63(2> 


CFCO to CFE3 


1 to 18 


CFE4 to CFFF 


not used 



Notes 

1 . Characters 1 to 59 are setup in the similar way as character 0; due 

2. Locations 60, 61 , 62 and 63 should be programmed to logic Os. The 



to space and simplicity this is not fully displayed, 
character names are: character no. 60 = Normal 



1996 Mar 22 



3-264 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



Table 36 Register map 
Values within 



show the bit state after a reset operation; 'X' denotes an undefined state. 



ADDR. 
(HEX) 


REGISTER 




6 


5 


4 


3 


2 


1 





EO 


ACCO) 


A 


ZC7 


ACC6 


ACC5 


ACC4 


ACC3 


ACC2 


ACC1 


ACCO 




(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


FO 


B< 1 > 


B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 








(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


83 


DPH 


DPH7 


DPH6 


DPH5 


DPH4 


DPH3 


DPH2 


DPH1 


DPHO 








(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


82 


DPL 


DPL7 


DPL6 


DPL5 


DPL4 


DPL3 


DPL2 


DPL1 


DPLO 








(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


A8 


IE< 1 > 


EA 


- 


- 


EVS 


ET1 


EX1 


ETO 


EXO 








(0) 


(X) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


9A 


OSAD 






OSAD6 


OSAD5 


OSAD4 


OSAD3 


OSAD2 


OSAD1 


OSADO 




(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


9F to 98 


OSAT< 1 >« 






- 


- 


E 


- 


SR 


D 


Sh 


















(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 




OSAT( 1 >< 3 > 




- 




B 

(X) 




BC2 
(X) 


BC1 

(X) 


BCO 
(X) 




(X) 


(X) 


- 
(X) 


- 

(X) 




OSAT< 1 >< 4 > 








B 




FC2 


FC1 


FCO 








- 


- 


- 






(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


99 


OSDT 






- 


OSDT5 


OSDT4 


OSDT3 


OSDT2 


OSDT1 


OSDTO 






(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


CO 


OSCON< 1 > 




IV 


Pv 


Lv 


Ph 


Pc 


Po 


DH 


BFe 


— 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


C1 


OSMOD 


Wc 


- 


Model 


ModeO 


- . 


SHM2 


SHM1 


SHMO 






(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


C2 


OSORG 


HS4 


HS3 


HS2 


HS1 


HSO 


VS2 


VS1 


VSO 






(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


80 


POO) 


P07 


P06 


P05 


P04 


P03 


P02 


P01 


POO 






(D 


V) 


0) 


(') 


(i) 


(1) 


0) 


0) 


90 


PKD 


P17 


P16 


P15 


P14 


P13 


P12 


P11 


P10 






(1) 


(D 


(1) 


(D 


(1) 


(1) 


0) 


(D 


AO 


P2 m 


P27 


P26 


P25 


P24 


P23 


P22 


P21 


P20 






(D 


(D 


d) 


(D 


(1) 


(D 


(D 


(D 


BO 


P3(D 


P37 


P36 


P35 


P34 


P33 


P32 


P31 


P30 






(D 


(D 


(D 


(1) 


(1) 


(D 


0) 


(1) 


87 


PCON 












GF1 


GFO 










(0) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


(X) 


DO 


PSW< 1 > 


CY 


AC 


FO 


RS1 


RSO 


ov 




P 






(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


D4 


PWMO 


PWOE 
(0) 


(0) 


PV05 
(0) 


PV04 

(0) 


PV03 
(0) 


PV02 
(0) 


PV01 

(0) 


PVOO 
(0) 



1996 Mar 22 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



ADDR. 
(HEX) 


REGISTER 


7 


6 


5 


4 


3 


2 


1 





D5 


PWM1 


PW1E 


- 


PV15 


PV14 


PV13 


PV12 


PV11 


PV10 






(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


(0) 


D6 


PWM2 


PW2E 
(0) 


(0) 


PV25 
(0) 


PV24 
(0) 


PV23 
(0) 


PV22 
(0) 


PV21 

(0) 


PV20 
(0) 


D7 


PWM3 


PW3E 
(0) 


(0) 


PV35 
(0) 


PV34 
(0) 


PV33 
(0) 


PV32 
(0) 


PV31 
(0) 


PV30 
(0) 


DC 




PWM4 


PW4E 
(0) 


(0) 


PV45 
(0) 


PV44 
(0) 


PV43 
(0) 


PV42 
(0) 


PV41 

(0) 


PV40 
(0) 


DD 


PWM5 


PW5E 
(0) 


(0) 


PV55 
(0) 


PV54 
(0) 


PV53 
(0) 


PV52 
(0) 


PV51 
(0) 


PV50 
(0) 


DE 


PWM6 


PW6E 
<0) 


(0) 


PV65 
(0) 


PV64 
(0) 


PV63 
(0) 


PV62 
(0) 


PV61 

(0) 


PV60 
(0) 


DF 


PWM7 


PW7E 
(0) 


(0) 


PV75 
(0) 


PV74 
(0) 


PV73 
(0) 


PV72 
(0) 


PV71 
(0) 


PV70 
(0) 


D8 


SADW 


VHi 
(0) 


cm 

(0) 


CH0 

(0) 


St 
(0) 


SAD3 
(0) 


SAD2 
(0) 


SAD1 

(0) 


SADO 
(0) 


81 


SP 


SP7 
(0) 


SP6 
(0) 


SP5 
(0) 


SP4 

(0) 


SP3 
(0) 


SP2 
(0) 


SP1 

(0) 


SPO 
(0) 


D3 


TDACH 


TDE 

(0) 


(0) 


TD13 
(0) 


TD12 
(0) 


TD11 
(0) 


TD10 
(0) 


TD9 

(0) 


TD8 

(0) 


D2 


TDACL 


TD7 
(0) 


TDO 

(0) 


TD1 

(0) 


TD2 
(0) 


TD3 
(0) 


TD4 

(0) 


TD5 
(0) 


TD6 

(0) 


88 


TCON< 1 ' 


TF1 

(0) 


TR1 

(0) 


TFO 

(0) 


TRO 

(0) 


IE1 

(0) 


IT1 

(0) 


IE0 

(0) 


ITO 
(0) 


8C 


THO 


TH07 
(0) 


TH06 
(0) 


TH05 
(0) 


TH04 
(0) 


TH03 
(0) 


TH02 
(0) 


TH01 

(0) 


THOO 
(0) 


8D 


TH1 


TH17 
(0) 


TH16 

(0) 


TH15 
(0) 


TH14 

(0) 


TH13 
(0) 


TH12 
(0) 


TH11 

(0) 


TH10 

(0) 


8A 


TLO 


TL07 
(0) 


TL06 
(0) 


TL05 
(0) 


TL04 
(0) 


TL03 
(0) 


TL02 
(0) 


TL01 

(0) 


TLOO 
(0) 


8B 


TL1 


TL17 
(0) 


TL16 

(0) 


TL15 

(0) 


TL14 

(0) 


TL13 
(0) 


TL12 
(0) 


TL11 

(0) 


TL10 
(0) 


89 


TMOD 


GATE 
(0) 


err 

(0) 


M1 

(0) 


MO 

(0) 


GATE 
(0) 


C/T 
(0) 


M1 

(0) 


MO 

(0) 


C3 


RAMCHR 


for test purposes only 


C4 


RAMATT 


for test purposes only 



Notes 

1 . Bit addressable. 

2. With OSDT = New Line. 

3. With OSDT = BSpace or SplitBSpace. 

4. With OSDT = Any other character. 



1996 Mar 22 



3-266 



, F .,«,,i!»n»iM • » Ul IU V IUOU ^1 VI I V ) 



83C055; 87C055 



17 LIMITING VALUES 

In accordance with the Absolute Maximum Rating System (IEC 34); see notes 1 and 2. 



SYMBOL 


PARAMETER 


MIN. 


MAX 


UNIT 


Vdd 


supply voltage 


4.5 


5.5 


V 


V, 


input voltage on any pin with respect to ground (Vss) 


-0.5 


6.5 


V 


I OH 


maximum source current for all port lines 




-1.5 


mA 


l0L 


maximum sink current for all port lines 




15 


mA 


Ptot 


total power dissipation 




1.5 


W 


T a mb 


operating ambient temperature 





70 


°C 


T st g 


storage temperature 


-65 


150 


•c 



Notes 



1 . Stresses above those listed under Limiting Values may cause permanent damage to the device. 



2. Parameters are valid over open 
V S s unless otherwise noted 

18 HANDLING 



e unless otherwise specified. All voltages are with respect to 



Inputs and outputs are protected 
normal precautions 



ostatic discharge in normal handling. However it is good practice to take 



to handling MOS devices (see -Handling MOS devices 1 ) 



■ 



1996 Mar 22 



3-267 



Philips Semiconductors 



Product specification 



Microcontrollers for TV and video (MTV) 



83C145; 83C845 
83C055; 87C055 



19 DC CHARACTERISTICS 

V D d = 5 V ±1 0% Tamb = to +70 °C; all voltages with respect to Vss; unless otherwise specified. 



SYMBOL 


PARAMETER 


CONDITIONS 


MIN. 


TYP. 


MAX 


UNIT 


Supply 














Vnn 
* uu 


operating supply voltage 




4.5 


5.0 


5.5 


V 


Idd 


operating supply current 


V DD = 5.5 V; note 1 






30 


mA 


V IL 


LOW level input voltage 




-0.5 




0.2Vqd - 0- 1 


V 


V,L1 


LOW level input voltage; 
VSYNC and HSYNC 




-0.5 


- 


0.15V DD 


V 


V|H 


HIGH level input voltage; 
XTAL, VCLK1 and RST 




0.7V DD 




V DD + 0.5 


V 


V|H1 


HIGH level input voltage; P1 .2 to P1 .0, 
P3.6 to P3.5 and P3.3 to P3.1 




0.2V DD + 0.9 




V DD + 0.5 


V 


V|H2 


HIGH level input voltage; 
P1.3, P3.7,P3.4and P3.0 




0.2V DD + 0.9 




12.6 


V 


V,H3 


HIGH level input voltage; VSYNC and 
HSYNC 




0.67V DD 




V DD + 0.5 


V 


Vih - V DD 


HIGH level input voltage with respect 
ro Vqq, rorc U, rl.o, ro./, ro.4 ana 
P3.0 


note 2 


0.7V DD 


- 


V DD + 0.5 


V 


«OL1 


luw level output voltage, P2.7 to P2.0 
and P3.6 to P3.5 


Iol = 10 mA; note 3 






0.5 


V 


V L2 


LOW level output voltage; 
TDAC and PWMO to PWM7 


Iol = 700 nA; note 4 






0.5 


V 


V L3 


LOW level output voltage; all other 
outputs 


Iol = 1-6 mA 






0.45 


V 


VoH 


HIGH level output voltage; 

Port 1, VID2 to VIDO, VCTRL and BF 


Ioh = -60 nA 


2.4 






V 


Rrst 


Reset (RST) pull-down resistor 




50 




300 


kQ 


C| 


Pin capacitance; except PO O and P0.7 


test freq. = 1 MHz; 
Tamb = 25 °C; note 5 






10 


PF 


HYS 


Hysteresis; VSYNC and HSYNC 




0.8 






V 



Notes 

1 . I do measured with OSD block initialized and RST remaining LOW. 

2. This maximum applies at all times, including during power switching, and must be accounted for in power supply 
design. During a Power-on process, the +12 V source used for external pull-up resistors should not precede the V DD 
of the 83C055 up their respective voltage ramps by more than this margin, nor, during a Power-down process, should 
V DD precede +12 V down their respective voltage ramps by more than this margin. 

3. No more than 6 (any 6) of these 1 high current outputs may be used at the Vou Ool = 1 mA) specification. 
The other 4 should comply with the V i_3 specification (l i_ = 1 -6 mA). 

4. The specified current rating applies when any of these pins is used as a Pulse Width Modulated (PWM) output. 
For use as a port output, the rating is as given subsequently. 

5. The capacitance of pins POO and P0.7 for the 87C055 exceeds 1 pF; for PO.O this is maximum 40 pF, while for P0.7 
it is maximum 20 pF. 



1996 Mar 22 



3-268 



Philips Semiconductors 



Product specification 



Mil 



83C145; 83C845 



>r TV and video (MTV) 



20 AC CHARACTERISTICS 

V D d = 5 V ±1 0%; Tamb = to +70 °C; all voltages with respect to Vssl unless otherwise specified. 



SYMBOL 


PARAMETER 


CONDITIONS 


MIN. 


TYP. 


MAX. 


UNIT 


VtcLCL 


XTAL frequency 


note 1 


6 


- 


12 


MHz 


tcHCX 


XTAL1 clock HIGH time 


note 2 


20 






ns 


fCLCX 


XTAL1 clock LOW time 


20 






ns 


'CLCH 


XTAL1 clock rise time 






20 


ns 


tcHCL 


XTAL1 clock fall time 


5 




20 


ns 


1/tvCLCL 


VCLK frequency 




5 




8 


MHz 


IVcoh -'vcolI 


Rise versus fall time skew on any one of 
VI D2 to VI DO, VCTRL and BF 


note 3 






40 


ns 


I'VCOHI -*VC0H2l 


Rise time skew between any two of 
VID2 to VIDO, VCTRL and BF 






30 


ns 


|WcOL1 -VCOL2I 


Fall time skew between any two of 
VI D2 to VIDO, VCTRL and BF 






30 


ns 



Notes 

1 . The 83C055 is tested at its maximum XTAL frequency, but not at any other (lower) rate 

2. These parameters apply only when an external clock signal is used. 

3. These parameters assume equal loading at C L = 1 00 pF, for all the referenced outputs. These parameters are 
specified but not tested. 



1996 Mar 22 



3-269 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 
— — 



80CL41 




DESCRIPTION 

The 80CL410/83CL410 (hereafter genetically 
referred to as 8XCL41 0) is manufactured in 
an advanced CMOS process that allows the 
part to operate at supply voltages down to 
1 .8V and oscillator frequencies down to DC. 
The 8XCL410 has the same instruction set 
sthe 80C51. 



1 8XCL41 features a 4k byte ROM 
CL410), 128 bytes RAM (both ROM and 
RAM are externally expandable to 64k 
bytes), four 8-bit ports, two 16-bit 
timer/counters, an l 2 C serial interface, a 
thirteen source, two priority level nested 
interrupt structure, and on-chip oscillator 
circuitry suitable for quartz crystal, ceramic 
resonator, RC, or LC. 

The 8XCL410 has two reduced power modes 
that are the same as those on the standard 
80C51 . The special reduced power feature of 
this part is that it can be stopped and then 
restarted. Running from an external clock 
source, the clock can be stopped and after a 
period of time restarted. The 8XCL41 will 
resume operation from where it was when the 
code stopped with no loss of internal state, 
RAM contents, or Special Function Register 
contents. If the internal oscillator is used the 
part cannot be stopped and started, but the 
power-down mode, which can be terminated 
via an interrupt, can be used to achieve 
similar power savings and then restart 
without loss of on-chip RAM and Special 
Function Register values. 



FEATURES 

• Single supply voltage 1 .8V to 6.0V 

• Frequency from DC to 12MHz 

• 80C51 based architecture 

- 4k x 8 ROM (64k external) 

- 1 28 x 8 RAM (64k external) 

- Four 8-bit I/O ports 

- Two 16-bit timer/counters 

- A thirteen-source, two-level, nested 
priority interrupt structure 

- 10 external interrupts 

• Fully static 80C51 CPU 

• l 2 C Serial Interface 

• Two power control modes 

- Idle mode 

- Power-down mode - can be terminated 
by reset or external interrupt 

• Wake-up via external interrupts at port 1 

• Single supply voltage 1 .8V to 6.0V 

• Frequency range of DC to 12MHz 

• On-chip oscillator (quartz crystal, ceramic 
resonator, RC, LC) 

• Very low power consumption 

• Operating temperature range: 
-40to+85°C 



PIN CONFIGURATION 



HT2/P1.0[7 
INT3/P1.l[T 
INT4/P1.2[T 
INTSP1.3[7 
INT6rt>1.4[7 
IMT7/P1^[T 
SCL/1NTOP1.6(T 
1.7 [7 

hst[T 

P3.l[jl 
fWTSfP3.2[l2 

inrr/P3j[i3 

TOP3.4[l4 
T1/P3iQ| 

WH/pisQe 
BD/P3.7Q7 

XTAL2 [|8 

XTAL1 [jg 
vssH 



DIP 

vso 



P0.0/AD0 

P0.1/AD1 

P0.2/AD2 

P0.3/AD3 

P0.4/AD4 

P0.5/AD5 

P0.6/AD6 

P0.7/AD7 

EX 

ALE 

PSEN 

P2.7/A15 

P2.6/A14 

P2.5/A13 

P2.4/A12 

P2.3/A11 

P2.2/A10 

P2.1/A9 




SEE NEXT PAGE FOR QFP PIN FUNCTIONS. 



ORDERING CODE 



PHILIPS PART ORDER NUMBER 
PART MARKING 


PHILIPS NORTH AMERICA 
PART ORDER NUMBER 1 


TEMPERATURE °C 
AND PACKAGE 


FREQUENCY 


Drawing 
Number 


ROMIess 


ROM 


ROMIess 


ROM 


P80CL410HFP 


P83CL410HFP 


P80CL410HFN 


P83CL410HFN 


-40 to +85, 
40-Pin Plastic Dual In-line Package 


32kHZ to 12MHz 


SOT129-1 


P80CL410HFT 


P83CL410HFT 


P80CL410HFD 


P83CL410HFD 


-AO to +85, 
40-Pin Plastic Very Small Outline 
Package 


32kHZ to 12MHz 


SOT158-1 




P83CL410HFH 






-40 to +85, 
44-Pin Plastic Quad Flat Pack 


32kHZto 12MHz 


SOT307-2 



NOTE: 

1 . Parts ordered by the Philips North America part number will be marked with the Philips part marking. 



For emulation purposes, the P85CL000 (Piggyback version) with 256 bytes of RAM is recommended. 



1995 Jan 20 



3-270 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 



PLASTIC QUAD FLAT PACK 
PIN FUNCTIONS 



O 



9 
10 



15 
16 
17 



2, 



34 

JL 



33 
34 
35 
36 
37 
38 



42 
43 



2.5/A13 
P2.6/A14 
P2.7/A15 
P5EN 

Sc E 
EA" 

P0.7/AD7 
P0.6/AD6 



P0-3/AD3 
P0.2/AD2 
P0.1/AD1 
POO/ADO 

VDD 
NC 

P1.0/1NT2 
P1.1/1NT3 
P1.2/1NT4 
P1.3/INT5 



LOGIC SYMBOL 



P1.4/1NT6 



VDD v ss 



RST - 
ES- 



1NT0- 
[NTT- 
T0- 
T1 - 
WR< 
PTB-4 



INT2 
INT3 
INT4 
INT5 
INT6 
INT7 

INT8/SCL 
INT9/SDA 



1995 Jan 20 



3-271 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 



BLOCK DIAGRAM 



XTAL2 XTAL1 






SCILLATO 
AND 
TIMING 


R 










CPU 





I 



INTERNAL 
INTERRUPTS 



PROGRAM 
MEMORY 
(4K X 8 ROM) 



7^ 



DATA 
MEMORY 
(128 X 8 RAM) 



64K BYTE BUS 
EXPANSION 
CONTRTOL 



-A 



Iz 



PROGRAMMABLE I/O 



(1) Pins shared with parallel port pins. 



COUNTER (1) 



TWO 16-BIT 
TIMER/EVENT 
COUNTERS 



7^ 



l 2 C-BUS SERIAL I/O 



■ 




1995 Jan 20 



3-272 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 



PIN DESCRIPTION 



MNEMONIC 


PIN NO. 


Urr 


DIL40/ 
VSO40 


Vss 


16 


20 


Vdd 


38 


40 


PO.0-0.7 


30-37 


39-32 


P1.0-P1.7 


40-44 


1-8 




1-3 








7 






Q 






I — O 


P2.0-P2.7 


18-25 


21-28 


P3.0-P3.7 


5,7-13 


10-17 




8 


12 




9 


13 




10 


14 




11 


15 




12 


16 




I O 


H -J 


RST 


4 


9 


ALE 


27 


30 




26 


29 


ES 


29 


31 


XTAL1 


15 


19 








XTAL2 


14 


18 



TYPE 



NAME AND FUN 



I/O 



I/O 



I/O 
I/O 

-It. 

I/O 



I/O 



I 
I 

I 
I 

o 
o 



Ground: 0V reference. 

Power Supply: This is the power su| 
operation. 



voltage fo normal, idle, and power-down 



Port 0: Port is an open-drain, bidirectional I/O port. Port pins that have 1s written 
to them float and can be used as high-impedance inputs. Port is also the multiplexed 
low-order address and data bus during accesses to external program and data 
memory. In this application, it uses strong internal pull-ups when emitting 1s. 

Port 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that 
have 1 s written to them are pulled high by the internal pull-ups and can be used as 
inputs. As inputs, port 1 pins that are externally pulled low will source current because 
of the internal pull-ups. (See DC Electrical Characteristics: l| L ). Additional functions 
include: 

SCL (P1.6): l 2 C serial bus clock. 
SDA (P1.7): l 2 C serial bus data. 
INT2-INT9 (P1.0-P1.7): Additional external interrupts. 

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that 
have 1s written to them are pulled high by the internal pull-ups and can be used as 
inputs. As inputs, port 2 pins that are externally being pulled low will source current 
because of the internal pull-ups. (See DC Electrical Characteristics: Port 2 emits 
the high-order address byte during fetches from external program memory and during 
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this 
application, it uses strong internal pull-ups when emitting 1s. During accesses to 
external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents 
of the P2 special function register. 

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that 
have 1s written to them are pulled high by the internal pull-ups and can be used as 
inputs. As inputs, port 3 pins that are externally being pulled low will source current 
because of the pull-ups. (See DC Electrical Characteristics: l| L ). Port 3 also serves the 
special features of the 80C51 family, as listed below 
INTO (P3.2): External interrupt 
INTT (P3.3): External interrupt 1 
TO (P3.4): Timer external input 
T1 (P3.5): Timer 1 external input 
WR (P3.6): External data memory write strobe 
RD (P3.7): External data memory read strobe 

Reset: A high on this pin for two machine cycles while the oscillator is running, resets 
the device. An internal diffused resistor to V ss permits a power-on reset using only an 
external capacitor to V D d- 

Address Latch Enable: Output pulse for latching the low byte of the address during 
an access to external memory. In normal operation, ALE is emitted at a constant rate 
of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note 
that one ALE pulse is skipped during each access to external data memory. 

Program Store Enable: The read strobe to external progra m memo ry. When the 
device is executing code from the ex ternal p rogram memory, PSEN is activated twice 
each machine cycle, except that two PS EN activations are skipped during each 
access to external data memory. PSEN is not activated during fetches from internal 
program memory. 

External Access Enable: ES must be externally held low to enable the device to 
fetch code from external program memory locations OO0OH to 0FFFH. If ETA is held 
high, the device executes from internal program memory unless the program counter 
contains an address greater than 0FFFH. 

Crystal 1 : Input to the inverting oscillator amplifier and input for an external clock 
source. 

O | Crystal 2: Output from the inverting oscillator amplifier. 



1995 Jan 20 



3-273 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 



Table 1. 8XCL410 Special Function Registers 



SYMBOL 


DESCRIPTION 


DIRECT 
ADDRESS 


BIT ADDRE 

MSB 


SS, SYMBOL, OR ALTERNATIVE PORT FUNCTION 

LSB 


RESET 
VALUE 


ACC* 


Accumulator 


EOH 


E7 


E6 


E5 


E4 


E3 


E2 


E1 


EO 


00H 


B* 


lj icyioLci 


FOH 


F7 


F6 


F5 


F4 


F3 


F2 


F1 


FO 


00H 


DPTR- 

DPH 
DPL 


Udld pull llcl 

(2 bytes): 
High byte 

luw uyic 


83H 
82H 


















00H 
00H 








BF 


BE 


BD 


BC 


BB 


BA 


B9 


B8 




IPO*# 


Intorn int nriftritv 
ii uei i u(ji piiuiiLy u 


B8H 


_ 


| - 


| PS1 


| - 


| PT1 


| PX1 


PTO 


I PXO 
I — 


wnnnnnnR 








FF 


FE 


FD 


FC 


FB 


FA 


F9 


F8 




IP1 *# 


interrupt pnoniy i 


F8H 


PX9 


| PX8 


| PX7 


| PX6 


| PX5 


| PX4 


PX3 


| PX2 


uun 








AF 


AE 


AD 


AC 


AB 


AA 


A9 


A8 




1EN0*# 


1 1 hoi i up l ci iciuic w 


A8H 


EA 




ES1 


I " 




| EX1 


ETO 


[ EXO 


00H 








EF 


EE 


ED 


EC 


EB 


EA 


E9 


E8 




IEN1*# 


Interrupt enable 1 


E8H 


EX9 


EX8 


| EX7 


| EX6 


| EX5 


EX4 


EX3 


| EX2 


00H 








C7 


C6 


C5 


C4 


C3 


C2 


C1 


CO 




IRQ1*# 


Interrupt request flag 


COH 


IQ9 


IQ8 


IQ7 


IQ6 


I IQ5 


IQ4 


IQ3 
' 


IQ2 


00H 


1X1 # 


Interrupt polarity 


E9H 


















00H 


PO* 


Port 


80H 


87 


86 


85 


84 


83 


82 


81 


80 


FFH 


PI* 


Port 1 


90H 


97 


96 


95 


94 


93 


92 


91 


90 


PPM 

rrn 


P2* 


Port 2 


AOH 


A7 


A6 


A5 


A4 


A3 


AO 

A2 


A1 


AO 


FFH 
rrn 


P3* 


Port3 


BOH 


B7 


B6 


B5 


B4 


B3 


B2 


B1 


BO 


FFH 


PCON 


Power control 


87H 


SMOD | - 


- 


" 


GF1 


GFO 


PD 


IDL 


OxxxOOOOB 








D7 


D6 


D5 


D4 


D3 


D2 


D1 


DO 




PSW 


Program status word 


DOH 


CY 


AC 


FO 


RS1 


RSO 


OV 






00H 


S1ADR# 


Slave address 


DBH 














p 




00H 








DF 


DE 


DD 


DC 


DB 


DA 


D9 


D8 




S1CON*# 


Serial control 


D8H 




ENS1 


STA 


STO 


S, 


AA 


CR1 


CRO 


X0000000B 


S1DAT# 
S1STA# 


Serial data 
Serial status 


DAH 
D9H 


















00H 

11111000B 


SP 


Stack pointer 


81H 


















07H 








8F 


8E 


8D 


8C 


8B 


8A 


89 


88 




TCON* 


Timer/counter con- 
trol 


88H 


TF1 


TR1 


TFO 


TRO 


IE1 


IT1 


IE0 


ITO 


00H 












TMOD 


Timer/counter mode 


89H 


GATE 


C/T 


Ml 


MO 


GATE 


C/T 


M1 


MO 


00H 


THO 


Timer high byte 


8CH 


















00H 


TH1 
TLO 


Timer 1 high byte 
Timer low byte 


8DH 
8AH 


















00H 
00H 


TL1 


Timer 1 low byte 


8BH 


















00H 



# SFRs are modified from or added to the 80C51 SFRs. 



1995 Jan 20 



3-274 



Philips Semiconductors Product specificate 

Low voltage/low power single-chip Qnr . n/Mr . Ai n 

8-bit microcontroller with l 2 C 80CL41 0/83CL41 



PORT OPTIONS 

The pins of port 1 (not P1 .6/SCL or 
P1.7/SDA), port 2, and port 3 may be 
individually configured with one of the 
following port options (see Figure 1): 

Option 1: Standard Port— 

quasi-bidirectional I/O with pull-up. 
The strong booster puli-up p1 is 
turned on for two oscillator periods 
after a 0-to-1 transition in the port 
latch. See Figure 1(a). 

Option 2: Open Drain — quasi-bidirectional 
I/O with n-channel open drain 
output. Use as an output requires 
the connection of an external 
pull-up resistor. See Figure 1(b). 

Option 3: Push-Pull — output with drive 

capability in both polarities. Under 
this option, pins can only be used 
as outputs. See Figure 1 (c). 

The definition of port options for port is 
slightly different. 



Two cases have to be examined. First, 
accesses to external memory (ES = or 
access above the built-in memory boundary), 
and second, I/O accesses. 

External Memory Accesses 

Option 1 : True and 1 are written as 

address to the external memory 
(strong pull-up is used). 

Option 2: An external pull-up resistor is 
needed for external accesses. 

Option 3: Not allowed for external memory 
accesses as the port can only be 
used as output. 

I/O Accesses 

Option 1 : When writing a 1 to the port latch, 
the strong pull-up p1 will be on for 
two oscillator periods. No weak 
pull-up exists. Without an external 
pull-up, this option can be used as 
a high-impedance input. 



Option 2: Open drain — quasi-bidirectional 
I/O with n-channel open drain 
output. Use as an output requires 
the connection of an external 
pull-up resistor. See Figure 1 (c). 

Option 3: Push-Pull — output with drive 

capability in both polarities. Under 
this option, pins can only be used 
as outputs. 

Individual mask selection of the post-reset 
state is available on any of the above pins. 
Make your selection by appending "S" or "R" 
to option 1 , 2, or 3 above (e.g., 1 S for a 
standard I/O to be set after RESET or 2R for 
an open-drain I/O to be reset after RESET. 

Option S: Set— after reset, this pin will be 
initialized High. 

Option R: Reset— after reset, this pin will be 



initialized Low. 











STRONG PULL-UP 
TWO OSCILLATOR PERIODS 



(a) 



FROM PORT LATCH 



I 



INPUT DATA 
READ PORT PIN 




+5V 

EXTERNAL 







<1 



PULL-UP 



BUFFER 



STRONG PULL-UP 



(C) 



Figure 1. Ports 



1995 Jan 20 



3-275 



Philips Semiconductors 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



Product specification 



80CL410/83CL410 



POWER-DOWN MODE 

The instruction setting PCON.1 is the last 
executed prior to going into the power-down 
mode. In power-down mode, the oscillator is 
stopped. The contents of the the on-chip 
RAM and SFRs are preserved. The port pins 
output the values held by their respective 
SFRs. ALE and PSEN are held low. 

In the power-down mode, Vqd may be 
reduced to minimize power consumption. 
However, the supply voltage must not be 
reduced until the power-down mode is active, 
and must be restored before the hardware 
reset is applied and frees the oscillator. Reset 
must be held active until the oscillator has 
restarted and stabilized. 

From the power-down mode the part can be 
restarted by using either the wake-up mode 
or the Reset Mode. 

Wake-Up Mode 

Setting both PD and IDL bits in the PCON 
register forces the controller into the 
power-down mode. Setting both bits enable 
the controller to be woken-up from the 
power-down mode via either an enabled 
external interrupt INT2-INT9, or a reset 
operation. 

An external interrupt for an enabled interrupt 
INT2-INT9 at port 1 starts both the oscillator 
and the delay counter. To ensure that the 
oscillator is stable before the controller 
restarts, the internal clock will remain inactive 
for 1 536 oscillator periods after the interrupt 



is detected. This is controlled by the on-chip 
delay counter. After this, the PD flag will be 
reset, the controller is now in the Idle mode 
and the interrupt will be handled in the normal 
way. 

Reset Mode 

Setting only the PD bit in the PCON register 
again forces the controller into the 
power-down mode, but in this case it can 
only be restored to normal operation with a 
direct reset operation. 

To restore normal operation, the RESET pin 
has to be kept High for a minimum of 24 
oscillator periods. The on-chip delay counter 
is inactive. The user has to insure that the 
oscillator is stable before any operation is 
attempted. Figure 2 illustrates the two 
possibilities for wake-up. 

IDLE MODE 

The instruction that sets PCON.O is the last 
instruction executed before going into idle 
mode. In idle mode, the internal clock is 
stopped for the CPU, but not for the interrupt, 
timer, and serial port functions. The CPU 
status is preserved along with the stack 
pointer, program counter, program status 
word and accumulator. The RAM and all 
other registers maintain their data during idle 
mode. The port pins retain the logical states 
they held at idle mode activation. ALE and 
PSEN hold at the logic high level. 



There are two methods used to terminate the 
idle mode. Activation of any interrupt will 
cause PCON to be cleared by hardware; 
terminating idle mode. The interrupt is 
serviced, and following the instruction RETI, 
the next instruction to be executed will be the 
one following the instruction that put the 
device in the the idle mode. 

Flag bits GFO and GF1 can be used to 
determine whether the interrupt was received 
during normal execution or idle mode. For 
example, the instruction that writes to 
PCON.O can also set or clear one or both flag 
bits. When idle mode is terminated by an 
interrupt, the service routine can examine the 
status of the flag bits. 

The second method of terminating the idle 
mode is with an external hardware reset. 
Since the oscillator is still running, the 
hardware reset is required to be active for 
only two machine cycles to complete the 
reset operation. Reset redefines all SFRs, 
but does not affect the state of the on-chip 
RAM. 

The status of the external pins during idle and 
power-down mode is shown in Table 2. If the 
power-down mode is activated while 
accessing external memory, port data held in 
the special function register P2 is restored to 
port 2. If the data is a logic 1 , the port pin is 
held high during the power-down mode. 



r 



Table 2. External Pin Status During Idle and Power-Down Modes 



MODE 


PROGRAM MEMORY 


ALE 


PSEN 


PORTO 


PORT 1 


PORT 2 


PORT 3 


Idle 


Internal 


1 


1 


Data 


Data 


Data 


Data 


Idle 


External 


1 


1 


Floating 


Data 


Address 


Data 


Power-down 


Internal 








Data 


Data 


Data 


Data 


Power-down 


External 








Floating 


Data 


Data 


Data 



POWER-DOWN 



J~L 











EXTERNAL INTERRUPT j 


< 














I 


f 










> 24 PERIODS 



DELAY COUNTER 
1536 PERIODS 



Figure 2. Wake-Up Operation 



1995 Jan 20 



3-276 



Philips Semiconductors Product 

Low voltage/low power single-chip n/0 o n . Ai n 

8-bit microcontroller with l 2 C 80CL410/83CL410 



SLAVE ADDRESS 



| ARBITRATION LOGIC | 



SHIFT REGISTER 



BUS CLOCK GENERATOR 



7 6 5 4 3 2 1 



_ 



Figure 3. Serial I/O 



l 2 C-BUS SERIAL I/O 

The serial port supports the twin line l 2 C-bus. 
The l 2 C-bus consists of a data line (SDA) 
and a clock line (SCL). These lines also 
function as I/O port lines P1.7 and P1.6 
respectively. The system is unique because 
data transport, clock generation, address 
recognition and bus control arbitration are all 
controlled by hardware. The l 2 C-bus serial 
I/O has complete autonomy in byte handling 
and operates in four modes: 

- Master transmitter 

- Master receiver 

- Slave transmitter 

- Slave receiver 

These functions are controlled by the S1 CON 
register. S1STA is the status register whose 
contents may also be used as a vector to 
various service routines. S1 DAT is the data 
shift register and S1 ADR the slave address 
register. Slave address recognition is 
performed by hardware. 

S1CON (D8H) 

Serial control register 




Assert acknowledge bit. When 
the AA flag is set, an 
acknowledge (low level to SDA) 
will be returned during the 
acknowledge clock pulse on the 
SCL line when: 

- own slave address is received 

- general call address is 
received (S1ADR.0 = 1) 

- data byte received while 
device is programmed as 



- data byte received while 
device is selected slave 

With AA = 0, no acknowledge will 
be returned. Consequently, no 
interrupt is requested when the 
"own slave address" or general 
call address is received. 



CR2 


ENS1 


STA 


STO 


SI 


AA 


CR1 


CRO 



CRO, CR1, CR2 

These three bits determine the 
serial clock frequency when SIO 
is in a master mode. 



SIO interrupt flag. When the SI 
flag is set, an acknowledge is 
returned after any one of the 
following conditions: 

- a start condition is generated 
in master mode 

- own slave address received 
during AA = 1 

- general call address received 
while S1ADR.0 andAA= 1 

- data byte received or 
transmitted in master mode 
(even if arbitration is lost) 

- data byte received or 
transmitted as selected slave 

- stop or start condition received 
as selected slave receiver or 



STO STOP flag. With this bit set while 
in master mode, a STOP 
condition is generated. When a 
STOP condition is detected on 
the bus, the SIO hardware clears 
the STO flag. In the slave mode, 
the STO flag may also be set to 
recover from an error condition. 
In this case, no STOP condition 
is transmitted to the l 2 C-bus. 
However, the SIO hardware 
behaves as if a STOP condition 
has been received and releases 
SDA and SCL. The SIO then 
switches to the "not addressed" 
slave receiver mode. The STO 
flag is automatically cleared by 
hardware. 

STA START flag. When the STA bit is 

set in slave mode, the SIO 
hardware checks the status of 
the l z C-bus and generates a 
START condition if the bus is 
free. If STA is set while the SIO 
is in master mode, SIO transmits 
a repeated START condition. 

ENS1 When ENS1 = 0, the SIO is 
disabled. The SDA and SCL 
outputs are in a high-impedance 
state; P1 .6 and P1 .7 function as 
open drain ports. 

WhenENSI = 1, the SIO is 
enabled. The P1 .6 and P1 .7 port 



set to logic!. 



1995 Jan 20 



3-277 



Philips Semiconductors Product specification 

Low voltage/low power single-chip 80CL41 0/83CL41 

8-bit microcontroller with l 2 C 



S1STA(D9H) 
Status register 



SC4| SC3[ SC2| SCI | SCO | ~ 



S1 STA is an 8-bit read-only special function 
register. S1 STA.3-S1 STA. 7 hold a status 
code. S1STA.0-S1STA.2 are held LOW. The 
contents of S1 STA may be used as a vector 
to a service routine. This optimizes response 
time of the software and consequently that of 
the l 2 C-bus. 

The following is a list of the status codes: 

Abbreviations used: 

SLA: 7-bit slave address 
R: Read bit 
W: Write bit 

ACK: Acknowledgement (acknowledge 
bit = 0) 

ACK: Not Acknowledge (acknowledge 
bit = 1 ) 

DATA: 8-bit byte to or from the l 2 C-bus 
MST: Master 
SLV: Slave 
TRX: Transmitter 
REC: Receiver 

MSTfl-RX mode 

S1 STA value 

08H - a START condition has been 

transmitted 
1 0H - a repeated START condition has 

been transmitted 
18H- SLA and W have been transmitted, 

ACK received 
20H - SLA and W have been transmitted, 

ACK received 
28H - DATA of S1 DAT has been 

transmitted, ACK received 
30H - DATA of S1 DAT has been 

transmitted, ACK received 
38H - Arbitration lost in SLA, WW or DATA 



MST/REC mode 


SLV/TRX mode 


S1 STA value 


ololtt vdl UB 


08H- 


a START condition has been 


A8H - Own SLA and R have been received, 




transmitted 


ACK returned 


10H- 


a repeated START condition has 


BOH - Arbitration lost in SLA, R/W as MST. 




been transmitted 


Own SLA and R have been received, 


38H- 


Arbitration lost while returning ACK 


ACK returned 


40H- 


SLA and R have been transmitted, 


B8H - DATA byte has been transmitted, 




ACK received 


ACK received 


48H- 


SLA and R have been transmitted, 


C0H- DATA byte has been transmitted, 




ACK received 


ACK received 


50H- 


DATA has been received, ACK 


C8H- Last DATA byte has been transmitted 




returned 


(AA = logic 0), ACK received 


58H- 


DATA has been received, ACK 




returned 


Miscellaneous 




S1 STA value 



SLV/REC mode 

S1 STA value 

60H - Own SLA and W have been received, 

ACK returned 
68H - Arbitration lost in SLA, R/W as MST. 

Own SLA and W have been received, 

ACK returned 
70H - General CALL has been received, 

ACK returned 
78H - Arbitration lost in SLA, R/W as MST. 

General CALL has been received 
80H - Previously addressed with own SLA. 

DATA byte received, ACK returned 
88H - Previously addressed with own SLA. 

DATA byte received, ACK returned 
90H - Previously addressed with general 

CALL. DATA byte has been received, 

ACK has been returned 
98H - Previously addressed with general 

CALL. DATA byte has been received, 

ACK has been returned 
AOH - A STOP condition or repeated START 

condition has been received while still 

addressed as SLV/REC or SLV/TRX 



OOH - Bus error during MST mode or 
selected SLV mode, due to an 
erroneous START or STOP condition 

F8H - No relevant state interruption 
available, SI = 0. 

S1 DAT (DAH) 
Data Shift Register 



Data shift register S1 DAT 

This register contains the serial data to be 
transmitted or data that has just been 
received. Bit 7 is transmitted or received first, 
i.e., data is shifted from left to right. 

S1ADR (DBH) 
Slave Address Register 



S1ADR.0, GC: 0= general CALL address is 
not recognized 
1 = general CALL address is 
recognized 

S1ADR.7-1: own slave address 

This 8-bit register may be loaded with the 
7-bit slave address, to which the controller 
will respond when programmed as a slave 
receiver/transmitter. The LSB bit (GC) is used 
to determine whether the general CALL 
address is recognized. 



Table 3. SCL Frequency 



CR2 


CR1 


CRO 


fosc DIVIDED BY 


BIT RATE (kHz) at f OS c 


3.58MHz 


6MHz 


12MHz 











256 


14.0 


23.4 


46.9 








1 


224 


16.0 


26.8 


53.6 





1 





192 


18.6 


31.3 


62.5 





1 


1 


160 


22.4 


37.5 


75.0 


1 








960 


3.73 


6.25 


12.5 


1 





1 


120 


29.8 


50 


100 


1 


1 





60 


59.7 


100 




1 


1 


1 


not allowed 









1995 Jan 20 



3-278 



Philips Semiconductors 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



Product specification 



■ 



80CL410/83CL410 



INTERRUPT SYSTEM 

External events and the real-time-driven 
on-chip peripherals require service by the 
CPU asynchronous to the execution of any 
particular section of code. To tie the 
asynchronous activities of these functions to 
normal program execution, a multiple-source, 
two-priority level, nested interrupt system is 
provided. The 8XCL410 acknowledges 
interrupt requests from thirteen sources, as 
follows: 

- INTO and INT1 

- Timer and timer 1 

- l 2 C-bus serial I/O interrupt 

- INT2tolNT9(port1) 

Each interrupt vectors to a separate location 
in program memory for its service routine. 
Each source can be individually enabled or 
disabled by corresponding bits in the internal 
enable registers (IEN0, IEN1) The priority 
level is selected via the interrupt priority 
register (IPO, IP1). All enabled sources can 
be globally disabled or enabled. 

External Interrupts INT2-INT9 

Port 1 lines serve an alternative purpose as 
eight additional interrupts INT2-INT9. When 
enabled, each of these lines can "wake-up" 
the device from power-down mode. Using the 
1X1 register, each pin may be initialized to 
either active high or low. IRQ1 is the interrupt 
request flag register. Each flag, if the interrupt 
is enabled, will be set on an interrupt request 
but it must be cleared by software. 

IEN0(A8H) 

Interrupt enable register 



IEN1 (E8H) 

Interrupt enable register 



1X1 (E9H) 

Interrupt polarity register 



7 


6 


5 


4 


3 


2 


1 





EA 




ESI 




ET1 


EX1 


ETO 


EXO 



Bit Symbol Function 

IEN0.7 EEA General enable/disable 
control 

= no interrupt is enabled 

1 = any individually enabled 

interrupt will be 
accepted 



IEN0.6 




(unused) 


IEN0.5 


ES1 


Enable l 2 C SIO interrupt 


IEN0.4 




(unused) 


IEN0.3 


ET1 


Enable Timer T1 interrupt 


IEN0.2 


EX1 


Enable external interrupt 1 


IEN0.1 


ETO 


Enable Timer TO interrupt 


IEN0.0 


EXO 


Enable external interrupt 



7 


6 


5 


4 


3 


2 


1 





EX9 


EXS 


EX7 


EX6 


EXS 


EX4 


EX3 


EX2 



Bit Symbol Function 

I EN 1 .7 EX9 Enable external interrupt 9 

IEN1.6 EX 8 Enable external interrupt 8 

I EN 1 .5 EX7 Enable external interrupt 7 

I EN 1 .4 EX6 Enable external interrupt 6 

IEN1.3 EX5 Enable external interrupt 5 

IEN1.2 EX4 Enable external interrupt 4 

IEN1.1 EX3 Enable external interrupt 3 

IEN1.0 EX2 Enable external interrupt 2 

where 0= interrupt disabled 
1 = interrupt enabled 

IPO (B8H) 

Interrupt priority register 



7 


6 


5 


4 


3 


2 


1 









PS1 




PT1 


PX1 


PTO 


PXO 



Bit 

IP0.7 
IP0.6 
IP0.5 

IP0.4 
IP0.3 



PS1 



PT1 



IP0.1 PTO 
IPO.O PXO 



Symbol Function 

— (unused) 

— (unused) 
l 2 C SIO interrupt 
priority level 
(unused) 
Timer 1 interrupt 
prioity level 
External interrupt 1 
priority level 
Timer interrupt 
prioity level 
External interrupt 
priority level 



IP1 (F8H) 
Interrupt priority register 



7 


6 


5 


4 


3 


2 


1 





PX9 


PX» 


PX7 


PX6 


PX5 


PX4 


PX3 


PX2 



IP1.4 
IP1.3 



IP1.0 



Interrupt priority is as follows: 
0- low priority 
1 - high priority 



7 6 


5 


4 


3 


2 


1 





IL9 


IL8 


IL7 


IL6 


IL5 


IL4 


IL3 


IL2 



Bit Symbol Function 

1X1 .7 IL9 External interrupt 9 polarity 
level 

1X1.6 IL8 External interrupt 8 polarity 
level 

1X1.5 IL7 External interrupt 7 polarity 
level 

1X1.4 IL6 External interrupt 6 polarity 
level 

1X1.3 IL5 External interrupt 5 polarity 
level 

1X1.2 IL4 External interrupt 4 polarity 
level 

1X1.1 IL3 External interrupt 3 polarity 
level 

1X1 .0 IL2 External interrupt 2 polarity 
level 

Writing either a "1" or "0" to an 1X1 register bit 
sets the priority level of the corresponding 
external interrupt to active High or Low, 
respectively. 

or 



Bit Symbol Function 

I P1 .7 PX9 External interrupt 9 priority 
level 

IP1.6 PX8 External interrupt 8 priority 
level 

IP1.5 PX7 External interrupt 7 priority 
level 

PX6 External interrupt 6 priority 
level 

PX5 External interrupt 5 priority 
level 

IP1.2 PX4 External interrupt 4 priority 
level 

IP1.1 PX3 External interrupt 3 priority 
level 

interrupt 2 priority 



1995 Jan 20 



3-279 



Philips Semiconductors Product specification 

Low voltage/low power single-chip nr . . 1 n/(nr , A1 n 

8-bit microcontroller with l 2 C 80CL41 0/83CL41 



IRQ1 (COH) 

Interrupt request flag register 



7 


6 


5 


4 


3 


2 


1 





ICS 


IQ8 


I07 


IQ6 


K35 


KM 


103 


102 



Bit 


Symbol 


Function 


IRQ1.7 


IQ9 


External interrupt 9 request 






flag 


IRQ1.6 


IQ8 


External interrupt 8 request 






flag 


IRQ1.5 


IQ7 


External interrupt 7 request 






flag 


IRQ1.4 


IQ6 


External interrupt 6 request 


IRQ1.3 


IQ5 


flag 

External interrupt 5 request 


IRQ1.2 


IQ4 


flag 

External interrupt 4 request 






flag 


IRQ1.1 


1Q3 


External interrupt 3 request 




flag 


IRQ1.0 


IQ2 


External interrupt 2 request 






flag 



Priority 


Vector 


Source 


XO (highest) 


0003H 


External 


S1 


002BH 


l 2 C port 


X5 


0053H 


External 5 


TO 


OOOBH 


Timer 


X6 


005BH 


External 6 


X1 


0013H 


External 1 


X2 


003BH 


External 2 


X7 


0063H 


External 7 


T1 


001 BH 


Timer 1 


X3 


0043H 


External 3 


X8 


006BH 


External 8 


X4 


004BH 


External 4 


X9 (lowest) 


0073H 


External 9 







SFR 


Registei 


Function 


Address 


1X1 


Interrupt polarity register 


E9H 


IRQ1 


Interrupt request flag 


COH 




register 




IEN0 


Interrupt enable register 


A8H 


IEN1 


Interrupt enable register 


E8H 




(INT2-INT9) 




IPO 


Interrupt priority register 


B8H 


IP1 


Interrupt priority register 


F8H 




(INT2-INT9) 





OSCILLATOR CIRCUITRY 

The on-chip oscillator circuitry of the 
8XCL410 is a single stage inverting amplifier 
biased by an internal feedback resistor. (See 
Figure 4.) The oscillator can be operated with 
a quartz crystal, ceramic resonator, LC 
network or RC network. See Figure 5 for 
different configurations. When ordering parts, 
it is necessary to specify an oscillator option. 
The options are: RC when an RC network will 
be used, OSC 2 for oscillator operation below 
4MHz, OSC 3 for oscillator operation from 
4MHz to 10MHz, OSC 4 for oscillator 
operation above 10MHz, and 32kHz if 32kHz 
to 400kHz operation is desired. 

For operation as a standard quartz oscillator, 
no external components are needed (except 
at 32KHz). When using external capacitors, 
ceramic resonators, coils, and RC networks 
to drive the oscillator, five different 
configurations are supported (see Figure 5 
and Table 4). 

In the power-down mode the oscillator is 
stopped and XTAL1 is pulled high. The 
oscillator inverter is switched off to ensure no 
current will flow. To drive the device with an 
external clock source, apply the external 
clock signal to XTAL1 , and leave XTAL2 to 
float, as shown in Figure 5(f). There are no 
requirements on the duty cycle of the 
external clock, since the input to the internal 
clocking circuitry is split using a flip-flop. 

The following options are provided for 
optimum on-chip oscillator performance. 
Please state option when ordering: 

Osc.1 : Figure 5(c). An option for 32kHz 
clock applications with external 
trimmer for frequency adjustment. 

A 4.7M£2 bias resistor must be 
connected in parallel with the 
crystal. 

Osc.2: Figure 5(e). An option for low-power, 
low-frequency operations using LC 
components or quartz. 

Osc.3: An option for medium frequency 
range applications. 

Osc.4: An option for high frequency range 
applications. 

RC: Figure 5(g). An option for an RC 
oscillator. 

The equivalent circuit data of the internal 
oscillator compares with that of matched 
crystals. 

The externally adjustable RC oscillator has a 
frequency range from 100kHz to 500kHz. 
(See Figure 7.) 



Power-on Reset 

The 8XCL410 contains on-chip circuitry 
which switch the port pins to the 
customer-defined logic level as soon as Vqd 
exceeds 1 .3V if the mask option "ON" has 
been chosen (see Figures 8 and 9). As soon 
as the minimum supply voltage is reached, 
the oscillator will start up. However, to ensure 
that the oscillator is stable before the 
controller starts, the clock signals are gated 
away from the CPU for a further 1536 
oscillator periods. 

An hysteresis of approximately 50mV at a 
typical power-on switching level of 1 .3V will 
ensure correct operation. 

The on-chip power-on reset circuitry can also 
be switched off via the mask option "OFF". 
This option reduces the power-down current 
to typically 800nA and can be chosen if 
external reset circuitry is used. For 
applications not requiring the internal reset, 
option "OFF" should be chosen. 

An automatic reset can be obtained at 
power-on by connecting the RST pin to Vrjrj 
via a 10nF capacitor. At power-on, the 
voltage on the RST pin is equal to V pu minus 
the capacitor voltage, and decreases from 
V DD as the capacitor discharges through the 
internal resistor Rrst to ground. The larger 
the capacitor, the more slowly Vrst 
decreases. V r st must remain above the 
lower threshold of the Schmitt trigger long 
enough to effect a complete reset. The time 
required is the oscillator start-up time, plus 2 
machine cycles. 



P80CL410: 

ROM-less VERSION OF P83CL410 

The P80CL410 is a low voltage ROMIess 
version of the P83CL410. The mask options 
on the P80CL410 are fixed as follows: 

• Port Options: 

All ports except P16/P17 have option "1S", 
i.e., standard port, High after reset. The 
ports P16/P17 have option "2S", i.e., open 
drain. High after reset. 

• Oscillator option: OSC3 

• Power-on Reset option: OFF 



1995 Jan 20 



3-280 



is Semiconductors Product specification 

Low voltage/low power single-chip 0/83CL41 

8-bit microcontroller with KC 



C1|-- 



i 



^ 



... 



Dscillator 




- 







- 



XTAL1 

_!_ 



IUI — ' 

-- -- 



/77 



(a) Oscillator Configuration for 
Qua"*'* 



(b) Quartz Oscillator with External 
Capacitors 

I . 

i (d) Configuration for 

Ceramic Resonator 



Configuration for 
iperation 




(e) Configuration for 
LC Network 



N.C. 



(f) External Clock 
Configuration 



Vdd 



/77 



(g) RC Network 
Configuration 



Figure 5. Oscillator Configurations 



1995 Jan 20 



3-281 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 



Table 4. Oscillator Type Selection Guide 



RESONATOR f (MHz) OPTION 


C1 EXT. 


C2 EXT. 


MAXIMUM RESONATOR 
SERIES RESISTANCE 


MIN 


MAX 


MIN 


MAX 


Quartz 


0.032 


Osc.1 


5 


15 








15kn 1 


Quartz 


1.0 


Osc.2 





30 





30 


60on 


Quartz 


3.58 


Osc.2 





15 





15 


ioon 


Quartz 


4.0 


Osc.2 





20 





20 


75Q 


Quartz 


6.0 


Osc.3 





10 





10 


60£1 


Quartz 


10.0 


Osc.4 





15 





15 


60n 


Quartz 


12.0 


Osc.4 





10 





10 


40S2 


Quartz 


16.0 


Osc.4 





15 





15 


20£5 


PXE 


0.455 


Osc.2 


40 


50 


40 


50 


ion 


PXE 


1.0 


Osc.2 


15 


50 


15 


50 


100f2 


PXE 


3.58 


Osc.2 





40 





40 


ion 


PXE 


4.0 


Osc.2 





40 





40 


ion 


PXE 


6.0 


Osc.2 





20 





20 


5£2 


PXE 


10.0 


Osc.3 





15 





15 


6f2 
















PXE 


12.0 


Osc.4 


10 


40 


10 


40 


6Q 


LC 




Osc.2 


20 


90 


20 


90 


i0(iH = m 

100(iH = 5fi 
1mH = 75£5 



NOTE: 

1 . 32kHz quartz crystals with a series resistance higher than 1 5kn will reduce the guaranteed supply voltage range to 2.5 to 3.5V. 

Table 5. Oscillator Equivalent Circuit Parameters (see Figure 6) 



PARAMETER 


OPTION 


SYMBOL 


CONDITION 


MIN 


TYP 


MAX 


UNIT 


Transconductance 


Osc.1 


9m 


T = 


= +25°C; V DD = 


4.5V 




15 




US 


Osc.2 


9m 


T = 


= +25°C; VpD = 


4.5V 


200 


600 


1000 


us 




Osc.3 


9m 


T = 


= +25»C; Vrjp = 


4.5V 


400 


1500 


4000 


us 




Osc.4 


9m 


T = 


= +25°C; Vqq = 


4.5V 


1000 


4000 


10000 


us 


Input capacitance 


Osc.1 


Clj 










3.0 




PF 




Osc.2 


Clj 










8.0 




pF 




Osc.3 


Clj 










8.0 




PF 




Osc.4 


C1| 










8.0 




PF 


Output capacitance 


Osc.1 


c2| 










23.0 




pF 




Osc.2 


c2i 










8.0 




PF 




Osc.3 


c2. 










8.0 




PF 




Osc.4 


c2. 










8.0 




PF 


Output resistance 


Osc.1 


R2 










3800 




k£i 




Osc.2 


R2 










65 




kd 




Osc.3 


R2 










18 




ko 




Osc.4 


R2 










5.0 




k£2 



1995 Jan 20 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 




Circuit Diagram 



fosc 

(kHz) 




I 1 1 1 1 1 

2 RC(pB) 4 6 

Figure 7. Frequency as a Function of RC 







SWITCHING 
LEVEL 
PDR 



SUPPLY VOLTAGE 



POWER-ON RESET 
(INTERNAL) 



CPU RUNNING 




START-UP 1536 OSCILLATOR 
TIME PERIODS DELAY 



Figure 8. Power-on Reset Switching Level 



1995 Jan 20 



3-283 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



10|iF 





v cc 


+ 




b 


8XCL410 




RST 




|j "RST 







Figure 9. Recommended Power-on Reset Circuitry 



ABSOLUTE MAXIMUM RATINGS 1, 2> 3 



PARAMETER 


RATING 


UNIT 


Supply voltage 


-0.5 to +6.5 


V 


All input voltages 


-0.5 to V DD +0.5 


V 


DC current into any input or output 


5 


mA 


Total power dissipation 


300 


mW 


Storage temperature range 


-65 to +150 


°C 


Operating ambient temperature range 


-40 to +85 


°C 


Operating junction temperature 


125 


°c 



NOTES: 

1 . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and 
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section 
of this specification is not implied. 

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static 
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V S s unless otherwise 
noted. 



1995 Jan 20 



3-284 



Philips Semiconductors 



Product specification 



Low voltage/low power single-chip 
8-bit microcontroller with l 2 C 



80CL410/83CL410 



DC ELECTRICAL CHARACTERISTICS 

T amb = -40°C to +85°C, V ss = OV 



SYMBOL 



PARAMETER 



TEST 
CONDITIONS 



LIMITS 



MIN 



MAX 



UNIT 



Supply voltage 

RAM retention voltage in power-down mode 



f C LK(see Figure 13) 



1.8 
1.0 



6.0 



Idd 



Power supply current: 

Operating 1 
OSC 1 option 
OSC 2 option 
OSC 2 option 
OSC 3 option 
OSC 4 option 

Idle mode 2 
OSC 1 option 
OSC 2 option 
OSC 2 option 
OSC 3 option 
OSC 4 option 

Power-down mode 3 



f CL K = 32kHz, V DD = 1 .8V, T^ = +25°C 
fcLK = 3.58MHz, V D0 = 3V 
fcLK= 10MHz, V DD = 5V 
f CLK = 12MHz, V DD = 5V 
f CLK = 12MHz, V DD = 5V 

f CL K = 32kHz, V DD = 1 ,8V, T amb = +25°C 
fCLK = 3.58MHz, Vqd = 3V 
f CL K = 10MHz, V DD = 5V 
f 0LK = 12MHz, V DD = 5V 
f CLK = 12MHz, V DD = 5V 

V DD = 1.8V, Tamb = +25°C 



50 

2.5 
14 
16 
20 

25 
1.0 
5.0 
7.0 
8.5 

10 



MA 
mA 
mA 
mA 
mA 

uA 
mA 
mA 
mA 
mA 

HA 



Input low voltage 



Vss 



0.3V DD 



Input high voltage 



0.7V DD 



Vdd 



l0L 



Output sink current, except SDA, SCL 



V DD = 5V, V 0L = 0.4V 
V DD = 2.5V, Vql = 0.4V 



1.6 
0.7 



mA 
mA 



Ioli 



Output sink current, SDA, SCL 



Vdd = 5V, V 0L = 0.4V 



3.0 



mA 



'oh 



Output source current (push-pull options only) 



Vdd = 5V,V 0H = V DD -0.4V 
V DD = 2.5V, V h = V dd - 0.4V 



1.6 
0.7 



mA 
mA 



IlL 



Logical input current, ports 1 , 2, 3 



Vpo = 5V,V, N = 0.4V 
V DD = 2.5V,V, N = 0.4V 



-100 
-50 



HA 
MA 



Itl 



Logical 1 -to-0 transition current, ports 1,2,3 



Vdd = 5V,V in = V D d/2 
Vdd = 2 5V, V in = V D d/2 



-1.0 
-500 



mA 
HA 



Ili 



Input leakage current, port 0, EA 



V SS < V, < Vpp 



±10 



HA 



R RST 



Internal reset pull-down resistor 



10 



kSJ 



NOTES: 

1 . The operating supply current is measured with all output pins disconnected; XTAL1 driven with t r = tf = 10ns; V| U = Vss, Vih = Vdd; XTAL2 
not connected; EA" = RST = Port = V D d; all open drain outputs connected to V S s- 

2. The idle supply current is measured with all output pins disconnected; XTAL1 driven with tr=tf= 1 0ns; Vil = Vss, v ih = v dd; XTAL2 not 
connected; EA" = Port = V D d; RST = V S s; all open drain outputs connected to V S s- 

3. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA" = port = V DD ; RST = V ss ; all open-drain 
outputs connected to V S s- 

4. The RC-oscillator is not implemented in this version. 

5. Circuits with "power-on reset" option "OFF" are tested at V D dmin = 1 -8V, with option "ON" (typically 1 .3V) are tested at V DD min = 2.3V. 



1995 Jan 20 



3-285 



Philips Semiconductors 



Product specification 



)w voltage/low power single-chip 
jntroller with l 2 C 



__410/83CL410 







1.4 






1.2 






1.0 




iDD(mA) 








0.8 












0.6 








■ 




0.4 












0.2 





















































































































































































1.2MHz 
















































































32kHz 
















- 






















1 


2 



Vqq MIN :1.8V 



VddOO 

Typical Operating Current Versus Supply and Frequency (32kHz-1.2MHz) at +25°C 



1995 Jan 20 



3-286 



Philips Semiconductors Product specification 

Low